diff options
| author | Aravind Venkateswaran <aravindh@codeaurora.org> | 2016-03-29 14:25:55 -0700 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-05-03 15:46:30 -0700 |
| commit | 58ace0e3869290844a7828dadc0ebd3134483b59 (patch) | |
| tree | 62186ec66a93a89f8d3f18fad3f5d3633407f85d | |
| parent | b1c169bae4c42fce02f8a7ea2429d3e8f39548d1 (diff) | |
ARM: dts: msm: setup external clock sources for DSI clock on msmcobalt
The DSI RCGs exported by the MMSS clock controller (MMSS-CC)
can be sourced out of the DSI PLL which is outside the MMSS-CC. Set up
these external clock sources to point to the DSI PLL clocks.
CRs-Fixed: 1000756
Change-Id: I2d2e651ba554812198d721892e14ca1a61a34027
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt.dtsi | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index 78c99ee81a12..272cec897720 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -629,10 +629,16 @@ reg = <0xc8c0000 0x40000>; reg-names = "cc_base"; vdd_dig-supply = <&pmcobalt_s1_level>; - clock-names = "xo", "gpll0", "gpll0_div"; + clock-names = "xo", "gpll0", "gpll0_div", + "pclk0_src", "pclk1_src", + "byte0_src", "byte1_src"; clocks = <&clock_gcc clk_cxo_clk_src>, <&clock_gcc clk_gpll0_out_main>, - <&clock_gcc clk_gcc_mmss_gpll0_div_clk>; + <&clock_gcc clk_gcc_mmss_gpll0_div_clk>, + <&mdss_dsi0_pll clk_dsi0pll_pclk_mux>, + <&mdss_dsi1_pll clk_dsi1pll_pclk_mux>, + <&mdss_dsi0_pll clk_dsi0pll_byteclk_mux>, + <&mdss_dsi1_pll clk_dsi1pll_byteclk_mux>; #clock-cells = <1>; }; |