diff options
| author | Sandeep Panda <spanda@codeaurora.org> | 2015-12-14 19:49:01 +0530 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 21:14:17 -0700 |
| commit | 56c024f4f8c54cc8644066479f289ef0efeee3b2 (patch) | |
| tree | 0538cf333432143ca1275776bb047318ba22a50e | |
| parent | 3a37212ae9f542659b68a6914ae1d864fe2623e8 (diff) | |
msm: mdss: update DSI PHY enable sequence based on PHY revision
In the current implementation DSI controller version is used to
determine which PHY enable sequence should be used. But this will
fail in case of platforms where DSI controller version is same as
older platforms but PHY version is new. So change the version check
to be based on PHY version instead for controller version.
Change-Id: I636a6442e84f1bd549b6a125cfb991402e53c796
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
| -rw-r--r-- | drivers/video/fbdev/msm/msm_mdss_io_8974.c | 61 |
1 files changed, 25 insertions, 36 deletions
diff --git a/drivers/video/fbdev/msm/msm_mdss_io_8974.c b/drivers/video/fbdev/msm/msm_mdss_io_8974.c index d38bf4ceed52..a30d73f328c9 100644 --- a/drivers/video/fbdev/msm/msm_mdss_io_8974.c +++ b/drivers/video/fbdev/msm/msm_mdss_io_8974.c @@ -441,10 +441,7 @@ void mdss_dsi_phy_sw_reset(struct mdss_dsi_ctrl_pdata *ctrl) return; } - if (IS_MDSS_MAJOR_MINOR_SAME(ctrl->shared_data->hw_rev, - MDSS_DSI_HW_REV_104) && - (MDSS_GET_STEP(ctrl->shared_data->hw_rev) != - MDSS_DSI_HW_REV_STEP_2)) { + if (ctrl->shared_data->phy_rev == DSI_PHY_REV_20) { if (mdss_dsi_is_ctrl_clk_master(ctrl)) sctrl = mdss_dsi_get_ctrl_clk_slave(); else @@ -481,10 +478,7 @@ static void mdss_dsi_phy_regulator_disable(struct mdss_dsi_ctrl_pdata *ctrl) return; } - if (IS_MDSS_MAJOR_MINOR_SAME(ctrl->shared_data->hw_rev, - MDSS_DSI_HW_REV_104) && - (MDSS_GET_STEP(ctrl->shared_data->hw_rev) != - MDSS_DSI_HW_REV_STEP_2)) + if (ctrl->shared_data->phy_rev == DSI_PHY_REV_20) return; MIPI_OUTP(ctrl->phy_regulator_io.base + 0x018, 0x000); @@ -497,10 +491,7 @@ static void mdss_dsi_phy_shutdown(struct mdss_dsi_ctrl_pdata *ctrl) return; } - if (IS_MDSS_MAJOR_MINOR_SAME(ctrl->shared_data->hw_rev, - MDSS_DSI_HW_REV_104) && - (MDSS_GET_STEP(ctrl->shared_data->hw_rev) != - MDSS_DSI_HW_REV_STEP_2)) { + if (ctrl->shared_data->phy_rev == DSI_PHY_REV_20) { MIPI_OUTP(ctrl->phy_io.base + DSIPHY_PLL_CLKBUFLR_EN, 0); MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_GLBL_TEST_CTRL, 0); MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, 0); @@ -525,10 +516,7 @@ void mdss_dsi_lp_cd_rx(struct mdss_dsi_ctrl_pdata *ctrl) return; } - if (IS_MDSS_MAJOR_MINOR_SAME(ctrl->shared_data->hw_rev, - MDSS_DSI_HW_REV_104) && - (MDSS_GET_STEP(ctrl->shared_data->hw_rev) != - MDSS_DSI_HW_REV_STEP_2)) + if (ctrl->shared_data->phy_rev == DSI_PHY_REV_20) return; pd = &(((ctrl->panel_data).panel_info.mipi).dsi_phy_db); @@ -965,17 +953,17 @@ static void mdss_dsi_phy_regulator_ctrl(struct mdss_dsi_ctrl_pdata *ctrl, mutex_lock(&sdata->phy_reg_lock); if (enable) { - switch (ctrl->shared_data->hw_rev) { - case MDSS_DSI_HW_REV_104: - case MDSS_DSI_HW_REV_104_1: + if (ctrl->shared_data->phy_rev == DSI_PHY_REV_20) { mdss_dsi_8996_phy_regulator_enable(ctrl); - break; - case MDSS_DSI_HW_REV_103: - mdss_dsi_20nm_phy_regulator_enable(ctrl); - break; - default: - mdss_dsi_28nm_phy_regulator_enable(ctrl); - break; + } else { + switch (ctrl->shared_data->hw_rev) { + case MDSS_DSI_HW_REV_103: + mdss_dsi_20nm_phy_regulator_enable(ctrl); + break; + default: + mdss_dsi_28nm_phy_regulator_enable(ctrl); + break; + } } ctrl->is_phyreg_enabled = 1; } else { @@ -1006,17 +994,18 @@ static void mdss_dsi_phy_ctrl(struct mdss_dsi_ctrl_pdata *ctrl, bool enable) } if (enable) { - switch (ctrl->shared_data->hw_rev) { - case MDSS_DSI_HW_REV_104: - case MDSS_DSI_HW_REV_104_1: + + if (ctrl->shared_data->phy_rev == DSI_PHY_REV_20) { mdss_dsi_8996_phy_config(ctrl); - break; - case MDSS_DSI_HW_REV_103: - mdss_dsi_20nm_phy_config(ctrl); - break; - default: - mdss_dsi_28nm_phy_config(ctrl); - break; + } else { + switch (ctrl->shared_data->hw_rev) { + case MDSS_DSI_HW_REV_103: + mdss_dsi_20nm_phy_config(ctrl); + break; + default: + mdss_dsi_28nm_phy_config(ctrl); + break; + } } } else { /* |