diff options
| author | Girish Mahadevan <girishm@codeaurora.org> | 2016-05-26 15:18:15 -0600 |
|---|---|---|
| committer | Kyle Yan <kyan@codeaurora.org> | 2016-06-29 15:02:17 -0700 |
| commit | 538198f2f891efbb3f08ca71240a8c672137ef1f (patch) | |
| tree | 0a3b7df8ae824dc0ca790b6aba53a9502f2b761c | |
| parent | 6e4ffe07abe46a16ffd9c0f77201166399be4911 (diff) | |
ARM: dts: msm: Correct the TLMM IRQs for UART instances
The TLMM IRQ numbers were set incorrectly. This can prevent the UART
peer devices from waking up the core from sleep.
Change-Id: I11e725ac31f78f838ac9b8e1e08c384d11ea14a6
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt-blsp.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-blsp.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-blsp.dtsi index 555c68867ff5..929a079c64c3 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-blsp.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-blsp.dtsi @@ -687,7 +687,7 @@ interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 0 108 0 1 &intc 0 0 238 0 - 2 &tlmm 5 0>; + 2 &tlmm 34 0>; qcom,inject-rx-on-wakeup; qcom,rx-char-to-inject = <0xFD>; @@ -724,7 +724,7 @@ interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 0 109 0 1 &intc 0 0 238 0 - 2 &tlmm 9 0>; + 2 &tlmm 46 0>; qcom,inject-rx-on-wakeup; qcom,rx-char-to-inject = <0xFD>; @@ -761,7 +761,7 @@ interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 0 113 0 1 &intc 0 0 239 0 - 2 &tlmm 1 0>; + 2 &tlmm 54 0>; qcom,inject-rx-on-wakeup; qcom,rx-char-to-inject = <0xFD>; @@ -835,7 +835,7 @@ interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 0 115 0 1 &intc 0 0 239 0 - 2 &tlmm 9 0>; + 2 &tlmm 50 0>; qcom,inject-rx-on-wakeup; qcom,rx-char-to-inject = <0xFD>; |