phy: qcom-ufs: remove support for 28nm phy

As there is no support for UFS in APQ8084 under kernel 3.14, we also
can remove the support for 28nm ufs phy (since APQ8084 is the only
platform that uses this phy).

Change-Id: Iae76f98424842cc29e9397c0050a37a010509bcc
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

3 files changed, 0 insertions, 1072 deletions

diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 8266d404f310..7160f8c5c94c 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -37,7 +37,6 @@ obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
 obj-$(CONFIG_SCSI_UFS_QCOM) 	+= phy-qcom-ufs.o
-obj-$(CONFIG_SCSI_UFS_QCOM) 	+= phy-qcom-ufs-qmp-28nm.o
 obj-$(CONFIG_SCSI_UFS_QCOM) 	+= phy-qcom-ufs-qmp-20nm.o
 obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
 obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-qcom-ufs-qmp-28nm.c b/drivers/phy/phy-qcom-ufs-qmp-28nm.c
deleted file mode 100644
index dd27b4464d3c..000000000000
--- a/drivers/phy/phy-qcom-ufs-qmp-28nm.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
- * Copyright (c) 2013-2014, Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/time.h>
-#include <linux/clk.h>
-#include <linux/of.h>
-#include <linux/iopoll.h>
-#include <linux/platform_device.h>
-#include <linux/msm-bus.h>
-#include <linux/phy/phy.h>
-
-#include <linux/phy/phy-qcom-ufs.h>
-#include "phy-qcom-ufs-qmp-28nm.h"
-
-#define UFS_PHY_NAME "ufs_qcom_phy_qmp_28nm"
-
-static
-void ufs_qcom_phy_qmp_28nm_power_control(struct ufs_qcom_phy *phy, bool val)
-{
-	if (val) {
-		writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
-		/*
-		 * Before any transactions involving PHY, ensure PHY knows
-		 * that it's analog rail is powered ON. This also ensures
-		 * that PHY is out of power collapse before enabling the
-		 * SIGDET.
-		 */
-		mb();
-		if (phy->quirks & UFS_QCOM_PHY_DIS_SIGDET_BEFORE_PWR_COLLAPSE) {
-			writel_relaxed(0xC0,
-				phy->mmio + QSERDES_RX_SIGDET_CNTRL(0));
-			writel_relaxed(0xC0,
-				phy->mmio + QSERDES_RX_SIGDET_CNTRL(1));
-			/*
-			 * make sure that SIGDET is enabled before proceeding
-			 * further.
-			 */
-			 mb();
-		}
-	} else {
-		 if (phy->quirks &
-				UFS_QCOM_PHY_DIS_SIGDET_BEFORE_PWR_COLLAPSE) {
-			writel_relaxed(0x0,
-				phy->mmio + QSERDES_RX_SIGDET_CNTRL(0));
-			writel_relaxed(0x0,
-				phy->mmio + QSERDES_RX_SIGDET_CNTRL(1));
-			/*
-			 * Ensure that SIGDET is disabled before PHY power
-			 * collapse
-			 */
-			mb();
-		}
-		writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
-		/*
-		 * ensure that PHY knows its PHY analog rail is going
-		 * to be powered down
-		 */
-		mb();
-	}
-}
-
-static
-void ufs_qcom_phy_qmp_28nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
-{
-	phy_common->quirks = UFS_QCOM_PHY_QUIRK_CFG_RESTORE
-				| UFS_QCOM_PHY_DIS_SIGDET_BEFORE_PWR_COLLAPSE;
-}
-
-static int ufs_qcom_phy_qmp_28nm_init(struct phy *generic_phy)
-{
-	struct ufs_qcom_phy_qmp_28nm *phy = phy_get_drvdata(generic_phy);
-	struct ufs_qcom_phy *phy_common = &phy->common_cfg;
-	int err = 0;
-
-	err = ufs_qcom_phy_init_clks(generic_phy, phy_common);
-	if (err) {
-		dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
-			__func__, err);
-		goto out;
-	}
-
-	err = ufs_qcom_phy_init_vregulators(generic_phy, phy_common);
-	if (err) {
-		dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
-			__func__, err);
-		goto out;
-	}
-
-	ufs_qcom_phy_qmp_28nm_advertise_quirks(phy_common);
-
-out:
-	return err;
-}
-
-static int ufs_qcom_phy_qmp_28nm_calibrate(struct ufs_qcom_phy *ufs_qcom_phy)
-{
-	struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;
-	int tbl_size_A, tbl_size_B;
-	int rate = UFS_QCOM_LIMIT_HS_RATE;
-	u8 major = ufs_qcom_phy->host_ctrl_rev_major;
-	u16 minor = ufs_qcom_phy->host_ctrl_rev_minor;
-	u16 step = ufs_qcom_phy->host_ctrl_rev_step;
-	int err;
-
-	if ((major == 0x1) && (minor == 0x001) && (step == 0x0000)) {
-		tbl_size_A = ARRAY_SIZE(phy_cal_table_ctrl_1_1_0_rate_A);
-		tbl_A = phy_cal_table_ctrl_1_1_0_rate_A;
-	} else if ((major == 0x1) && (minor == 0x001) && (step == 0x0001)) {
-		tbl_size_A = ARRAY_SIZE(phy_cal_table_ctrl_1_1_1_rate_A);
-		tbl_A = phy_cal_table_ctrl_1_1_1_rate_A;
-	}
-
-	tbl_B = phy_cal_table_rate_B;
-	tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
-
-	err = ufs_qcom_phy_calibrate(ufs_qcom_phy, tbl_A, tbl_size_A,
-			      tbl_B, tbl_size_B, rate);
-	if (err)
-		dev_err(ufs_qcom_phy->dev, "%s: ufs_qcom_phy_calibrate() failed %d\n",
-			__func__, err);
-
-	return err;
-}
-
-static
-u32 ufs_qcom_phy_qmp_28nm_read_attr(struct ufs_qcom_phy *phy_common, u32 attr)
-
-{
-	u32 l0, l1;
-
-	writel_relaxed(attr, phy_common->mmio + UFS_PHY_RMMI_ATTRID);
-	/* Read attribute value for both lanes */
-	writel_relaxed((UFS_PHY_RMMI_CFGRD_L0 | UFS_PHY_RMMI_CFGRD_L1),
-		       phy_common->mmio + UFS_PHY_RMMI_ATTR_CTRL);
-
-	l0 = readl_relaxed(phy_common->mmio + UFS_PHY_RMMI_ATTRRDVAL_L0_STATUS);
-	l1 = readl_relaxed(phy_common->mmio + UFS_PHY_RMMI_ATTRRDVAL_L1_STATUS);
-	/* Both lanes should have the same value for same attribute type */
-	if (unlikely(l0 != l1))
-		dev_warn(phy_common->dev, "%s: attr 0x%x values are not same for Lane-0 and Lane-1, l0=0x%x, l1=0x%x",
-				__func__, attr, l0, l1);
-
-	/* must clear now */
-	writel_relaxed(0x00, phy_common->mmio + UFS_PHY_RMMI_ATTR_CTRL);
-
-	return l0;
-}
-
-static void
-ufs_qcom_phy_qmp_28nm_write_attr(struct ufs_qcom_phy *phy_common,
-				 u32 attr, u32 val)
-{
-	writel_relaxed(attr, phy_common->mmio + UFS_PHY_RMMI_ATTRID);
-	writel_relaxed(val, phy_common->mmio + UFS_PHY_RMMI_ATTRWRVAL);
-	/* update attribute for both lanes */
-	writel_relaxed((UFS_PHY_RMMI_CFGWR_L0 | UFS_PHY_RMMI_CFGWR_L1),
-		       phy_common->mmio + UFS_PHY_RMMI_ATTR_CTRL);
-	if (is_mphy_tx_attr(attr))
-		writel_relaxed((UFS_PHY_RMMI_TX_CFGUPDT_L0 |
-				UFS_PHY_RMMI_TX_CFGUPDT_L1),
-			       phy_common->mmio + UFS_PHY_RMMI_ATTR_CTRL);
-	else
-		writel_relaxed((UFS_PHY_RMMI_RX_CFGUPDT_L0 |
-				UFS_PHY_RMMI_RX_CFGUPDT_L1),
-			       phy_common->mmio + UFS_PHY_RMMI_ATTR_CTRL);
-
-	writel_relaxed(0x00, phy_common->mmio + UFS_PHY_RMMI_ATTR_CTRL);
-}
-
-static
-void ufs_qcom_phy_qmp_28nm_save_configuration(struct ufs_qcom_phy *phy_common)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(cached_phy_regs); i++)
-		cached_phy_regs[i].cfg_value =
-			readl_relaxed(phy_common->mmio +
-				      cached_phy_regs[i].reg_offset);
-
-	for (i = 0; i < ARRAY_SIZE(cached_phy_attr); i++)
-		cached_phy_attr[i].value =
-			ufs_qcom_phy_qmp_28nm_read_attr(phy_common,
-					cached_phy_attr[i].att);
-}
-
-static void
-ufs_qcom_phy_qmp_28nm_restore_configuration(struct ufs_qcom_phy *phy_common)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(cached_phy_attr); i++)
-		ufs_qcom_phy_qmp_28nm_write_attr(phy_common,
-			cached_phy_attr[i].att, cached_phy_attr[i].value);
-}
-
-static
-void ufs_qcom_phy_qmp_28nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
-{
-	writel_relaxed(val & UFS_PHY_TX_LANE_ENABLE_MASK,
-			phy->mmio + UFS_PHY_TX_LANE_ENABLE);
-	mb();
-}
-
-static inline void ufs_qcom_phy_qmp_28nm_start_serdes(struct ufs_qcom_phy *phy)
-{
-	u32 tmp;
-
-	tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
-	tmp &= ~MASK_SERDES_START;
-	tmp |= (1 << OFFSET_SERDES_START);
-	writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
-	mb();
-}
-
-static int ufs_qcom_phy_qmp_28nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
-{
-	int err = 0;
-	u32 val;
-
-	err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
-			val, (val & MASK_PCS_READY), 10, 1000000);
-	if (err)
-		dev_err(phy_common->dev, "%s: phy init failed, %d\n",
-			__func__, err);
-
-	return err;
-}
-
-struct phy_ops ufs_qcom_phy_qmp_28nm_phy_ops = {
-	.init		= ufs_qcom_phy_qmp_28nm_init,
-	.exit		= ufs_qcom_phy_exit,
-	.power_on	= ufs_qcom_phy_power_on,
-	.power_off	= ufs_qcom_phy_power_off,
-	.owner		= THIS_MODULE,
-};
-
-struct ufs_qcom_phy_specific_ops phy_28nm_ops = {
-	.calibrate_phy		= ufs_qcom_phy_qmp_28nm_calibrate,
-	.start_serdes		= ufs_qcom_phy_qmp_28nm_start_serdes,
-	.save_configuration	= ufs_qcom_phy_qmp_28nm_save_configuration,
-	.restore_configuration	= ufs_qcom_phy_qmp_28nm_restore_configuration,
-	.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_28nm_is_pcs_ready,
-	.set_tx_lane_enable	= ufs_qcom_phy_qmp_28nm_set_tx_lane_enable,
-	.power_control		= ufs_qcom_phy_qmp_28nm_power_control,
-};
-
-static int ufs_qcom_phy_qmp_28nm_probe(struct platform_device *pdev)
-{
-	struct ufs_qcom_phy_qmp_28nm *phy;
-	struct device *dev = &pdev->dev;
-	int err = 0;
-	struct phy *generic_phy;
-
-	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
-	if (!phy) {
-		err = -ENOMEM;
-		dev_err(dev, "%s: failed to allocate phy\n", __func__);
-		goto out;
-	}
-
-	phy->common_cfg.cached_regs =
-			(struct ufs_qcom_phy_calibration *)cached_phy_regs;
-	phy->common_cfg.cached_regs_table_size =
-				ARRAY_SIZE(cached_phy_regs);
-
-	generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
-				&ufs_qcom_phy_qmp_28nm_phy_ops, &phy_28nm_ops);
-
-	if (!generic_phy) {
-		dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
-			__func__);
-		err = -EIO;
-		goto out;
-	}
-
-	phy_set_drvdata(generic_phy, phy);
-
-	strlcpy(phy->common_cfg.name, UFS_PHY_NAME,
-			sizeof(phy->common_cfg.name));
-
-out:
-	return err;
-}
-
-static int ufs_qcom_phy_qmp_28nm_remove(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct phy *generic_phy = to_phy(dev);
-	struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
-	int err = 0;
-
-	err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy);
-	if (err)
-		dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n",
-			__func__, err);
-
-	return err;
-}
-
-static const struct of_device_id ufs_qcom_phy_qmp_28nm_of_match[] = {
-	{.compatible = "qcom,ufs-phy-qmp-28nm"},
-	{},
-};
-MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_28nm_of_match);
-
-static struct platform_driver ufs_qcom_phy_qmp_28nm_driver = {
-	.probe = ufs_qcom_phy_qmp_28nm_probe,
-	.remove = ufs_qcom_phy_qmp_28nm_remove,
-	.driver = {
-		.of_match_table = ufs_qcom_phy_qmp_28nm_of_match,
-		.name = "ufs_qcom_phy_qmp_28nm",
-		.owner = THIS_MODULE,
-	},
-};
-
-module_platform_driver(ufs_qcom_phy_qmp_28nm_driver);
-
-MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 28nm");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/phy-qcom-ufs-qmp-28nm.h b/drivers/phy/phy-qcom-ufs-qmp-28nm.h
deleted file mode 100644
index b406d99fab3d..000000000000
--- a/drivers/phy/phy-qcom-ufs-qmp-28nm.h
+++ /dev/null
@@ -1,738 +0,0 @@
-/*
- * Copyright (c) 2013-2014, Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef UFS_QCOM_PHY_QMP_28NM_H_
-#define UFS_QCOM_PHY_QMP_28NM_H_
-
-#include <linux/phy/phy-qcom-ufs.h>
-
-/* QCOM UFS PHY control registers */
-
-#define COM_OFF(x)     (0x000 + x)
-#define PHY_OFF(x)     (0x700 + x)
-#define TX_OFF(n, x)   (0x100 + (0x400 * n) + x)
-#define RX_OFF(n, x)   (0x200 + (0x400 * n) + x)
-
-/* UFS PHY PLL block registers */
-#define QSERDES_COM_SYS_CLK_CTRL                            COM_OFF(0x00)
-#define QSERDES_COM_PLL_VCOTAIL_EN                          COM_OFF(0x04)
-#define QSERDES_COM_CMN_MODE                                COM_OFF(0x08)
-#define QSERDES_COM_IE_TRIM                                 COM_OFF(0x0C)
-#define QSERDES_COM_IP_TRIM                                 COM_OFF(0x10)
-#define QSERDES_COM_PLL_CNTRL                               COM_OFF(0x14)
-#define QSERDES_COM_PLL_IP_SETI                             COM_OFF(0x18)
-#define QSERDES_COM_CORE_CLK_IN_SYNC_SEL                    COM_OFF(0x1C)
-#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN                     COM_OFF(0x20)
-#define QSERDES_COM_PLL_CP_SETI                             COM_OFF(0x24)
-#define QSERDES_COM_PLL_IP_SETP                             COM_OFF(0x28)
-#define QSERDES_COM_PLL_CP_SETP                             COM_OFF(0x2C)
-#define QSERDES_COM_ATB_SEL1                                COM_OFF(0x30)
-#define QSERDES_COM_ATB_SEL2                                COM_OFF(0x34)
-#define QSERDES_COM_SYSCLK_EN_SEL                           COM_OFF(0x38)
-#define QSERDES_COM_RES_CODE_TXBAND                         COM_OFF(0x3C)
-#define QSERDES_COM_RESETSM_CNTRL                           COM_OFF(0x40)
-#define QSERDES_COM_PLLLOCK_CMP1                            COM_OFF(0x44)
-#define QSERDES_COM_PLLLOCK_CMP2                            COM_OFF(0x48)
-#define QSERDES_COM_PLLLOCK_CMP3                            COM_OFF(0x4C)
-#define QSERDES_COM_PLLLOCK_CMP_EN                          COM_OFF(0x50)
-#define QSERDES_COM_RES_TRIM_OFFSET                         COM_OFF(0x54)
-#define QSERDES_COM_BGTC                                    COM_OFF(0x58)
-#define QSERDES_COM_PLL_TEST_UPDN_RESTRIMSTEP               COM_OFF(0x5C)
-#define QSERDES_COM_PLL_VCO_TUNE                            COM_OFF(0x60)
-#define QSERDES_COM_DEC_START1                              COM_OFF(0x64)
-#define QSERDES_COM_PLL_AMP_OS                              COM_OFF(0x68)
-#define QSERDES_COM_SSC_EN_CENTER                           COM_OFF(0x6C)
-#define QSERDES_COM_SSC_ADJ_PER1                            COM_OFF(0x70)
-#define QSERDES_COM_SSC_ADJ_PER2                            COM_OFF(0x74)
-#define QSERDES_COM_SSC_PER1                                COM_OFF(0x78)
-#define QSERDES_COM_SSC_PER2                                COM_OFF(0x7C)
-#define QSERDES_COM_SSC_STEP_SIZE1                          COM_OFF(0x80)
-#define QSERDES_COM_SSC_STEP_SIZE2                          COM_OFF(0x84)
-#define QSERDES_COM_RES_TRIM_SEARCH                         COM_OFF(0x88)
-#define QSERDES_COM_RES_TRIM_FREEZE                         COM_OFF(0x8C)
-#define QSERDES_COM_RES_TRIM_EN_VCOCALDONE                  COM_OFF(0x90)
-#define QSERDES_COM_FAUX_EN                                 COM_OFF(0x94)
-#define QSERDES_COM_DIV_FRAC_START1                         COM_OFF(0x98)
-#define QSERDES_COM_DIV_FRAC_START2                         COM_OFF(0x9C)
-#define QSERDES_COM_DIV_FRAC_START3                         COM_OFF(0xA0)
-#define QSERDES_COM_DEC_START2                              COM_OFF(0xA4)
-#define QSERDES_COM_PLL_RXTXEPCLK_EN                        COM_OFF(0xA8)
-#define QSERDES_COM_PLL_CRCTRL                              COM_OFF(0xAC)
-#define QSERDES_COM_PLL_CLKEPDIV                            COM_OFF(0xB0)
-#define QSERDES_COM_PLL_FREQUPDATE                          COM_OFF(0xB4)
-#define QSERDES_COM_PLL_VCO_HIGH                            COM_OFF(0xB8)
-#define QSERDES_COM_RESET_SM                                COM_OFF(0xBC)
-
-/* UFS PHY registers */
-#define UFS_PHY_PHY_START                                   PHY_OFF(0x00)
-#define UFS_PHY_POWER_DOWN_CONTROL                          PHY_OFF(0x04)
-#define UFS_PHY_PWM_G1_CLK_DIVIDER                          PHY_OFF(0x08)
-#define UFS_PHY_PWM_G2_CLK_DIVIDER                          PHY_OFF(0x0C)
-#define UFS_PHY_PWM_G3_CLK_DIVIDER                          PHY_OFF(0x10)
-#define UFS_PHY_PWM_G4_CLK_DIVIDER                          PHY_OFF(0x14)
-#define UFS_PHY_TIMER_100US_SYSCLK_STEPS_MSB                PHY_OFF(0x18)
-#define UFS_PHY_TIMER_100US_SYSCLK_STEPS_LSB                PHY_OFF(0x1C)
-#define UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB                PHY_OFF(0x20)
-#define UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB                PHY_OFF(0x24)
-#define UFS_PHY_LINE_RESET_TIME                             PHY_OFF(0x28)
-#define UFS_PHY_LINE_RESET_GRANULARITY                      PHY_OFF(0x2C)
-#define UFS_PHY_CONTROLSYM_ONE_HOT_DISABLE                  PHY_OFF(0x30)
-#define UFS_PHY_CORECLK_PWM_G1_CLK_DIVIDER                  PHY_OFF(0x34)
-#define UFS_PHY_CORECLK_PWM_G2_CLK_DIVIDER                  PHY_OFF(0x38)
-#define UFS_PHY_CORECLK_PWM_G3_CLK_DIVIDER                  PHY_OFF(0x3C)
-#define UFS_PHY_CORECLK_PWM_G4_CLK_DIVIDER                  PHY_OFF(0x40)
-#define UFS_PHY_TX_LANE_ENABLE                              PHY_OFF(0x44)
-#define UFS_PHY_TSYNC_RSYNC_CNTL                            PHY_OFF(0x48)
-#define UFS_PHY_RETIME_BUFFER_EN                            PHY_OFF(0x4C)
-#define UFS_PHY_PLL_CNTL                                    PHY_OFF(0x50)
-#define UFS_PHY_TX_LARGE_AMP_DRV_LVL                        PHY_OFF(0x54)
-#define UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL                   PHY_OFF(0x58)
-#define UFS_PHY_TX_SMALL_AMP_DRV_LVL                        PHY_OFF(0x5C)
-#define UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL                   PHY_OFF(0x60)
-#define UFS_PHY_CFG_CHANGE_CNT_VAL                          PHY_OFF(0x64)
-#define UFS_PHY_OMC_STATUS_RDVAL                            PHY_OFF(0x68)
-#define UFS_PHY_RX_SYNC_WAIT_TIME                           PHY_OFF(0x6C)
-#define UFS_PHY_L0_BIST_CTRL                                PHY_OFF(0x70)
-#define UFS_PHY_L1_BIST_CTRL                                PHY_OFF(0x74)
-#define UFS_PHY_BIST_PRBS_POLY0                             PHY_OFF(0x78)
-#define UFS_PHY_BIST_PRBS_POLY1                             PHY_OFF(0x7C)
-#define UFS_PHY_BIST_PRBS_SEED0                             PHY_OFF(0x80)
-#define UFS_PHY_BIST_PRBS_SEED1                             PHY_OFF(0x84)
-#define UFS_PHY_BIST_FIXED_PAT_CTRL                         PHY_OFF(0x88)
-#define UFS_PHY_BIST_FIXED_PAT0_DATA                        PHY_OFF(0x8C)
-#define UFS_PHY_BIST_FIXED_PAT1_DATA                        PHY_OFF(0x90)
-#define UFS_PHY_BIST_FIXED_PAT2_DATA                        PHY_OFF(0x94)
-#define UFS_PHY_BIST_FIXED_PAT3_DATA                        PHY_OFF(0x98)
-#define UFS_PHY_TX_HSGEAR_CAPABILITY                        PHY_OFF(0x9C)
-#define UFS_PHY_TX_PWMGEAR_CAPABILITY                       PHY_OFF(0xA0)
-#define UFS_PHY_TX_AMPLITUDE_CAPABILITY                     PHY_OFF(0xA4)
-#define UFS_PHY_TX_EXTERNALSYNC_CAPABILITY                  PHY_OFF(0xA8)
-#define UFS_PHY_TX_HS_UNTERMINATED_LINE_DRIVE_CAPABILITY    PHY_OFF(0xAC)
-#define UFS_PHY_TX_LS_TERMINATED_LINE_DRIVE_CAPABILITY      PHY_OFF(0xB0)
-#define UFS_PHY_TX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY       PHY_OFF(0xB4)
-#define UFS_PHY_TX_MIN_STALL_NOCONFIG_TIME_CAPABILITY       PHY_OFF(0xB8)
-#define UFS_PHY_TX_MIN_SAVE_CONFIG_TIME_CAPABILITY          PHY_OFF(0xBC)
-#define UFS_PHY_TX_REF_CLOCK_SHARED_CAPABILITY              PHY_OFF(0xC0)
-#define UFS_PHY_TX_PHY_MAJORMINOR_RELEASE_CAPABILITY        PHY_OFF(0xC4)
-#define UFS_PHY_TX_PHY_EDITORIAL_RELEASE_CAPABILITY         PHY_OFF(0xC8)
-#define UFS_PHY_TX_HIBERN8TIME_CAPABILITY                   PHY_OFF(0xCC)
-#define UFS_PHY_RX_HSGEAR_CAPABILITY                        PHY_OFF(0xD0)
-#define UFS_PHY_RX_PWMGEAR_CAPABILITY                       PHY_OFF(0xD4)
-#define UFS_PHY_RX_HS_UNTERMINATED_CAPABILITY               PHY_OFF(0xD8)
-#define UFS_PHY_RX_LS_TERMINATED_CAPABILITY                 PHY_OFF(0xDC)
-#define UFS_PHY_RX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY       PHY_OFF(0xE0)
-#define UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAPABILITY       PHY_OFF(0xE4)
-#define UFS_PHY_RX_MIN_SAVE_CONFIG_TIME_CAPABILITY          PHY_OFF(0xE8)
-#define UFS_PHY_RX_REF_CLOCK_SHARED_CAPABILITY              PHY_OFF(0xEC)
-#define UFS_PHY_RX_HS_G1_SYNC_LENGTH_CAPABILITY             PHY_OFF(0xF0)
-#define UFS_PHY_RX_HS_G1_PREPARE_LENGTH_CAPABILITY          PHY_OFF(0xF4)
-#define UFS_PHY_RX_LS_PREPARE_LENGTH_CAPABILITY             PHY_OFF(0xF8)
-#define UFS_PHY_RX_PWM_BURST_CLOSURE_LENGTH_CAPABILITY      PHY_OFF(0xFC)
-#define UFS_PHY_RX_MIN_ACTIVATETIME_CAPABILITY              PHY_OFF(0x100)
-#define UFS_PHY_RX_PHY_MAJORMINOR_RELEASE_CAPABILITY        PHY_OFF(0x104)
-#define UFS_PHY_RX_PHY_EDITORIAL_RELEASE_CAPABILITY         PHY_OFF(0x108)
-#define UFS_PHY_RX_HIBERN8TIME_CAPABILITY                   PHY_OFF(0x10C)
-#define UFS_PHY_RX_HS_G2_SYNC_LENGTH_CAPABILITY             PHY_OFF(0x110)
-#define UFS_PHY_RX_HS_G3_SYNC_LENGTH_CAPABILITY             PHY_OFF(0x114)
-#define UFS_PHY_RX_HS_G2_PREPARE_LENGTH_CAPABILITY          PHY_OFF(0x118)
-#define UFS_PHY_RX_HS_G3_PREPARE_LENGTH_CAPABILITY          PHY_OFF(0x11C)
-#define UFS_PHY_DEBUG_BUS_SEL                               PHY_OFF(0x120)
-#define UFS_PHY_DEBUG_BUS_0_STATUS_CHK                      PHY_OFF(0x124)
-#define UFS_PHY_DEBUG_BUS_1_STATUS_CHK                      PHY_OFF(0x128)
-#define UFS_PHY_DEBUG_BUS_2_STATUS_CHK                      PHY_OFF(0x12C)
-#define UFS_PHY_DEBUG_BUS_3_STATUS_CHK                      PHY_OFF(0x130)
-#define UFS_PHY_PCS_READY_STATUS                            PHY_OFF(0x134)
-#define UFS_PHY_L0_BIST_CHK_ERR_CNT_L_STATUS                PHY_OFF(0x138)
-#define UFS_PHY_L0_BIST_CHK_ERR_CNT_H_STATUS                PHY_OFF(0x13C)
-#define UFS_PHY_L1_BIST_CHK_ERR_CNT_L_STATUS                PHY_OFF(0x140)
-#define UFS_PHY_L1_BIST_CHK_ERR_CNT_H_STATUS                PHY_OFF(0x144)
-#define UFS_PHY_L0_BIST_CHK_STATUS                          PHY_OFF(0x148)
-#define UFS_PHY_L1_BIST_CHK_STATUS                          PHY_OFF(0x14C)
-#define UFS_PHY_DEBUG_BUS_0_STATUS                          PHY_OFF(0x150)
-#define UFS_PHY_DEBUG_BUS_1_STATUS                          PHY_OFF(0x154)
-#define UFS_PHY_DEBUG_BUS_2_STATUS                          PHY_OFF(0x158)
-#define UFS_PHY_DEBUG_BUS_3_STATUS                          PHY_OFF(0x15C)
-#define UFS_PHY_RMMI_ATTR_CTRL                              PHY_OFF(0x16C)
-#define UFS_PHY_RMMI_RX_CFGUPDT_L1	(1 << 7)
-#define UFS_PHY_RMMI_TX_CFGUPDT_L1	(1 << 6)
-#define UFS_PHY_RMMI_CFGWR_L1		(1 << 5)
-#define UFS_PHY_RMMI_CFGRD_L1		(1 << 4)
-#define UFS_PHY_RMMI_RX_CFGUPDT_L0	(1 << 3)
-#define UFS_PHY_RMMI_TX_CFGUPDT_L0	(1 << 2)
-#define UFS_PHY_RMMI_CFGWR_L0		(1 << 1)
-#define UFS_PHY_RMMI_CFGRD_L0		(1 << 0)
-#define UFS_PHY_RMMI_ATTRID				    PHY_OFF(0x170)
-#define UFS_PHY_RMMI_ATTRWRVAL				    PHY_OFF(0x174)
-#define UFS_PHY_RMMI_ATTRRDVAL_L0_STATUS		    PHY_OFF(0x178)
-#define UFS_PHY_RMMI_ATTRRDVAL_L1_STATUS		    PHY_OFF(0x17C)
-
-/* TX LANE n (0, 1) registers */
-#define QSERDES_TX_BIST_MODE_LANENO(n)                      TX_OFF(n, 0x00)
-#define QSERDES_TX_CLKBUF_ENABLE(n)                         TX_OFF(n, 0x04)
-#define QSERDES_TX_TX_EMP_POST1_LVL(n)                      TX_OFF(n, 0x08)
-#define QSERDES_TX_TX_DRV_LVL(n)                            TX_OFF(n, 0x0C)
-#define QSERDES_TX_RESET_TSYNC_EN(n)                        TX_OFF(n, 0x10)
-#define QSERDES_TX_LPB_EN(n)                                TX_OFF(n, 0x14)
-#define QSERDES_TX_RES_CODE(n)                              TX_OFF(n, 0x18)
-#define QSERDES_TX_PERL_LENGTH1(n)                          TX_OFF(n, 0x1C)
-#define QSERDES_TX_PERL_LENGTH2(n)                          TX_OFF(n, 0x20)
-#define QSERDES_TX_SERDES_BYP_EN_OUT(n)                     TX_OFF(n, 0x24)
-#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_EN(n)           TX_OFF(n, 0x28)
-#define QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN(n)            TX_OFF(n, 0x2C)
-#define QSERDES_TX_BIST_PATTERN1(n)                         TX_OFF(n, 0x30)
-#define QSERDES_TX_BIST_PATTERN2(n)                         TX_OFF(n, 0x34)
-#define QSERDES_TX_BIST_PATTERN3(n)                         TX_OFF(n, 0x38)
-#define QSERDES_TX_BIST_PATTERN4(n)                         TX_OFF(n, 0x3C)
-#define QSERDES_TX_BIST_PATTERN5(n)                         TX_OFF(n, 0x40)
-#define QSERDES_TX_BIST_PATTERN6(n)                         TX_OFF(n, 0x44)
-#define QSERDES_TX_BIST_PATTERN7(n)                         TX_OFF(n, 0x48)
-#define QSERDES_TX_BIST_PATTERN8(n)                         TX_OFF(n, 0x4C)
-#define QSERDES_TX_LANE_MODE(n)                             TX_OFF(n, 0x50)
-#define QSERDES_TX_ATB_SEL(n)                               TX_OFF(n, 0x54)
-#define QSERDES_TX_REC_DETECT_LVL(n)                        TX_OFF(n, 0x58)
-#define QSERDES_TX_PRBS_SEED1(n)                            TX_OFF(n, 0x5C)
-#define QSERDES_TX_PRBS_SEED2(n)                            TX_OFF(n, 0x60)
-#define QSERDES_TX_PRBS_SEED3(n)                            TX_OFF(n, 0x64)
-#define QSERDES_TX_PRBS_SEED4(n)                            TX_OFF(n, 0x68)
-#define QSERDES_TX_RESET_GEN(n)                             TX_OFF(n, 0x6C)
-#define QSERDES_TX_TRAN_DRVR_EMP_EN(n)                      TX_OFF(n, 0x70)
-#define QSERDES_TX_TX_INTERFACE_MODE(n)                     TX_OFF(n, 0x74)
-#define QSERDES_TX_BIST_STATUS(n)                           TX_OFF(n, 0x78)
-#define QSERDES_TX_BIST_ERROR_COUNT1(n)                     TX_OFF(n, 0x7C)
-#define QSERDES_TX_BIST_ERROR_COUNT2(n)                     TX_OFF(n, 0x80)
-
-/* RX LANE n (0, 1) registers */
-#define QSERDES_RX_CDR_CONTROL(n)                           RX_OFF(n, 0x00)
-#define QSERDES_RX_AUX_CONTROL(n)                           RX_OFF(n, 0x04)
-#define QSERDES_RX_AUX_DATA_TCODE(n)                        RX_OFF(n, 0x08)
-#define QSERDES_RX_RCLK_AUXDATA_SEL(n)                      RX_OFF(n, 0x0C)
-#define QSERDES_RX_EQ_CONTROL(n)                            RX_OFF(n, 0x10)
-#define QSERDES_RX_RX_EQ_GAIN2(n)                           RX_OFF(n, 0x14)
-#define QSERDES_RX_AC_JTAG_INIT(n)                          RX_OFF(n, 0x18)
-#define QSERDES_RX_AC_JTAG_LVL_EN(n)                        RX_OFF(n, 0x1C)
-#define QSERDES_RX_AC_JTAG_MODE(n)                          RX_OFF(n, 0x20)
-#define QSERDES_RX_AC_JTAG_RESET(n)                         RX_OFF(n, 0x24)
-#define QSERDES_RX_RX_IQ_RXDET_EN(n)                        RX_OFF(n, 0x28)
-#define QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE(n)            RX_OFF(n, 0x2C)
-#define QSERDES_RX_RX_EQ_GAIN1(n)                           RX_OFF(n, 0x30)
-#define QSERDES_RX_SIGDET_CNTRL(n)                          RX_OFF(n, 0x34)
-#define QSERDES_RX_RX_BAND(n)                               RX_OFF(n, 0x38)
-#define QSERDES_RX_CDR_FREEZE_UP_DN(n)                      RX_OFF(n, 0x3C)
-#define QSERDES_RX_RX_INTERFACE_MODE(n)                     RX_OFF(n, 0x40)
-#define QSERDES_RX_JITTER_GEN_MODE(n)                       RX_OFF(n, 0x44)
-#define QSERDES_RX_BUJ_AMP(n)                               RX_OFF(n, 0x48)
-#define QSERDES_RX_SJ_AMP1(n)                               RX_OFF(n, 0x4C)
-#define QSERDES_RX_SJ_AMP2(n)                               RX_OFF(n, 0x50)
-#define QSERDES_RX_SJ_PER1(n)                               RX_OFF(n, 0x54)
-#define QSERDES_RX_SJ_PER2(n)                               RX_OFF(n, 0x58)
-#define QSERDES_RX_BUJ_STEP_FREQ1(n)                        RX_OFF(n, 0x5C)
-#define QSERDES_RX_BUJ_STEP_FREQ2(n)                        RX_OFF(n, 0x60)
-#define QSERDES_RX_PPM_OFFSET1(n)                           RX_OFF(n, 0x64)
-#define QSERDES_RX_PPM_OFFSET2(n)                           RX_OFF(n, 0x68)
-#define QSERDES_RX_SIGN_PPM_PERIOD1(n)                      RX_OFF(n, 0x6C)
-#define QSERDES_RX_SIGN_PPM_PERIOD2(n)                      RX_OFF(n, 0x70)
-#define QSERDES_RX_SSC_CTRL(n)                              RX_OFF(n, 0x74)
-#define QSERDES_RX_SSC_COUNT1(n)                            RX_OFF(n, 0x78)
-#define QSERDES_RX_SSC_COUNT2(n)                            RX_OFF(n, 0x7C)
-#define QSERDES_RX_PWM_CNTRL1(n)                            RX_OFF(n, 0x80)
-#define QSERDES_RX_PWM_CNTRL2(n)                            RX_OFF(n, 0x84)
-#define QSERDES_RX_PWM_NDIV(n)                              RX_OFF(n, 0x88)
-#define QSERDES_RX_SIGDET_CNTRL2(n)                         RX_OFF(n, 0x8C)
-#define QSERDES_RX_UFS_CNTRL(n)                             RX_OFF(n, 0x90)
-#define QSERDES_RX_CDR_CONTROL3(n)                          RX_OFF(n, 0x94)
-#define QSERDES_RX_CDR_CONTROL_HALF(n)                      RX_OFF(n, 0x98)
-#define QSERDES_RX_CDR_CONTROL_QUARTER(n)                   RX_OFF(n, 0x9C)
-#define QSERDES_RX_CDR_CONTROL_EIGHTH(n)                    RX_OFF(n, 0xA0)
-#define QSERDES_RX_UCDR_FO_GAIN(n)                          RX_OFF(n, 0xA4)
-#define QSERDES_RX_UCDR_SO_GAIN(n)                          RX_OFF(n, 0xA8)
-#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE(n)         RX_OFF(n, 0xAC)
-#define QSERDES_RX_UCDR_FO_TO_SO_DELAY(n)                   RX_OFF(n, 0xB0)
-#define QSERDES_RX_PI_CTRL1(n)                              RX_OFF(n, 0xB4)
-#define QSERDES_RX_PI_CTRL2(n)                              RX_OFF(n, 0xB8)
-#define QSERDES_RX_PI_QUAD(n)                               RX_OFF(n, 0xBC)
-#define QSERDES_RX_IDATA1(n)                                RX_OFF(n, 0xC0)
-#define QSERDES_RX_IDATA2(n)                                RX_OFF(n, 0xC4)
-#define QSERDES_RX_AUX_DATA1(n)                             RX_OFF(n, 0xC8)
-#define QSERDES_RX_AUX_DATA2(n)                             RX_OFF(n, 0xCC)
-#define QSERDES_RX_AC_JTAG_OUTP(n)                          RX_OFF(n, 0xD0)
-#define QSERDES_RX_AC_JTAG_OUTN(n)                          RX_OFF(n, 0xD4)
-#define QSERDES_RX_RX_SIGDET_PWMDECSTATUS(n)                RX_OFF(n, 0xD8)
-
-#define UFS_PHY_TX_LANE_ENABLE_MASK		0x3
-
-/*
- * This structure represents the 28nm specific phy.
- * common_cfg MUST remain the first field in this structure
- * in case extra fields are added. This way, when calling
- * get_ufs_qcom_phy() of generic phy, we can extract the
- * common phy structure (struct ufs_qcom_phy) out of it
- * regardless of the relevant specific phy.
- */
-struct ufs_qcom_phy_qmp_28nm {
-	struct ufs_qcom_phy common_cfg;
-};
-
-static struct ufs_qcom_phy_calibration phy_cal_table_ctrl_1_1_0_rate_A[] = {
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xFF),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CNTRL, 0x24),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x08),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x10),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x67),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x10),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x13),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(0), 0x43),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(1), 0x43),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(0), 0x22),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x12),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x2a),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(1), 0x22),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x12),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x2a),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(0), 0xC0),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(1), 0xC0),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(0), 0x07),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(1), 0x07),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PWM_G1_CLK_DIVIDER, 0x50),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PWM_G2_CLK_DIVIDER, 0x28),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PWM_G3_CLK_DIVIDER, 0x10),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PWM_G4_CLK_DIVIDER, 0x08),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G1_CLK_DIVIDER, 0xa8),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G2_CLK_DIVIDER, 0x54),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G3_CLK_DIVIDER, 0x2a),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G4_CLK_DIVIDER, 0x15),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_OMC_STATUS_RDVAL, 0xff),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_LINE_RESET_TIME, 0x1f),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_LINE_RESET_GRANULARITY, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TSYNC_RSYNC_CNTL, 0x03),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PLL_CNTL, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x1a),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CFG_CHANGE_CNT_VAL, 0x09),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYNC_WAIT_TIME, 0x30),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_TX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_RX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY, 0x08),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_TX_MIN_STALL_NOCONFIG_TIME_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAPABILITY, 0x0f),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_TX_MIN_SAVE_CONFIG_TIME_CAPABILITY, 0x04),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_RX_MIN_SAVE_CONFIG_TIME_CAPABILITY, 0xc8),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_RX_PWM_BURST_CLOSURE_LENGTH_CAPABILITY, 0x10),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_ACTIVATETIME_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1(0), 0x07),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2(0), 0x07),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1(1), 0x07),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2(1), 0x07),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL3(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL3(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3f),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_TRIM_OFFSET, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BGTC, 0x0f),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_AMP_OS, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TX_DRV_LVL(0), 0x0f),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TX_DRV_LVL(1), 0x0f),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_BIST_MODE_LANENO(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_BIST_MODE_LANENO(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TX_EMP_POST1_LVL(0), 0x04),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TX_EMP_POST1_LVL(1), 0x04),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_EN(0), 0x05),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_EN(1), 0x05),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_100US_SYSCLK_STEPS_MSB, 0x07),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_100US_SYSCLK_STEPS_LSB, 0x80),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x27),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CONTROLSYM_ONE_HOT_DISABLE, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RETIME_BUFFER_EN, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x03),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_PWMGEAR_CAPABILITY, 0x04),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_AMPLITUDE_CAPABILITY, 0x03),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_EXTERNALSYNC_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_TX_HS_UNTERMINATED_LINE_DRIVE_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_TX_LS_TERMINATED_LINE_DRIVE_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_REF_CLOCK_SHARED_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HIBERN8TIME_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x03),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_PWMGEAR_CAPABILITY, 0x04),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_UNTERMINATED_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_LS_TERMINATED_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_REF_CLOCK_SHARED_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G1_SYNC_LENGTH_CAPABILITY, 0x48),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_RX_HS_G1_PREPARE_LENGTH_CAPABILITY, 0x0f),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_LS_PREPARE_LENGTH_CAPABILITY, 0x09),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HIBERN8TIME_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G2_SYNC_LENGTH_CAPABILITY, 0x48),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G3_SYNC_LENGTH_CAPABILITY, 0x48),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_RX_HS_G2_PREPARE_LENGTH_CAPABILITY, 0x0f),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_RX_HS_G3_PREPARE_LENGTH_CAPABILITY, 0x0f),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_CLKBUF_ENABLE(0), 0x09),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_RESET_TSYNC_EN(0), 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_RES_CODE(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_SERDES_BYP_EN_OUT(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_REC_DETECT_LVL(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TRAN_DRVR_EMP_EN(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_AUX_CONTROL(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_AUX_DATA_TCODE(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RCLK_AUXDATA_SEL(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_EQ_CONTROL(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(0), 0x73),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE(0), 0x05),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_FREEZE_UP_DN(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_EIGHTH(0), 0x22),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_GAIN(0), 0x0a),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_GAIN(0), 0x06),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE(0), 0x35),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_TO_SO_DELAY(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_CLKBUF_ENABLE(1), 0x09),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_RESET_TSYNC_EN(1), 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_RES_CODE(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_SERDES_BYP_EN_OUT(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_REC_DETECT_LVL(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TRAN_DRVR_EMP_EN(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_AUX_CONTROL(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_AUX_DATA_TCODE(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RCLK_AUXDATA_SEL(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_EQ_CONTROL(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(1), 0x73),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE(1), 0x05),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_FREEZE_UP_DN(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_EIGHTH(1), 0x22),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_GAIN(1), 0x0a),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_GAIN(1), 0x06),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE(1), 0x35),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_TO_SO_DELAY(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_MODE, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_IE_TRIM, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_IP_TRIM, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_IN_SYNC_SEL, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_TEST_UPDN_RESTRIMSTEP, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_FAUX_EN, 0x00),
-};
-
-static struct ufs_qcom_phy_calibration phy_cal_table_ctrl_1_1_1_rate_A[] = {
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0x43),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CNTRL, 0x24),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x08),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x10),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x10),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(0), 0x43),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(1), 0x43),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(0), 0x40),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(1), 0x40),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(0), 0xC0),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(1), 0xC0),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(0), 0x07),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(1), 0x07),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PWM_G1_CLK_DIVIDER, 0x30),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PWM_G2_CLK_DIVIDER, 0x18),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PWM_G3_CLK_DIVIDER, 0x0c),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PWM_G4_CLK_DIVIDER, 0x06),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G1_CLK_DIVIDER, 0xa8),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G2_CLK_DIVIDER, 0x54),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G3_CLK_DIVIDER, 0x2a),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G4_CLK_DIVIDER, 0x15),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_OMC_STATUS_RDVAL, 0xff),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_LINE_RESET_TIME, 0x1f),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_LINE_RESET_GRANULARITY, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TSYNC_RSYNC_CNTL, 0x03),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PLL_CNTL, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x1a),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CFG_CHANGE_CNT_VAL, 0x09),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYNC_WAIT_TIME, 0x30),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_TX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_RX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY, 0x08),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_TX_MIN_STALL_NOCONFIG_TIME_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAPABILITY, 0x0f),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_TX_MIN_SAVE_CONFIG_TIME_CAPABILITY, 0x04),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_RX_MIN_SAVE_CONFIG_TIME_CAPABILITY, 0xc8),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_RX_PWM_BURST_CLOSURE_LENGTH_CAPABILITY, 0x10),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_ACTIVATETIME_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1(0), 0x1f),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2(0), 0x17),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1(1), 0x1f),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2(1), 0x17),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL3(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL3(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x07),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x0f),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x07),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_TRIM_OFFSET, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BGTC, 0x0f),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_AMP_OS, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TX_DRV_LVL(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TX_DRV_LVL(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_BIST_MODE_LANENO(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_BIST_MODE_LANENO(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TX_EMP_POST1_LVL(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TX_EMP_POST1_LVL(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_EN(0), 0x05),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_EN(1), 0x05),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_100US_SYSCLK_STEPS_MSB, 0x07),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_100US_SYSCLK_STEPS_LSB, 0x80),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x27),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CONTROLSYM_ONE_HOT_DISABLE, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RETIME_BUFFER_EN, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x03),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_PWMGEAR_CAPABILITY, 0x04),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_AMPLITUDE_CAPABILITY, 0x03),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_EXTERNALSYNC_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_TX_HS_UNTERMINATED_LINE_DRIVE_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		UFS_PHY_TX_LS_TERMINATED_LINE_DRIVE_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_REF_CLOCK_SHARED_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HIBERN8TIME_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x03),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_PWMGEAR_CAPABILITY, 0x04),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_UNTERMINATED_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_LS_TERMINATED_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_REF_CLOCK_SHARED_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G1_SYNC_LENGTH_CAPABILITY, 0x48),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G1_PREPARE_LENGTH_CAPABILITY,
-									0x0f),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_LS_PREPARE_LENGTH_CAPABILITY, 0x0a),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HIBERN8TIME_CAPABILITY, 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G2_SYNC_LENGTH_CAPABILITY, 0x48),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G3_SYNC_LENGTH_CAPABILITY, 0x48),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G2_PREPARE_LENGTH_CAPABILITY,
-									0x0f),
-	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G3_PREPARE_LENGTH_CAPABILITY,
-									0x0f),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_CLKBUF_ENABLE(0), 0x09),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_RESET_TSYNC_EN(0), 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_RES_CODE(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_SERDES_BYP_EN_OUT(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_REC_DETECT_LVL(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TRAN_DRVR_EMP_EN(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_AUX_CONTROL(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_AUX_DATA_TCODE(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RCLK_AUXDATA_SEL(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_EQ_CONTROL(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(0), 0x51),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE(0), 0x05),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_FREEZE_UP_DN(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_EIGHTH(0), 0x22),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_GAIN(0), 0x0a),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_GAIN(0), 0x06),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE(0), 0x35),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_TO_SO_DELAY(0), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_CLKBUF_ENABLE(1), 0x09),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_RESET_TSYNC_EN(1), 0x01),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_RES_CODE(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_SERDES_BYP_EN_OUT(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_REC_DETECT_LVL(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TRAN_DRVR_EMP_EN(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_AUX_CONTROL(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_AUX_DATA_TCODE(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RCLK_AUXDATA_SEL(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_EQ_CONTROL(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(1), 0x51),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE(1), 0x05),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_FREEZE_UP_DN(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_EIGHTH(1), 0x22),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_GAIN(1), 0x0a),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_GAIN(1), 0x06),
-	UFS_QCOM_PHY_CAL_ENTRY(
-		QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE(1), 0x35),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_TO_SO_DELAY(1), 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_MODE, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_IE_TRIM, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_IP_TRIM, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_IN_SYNC_SEL, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_TEST_UPDN_RESTRIMSTEP, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_FAUX_EN, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x08),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x08),
-};
-
-static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x10),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1E),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
-	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
-};
-
-static struct ufs_qcom_phy_calibration cached_phy_regs[] = {
-	{QSERDES_COM_PLL_CRCTRL},
-	{QSERDES_COM_PLL_CNTRL},
-	{QSERDES_COM_SYSCLK_EN_SEL},
-	{QSERDES_COM_SYS_CLK_CTRL},
-	{QSERDES_COM_PLL_CLKEPDIV},
-	{QSERDES_COM_DEC_START1},
-	{QSERDES_COM_DEC_START2},
-	{QSERDES_COM_DIV_FRAC_START1},
-	{QSERDES_COM_DIV_FRAC_START2},
-	{QSERDES_COM_DIV_FRAC_START3},
-	{QSERDES_COM_PLLLOCK_CMP1},
-	{QSERDES_COM_PLLLOCK_CMP2},
-	{QSERDES_COM_PLLLOCK_CMP3},
-	{QSERDES_COM_PLLLOCK_CMP_EN},
-	{QSERDES_COM_RESETSM_CNTRL},
-	{QSERDES_COM_PLL_RXTXEPCLK_EN},
-	{QSERDES_RX_PWM_CNTRL1(0)},
-	{QSERDES_RX_PWM_CNTRL1(1)},
-	{QSERDES_RX_CDR_CONTROL(0)},
-	{QSERDES_RX_CDR_CONTROL_HALF(0)},
-	{QSERDES_RX_CDR_CONTROL_QUARTER(0)},
-	{QSERDES_RX_CDR_CONTROL(1)},
-	{QSERDES_RX_CDR_CONTROL_HALF(1)},
-	{QSERDES_RX_CDR_CONTROL_QUARTER(1)},
-	{QSERDES_RX_SIGDET_CNTRL(0)},
-	{QSERDES_RX_SIGDET_CNTRL(1)},
-	{QSERDES_RX_SIGDET_CNTRL2(0)},
-	{QSERDES_RX_SIGDET_CNTRL2(1)},
-	{QSERDES_RX_RX_EQ_GAIN1(0)},
-	{QSERDES_RX_RX_EQ_GAIN2(0)},
-	{QSERDES_RX_RX_EQ_GAIN1(1)},
-	{QSERDES_RX_RX_EQ_GAIN2(1)},
-	{QSERDES_COM_PLL_IP_SETI},
-	{QSERDES_COM_PLL_CP_SETI},
-	{QSERDES_COM_PLL_IP_SETP},
-	{QSERDES_COM_PLL_CP_SETP},
-	{UFS_PHY_PWM_G1_CLK_DIVIDER},
-	{UFS_PHY_PWM_G2_CLK_DIVIDER},
-	{UFS_PHY_PWM_G3_CLK_DIVIDER},
-	{UFS_PHY_PWM_G4_CLK_DIVIDER},
-	{UFS_PHY_CORECLK_PWM_G1_CLK_DIVIDER},
-	{UFS_PHY_CORECLK_PWM_G2_CLK_DIVIDER},
-	{UFS_PHY_CORECLK_PWM_G3_CLK_DIVIDER},
-	{UFS_PHY_CORECLK_PWM_G4_CLK_DIVIDER},
-	{UFS_PHY_OMC_STATUS_RDVAL},
-	{UFS_PHY_LINE_RESET_TIME},
-	{UFS_PHY_LINE_RESET_GRANULARITY},
-	{UFS_PHY_TSYNC_RSYNC_CNTL},
-	{UFS_PHY_PLL_CNTL},
-	{UFS_PHY_TX_LARGE_AMP_DRV_LVL},
-	{UFS_PHY_TX_SMALL_AMP_DRV_LVL},
-	{UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL},
-	{UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL},
-	{UFS_PHY_CFG_CHANGE_CNT_VAL},
-	{UFS_PHY_RX_SYNC_WAIT_TIME},
-	{UFS_PHY_TX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY},
-	{UFS_PHY_RX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY},
-	{UFS_PHY_TX_MIN_STALL_NOCONFIG_TIME_CAPABILITY},
-	{UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAPABILITY},
-	{UFS_PHY_TX_MIN_SAVE_CONFIG_TIME_CAPABILITY},
-	{UFS_PHY_RX_MIN_SAVE_CONFIG_TIME_CAPABILITY},
-	{UFS_PHY_RX_PWM_BURST_CLOSURE_LENGTH_CAPABILITY},
-	{UFS_PHY_RX_MIN_ACTIVATETIME_CAPABILITY},
-	{QSERDES_RX_CDR_CONTROL3(0)},
-	{QSERDES_RX_CDR_CONTROL3(1)},
-	{QSERDES_COM_RES_TRIM_OFFSET},
-	{QSERDES_COM_BGTC},
-	{QSERDES_COM_PLL_AMP_OS},
-};
-
-static struct ufs_qcom_phy_stored_attributes cached_phy_attr[] = {
-	{TX_MODE},
-	{TX_HSRATE_SERIES},
-	{TX_HSGEAR},
-	{TX_PWMGEAR},
-	{TX_AMPLITUDE},
-	{TX_HS_SLEWRATE},
-	{TX_SYNC_SOURCE},
-	{TX_HS_PREPARE_LENGTH},
-	{TX_LS_PREPARE_LENGTH},
-	{TX_LCC_ENABLE},
-	{TX_PWM_BURST_CLOSURE_EXTENSION},
-	{TX_BYPASS_8B10B_ENABLE},
-	{TX_DRIVER_POLARITY},
-	{TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE},
-	{TX_LS_TERMINATED_LINE_DRIVE_ENABLE},
-	{TX_LCC_SEQUENCER},
-	{TX_MIN_ACTIVATETIME},
-	{TX_PWM_G6_G7_SYNC_LENGTH},
-	{RX_MODE},
-	{RX_HSRATE_SERIES},
-	{RX_HSGEAR},
-	{RX_PWMGEAR},
-	{RX_LS_TERMINATED_ENABLE},
-	{RX_HS_UNTERMINATED_ENABLE},
-	{RX_ENTER_HIBERN8},
-	{RX_BYPASS_8B10B_ENABLE},
-	{RX_TERMINATION_FORCE_ENABLE},
-};
-
-#endif