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| author | Linux Build Service Account <lnxbuild@localhost> | 2016-09-12 14:42:22 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-09-12 14:42:22 -0700 |
| commit | 50af22ee1c437fc9a858fe50d6b408a115d506a1 (patch) | |
| tree | dec07466960afa67336c4faba382a3786442c7dd | |
| parent | 43f14d2d08453b52b8c449ad72c5da4772cebe02 (diff) | |
| parent | 7c179541470a91b1492e19eb351b277bb1376708 (diff) | |
Merge "clk: msm: gcc-cobalt: Add support for gcc_aggre1_ufs_axi_hw_ctl_clk"
| -rw-r--r-- | drivers/clk/msm/clock-gcc-cobalt.c | 12 | ||||
| -rw-r--r-- | include/dt-bindings/clock/msm-clocks-cobalt.h | 1 |
2 files changed, 13 insertions, 0 deletions
diff --git a/drivers/clk/msm/clock-gcc-cobalt.c b/drivers/clk/msm/clock-gcc-cobalt.c index 71c5541d0c0d..272d7185ca47 100644 --- a/drivers/clk/msm/clock-gcc-cobalt.c +++ b/drivers/clk/msm/clock-gcc-cobalt.c @@ -1200,6 +1200,17 @@ static struct branch_clk gcc_aggre1_ufs_axi_clk = { }, }; +static struct hw_ctl_clk gcc_aggre1_ufs_axi_hw_ctl_clk = { + .cbcr_reg = GCC_AGGRE1_UFS_AXI_CBCR, + .base = &virt_base, + .c = { + .dbg_name = "gcc_aggre1_ufs_axi_hw_ctl_clk", + .parent = &gcc_aggre1_ufs_axi_clk.c, + .ops = &clk_ops_branch_hw_ctl, + CLK_INIT(gcc_aggre1_ufs_axi_hw_ctl_clk.c), + }, +}; + static struct branch_clk gcc_aggre1_usb3_axi_clk = { .cbcr_reg = GCC_AGGRE1_USB3_AXI_CBCR, .has_sibling = 1, @@ -2597,6 +2608,7 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = { CLK_LIST(gcc_qusb2phy_sec_reset), CLK_LIST(gpll0_out_msscc), CLK_LIST(gcc_aggre1_ufs_axi_clk), + CLK_LIST(gcc_aggre1_ufs_axi_hw_ctl_clk), CLK_LIST(gcc_aggre1_usb3_axi_clk), CLK_LIST(gcc_bimc_mss_q6_axi_clk), CLK_LIST(gcc_blsp1_ahb_clk), diff --git a/include/dt-bindings/clock/msm-clocks-cobalt.h b/include/dt-bindings/clock/msm-clocks-cobalt.h index 31c4537ea964..b80ea0c31597 100644 --- a/include/dt-bindings/clock/msm-clocks-cobalt.h +++ b/include/dt-bindings/clock/msm-clocks-cobalt.h @@ -157,6 +157,7 @@ #define clk_gcc_usb3_phy_reset 0x03d559f1 #define clk_gcc_usb3phy_phy_reset 0xb1a4f885 #define clk_gcc_aggre1_ufs_axi_clk 0x873459d8 +#define clk_gcc_aggre1_ufs_axi_hw_ctl_clk 0x117a6f39 #define clk_gcc_aggre1_usb3_axi_clk 0xc5c3fbe8 #define clk_gcc_bimc_mss_q6_axi_clk 0x7437988f #define clk_gcc_blsp1_ahb_clk 0x8caa5b4f |