diff options
| author | Amit Nischal <anischal@codeaurora.org> | 2017-01-12 11:38:56 +0530 |
|---|---|---|
| committer | Amit Nischal <anischal@codeaurora.org> | 2017-01-12 12:17:09 +0530 |
| commit | 4e98c1b61a11f47fc85a7ac1b796903b59a34333 (patch) | |
| tree | 2f9241b41a86a7258965d0a19203a490bdc0a013 | |
| parent | 2dc96b1cbbdcf5aef3780696708012d55fec57f2 (diff) | |
clk: qcom: Add support to set rcg parent src for dp_pixel clock
For set rate, dp_pixel_clk_src rcg requires the correct parent
source to configured so add support for the same.
Change-Id: I9c8ae2904b47dbe0bc6845e2ca38fbd2f126a7e5
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
| -rw-r--r-- | drivers/clk/qcom/clk-rcg2.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index c37716e8273d..5f043371e22c 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013, 2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2013, 2016-2017, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -1063,7 +1063,8 @@ static int clk_dp_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long src_rate; unsigned long num, den; u32 mask = BIT(rcg->hid_width) - 1; - u32 hid_div; + u32 hid_div, cfg; + int i, num_parents = clk_hw_get_num_parents(hw); src_rate = clk_get_rate(clk_hw_get_parent(hw)->clk); if (src_rate <= 0) { @@ -1081,7 +1082,17 @@ static int clk_dp_set_rate(struct clk_hw *hw, unsigned long rate, return -EINVAL; } - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &hid_div); + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); + hid_div = cfg; + cfg &= CFG_SRC_SEL_MASK; + cfg >>= CFG_SRC_SEL_SHIFT; + + for (i = 0; i < num_parents; i++) + if (cfg == rcg->parent_map[i].cfg) { + f.src = rcg->parent_map[i].src; + break; + } + f.pre_div = hid_div; f.pre_div >>= CFG_SRC_DIV_SHIFT; f.pre_div &= mask; |