diff options
| author | Pavankumar Kondeti <pkondeti@codeaurora.org> | 2016-12-22 11:47:49 +0530 |
|---|---|---|
| committer | Pavankumar Kondeti <pkondeti@codeaurora.org> | 2017-02-13 10:35:33 +0530 |
| commit | 4e258da2a2fd30c65937b04685439f6cb994da71 (patch) | |
| tree | 72129b142fa015ec1852d212fab8b49bced4f0af | |
| parent | 88fee0f3817730e279872a381b760833a146aa5b (diff) | |
ARM: dts: msm: update CPU efficiency values for sdm660
Update the CPU efficiency values as per the post silicon
data.
Change-Id: I69321cf5b4cf80d91f27744dd3da617354f3474d
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/sdm660.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/qcom/sdm660.dtsi b/arch/arm/boot/dts/qcom/sdm660.dtsi index 6077699ebea9..794f4b79a174 100644 --- a/arch/arm/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660.dtsi @@ -152,7 +152,7 @@ qcom,limits-info = <&mitigation_profile1>; qcom,lmh-dcvs = <&lmh_dcvs1>; qcom,ea = <&ea4>; - efficiency = <1536>; + efficiency = <1638>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "arm,arch-cache"; @@ -179,7 +179,7 @@ qcom,limits-info = <&mitigation_profile2>; qcom,lmh-dcvs = <&lmh_dcvs1>; qcom,ea = <&ea5>; - efficiency = <1536>; + efficiency = <1638>; next-level-cache = <&L2_1>; L1_I_101: l1-icache { compatible = "arm,arch-cache"; @@ -202,7 +202,7 @@ qcom,limits-info = <&mitigation_profile3>; qcom,lmh-dcvs = <&lmh_dcvs1>; qcom,ea = <&ea6>; - efficiency = <1536>; + efficiency = <1638>; next-level-cache = <&L2_1>; L1_I_102: l1-icache { compatible = "arm,arch-cache"; @@ -225,7 +225,7 @@ qcom,limits-info = <&mitigation_profile4>; qcom,lmh-dcvs = <&lmh_dcvs1>; qcom,ea = <&ea7>; - efficiency = <1536>; + efficiency = <1638>; next-level-cache = <&L2_1>; L1_I_103: l1-icache { compatible = "arm,arch-cache"; |