diff options
| author | Adrian Salido-Moreno <adrianm@codeaurora.org> | 2013-08-20 10:38:05 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:20:19 -0700 |
| commit | 4d025148bebafc76f21dd127e0ca64f0c4605a26 (patch) | |
| tree | 63092f373a217ddd05702dd2d390048991342467 | |
| parent | 710843adf53e568841f98cc1b37b8fb48cc1f2c6 (diff) | |
msm: mdss: disable MDP hw underflow recovery
When MDP underflows, hardware will automatically try to issue a reset to
recover from it. Potential issue has been identified when reset happens
on two video interfaces at the same time which may lead to a hw lockup.
To avoid such situations disable the hardware underflow recovery, MDP
will still automatically recover at the beginning of next frame.
Change-Id: I3473486e229e67f6213db83a0ecb34333a977d4f
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_mdp.c | 4 | ||||
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_mdp_hwio.h | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/drivers/video/fbdev/msm/mdss_mdp.c b/drivers/video/fbdev/msm/mdss_mdp.c index 0511515de0a6..96bfeac897ec 100644 --- a/drivers/video/fbdev/msm/mdss_mdp.c +++ b/drivers/video/fbdev/msm/mdss_mdp.c @@ -889,6 +889,10 @@ int mdss_hw_init(struct mdss_data_type *mdata) mdata->mdp_rev = MDSS_MDP_REG_READ(MDSS_MDP_REG_HW_VERSION); pr_info_once("MDP Rev=%x\n", mdata->mdp_rev); + /* disable hw underrun recovery */ + writel_relaxed(0x0, mdata->mdp_base + + MDSS_MDP_REG_VIDEO_INTF_UNDERFLOW_CTL); + if (mdata->hw_settings) { struct mdss_hw_settings *hws = mdata->hw_settings; diff --git a/drivers/video/fbdev/msm/mdss_mdp_hwio.h b/drivers/video/fbdev/msm/mdss_mdp_hwio.h index 9f266b0e80bd..ece12a0a605f 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_hwio.h +++ b/drivers/video/fbdev/msm/mdss_mdp_hwio.h @@ -45,6 +45,7 @@ #define MDSS_MDP_REG_HIST_INTR_STATUS 0x00120 #define MDSS_MDP_REG_HIST_INTR_CLEAR 0x00124 +#define MDSS_MDP_REG_VIDEO_INTF_UNDERFLOW_CTL 0x003E0 #define MDSS_MDP_REG_SPLIT_DISPLAY_EN 0x003F4 #define MDSS_MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTRL 0x003F8 #define MDSS_MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTRL 0x004F0 |