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authorJustin Shen <chias@qca.qualcomm.com>2014-07-15 10:01:34 +0800
committerAkash Patel <c_akashp@qca.qualcomm.com>2014-07-28 19:45:27 -0700
commit49eecceac743baa8d7c7cae6d6a650fea372bc95 (patch)
treec4d0c2149e8c2cb819429f1720afc7a2b689926e
parentf07623b1ebc3e0b20c20bb52f048e29546bca726 (diff)
qcacld-new: Support netif_stop and netif_wake in HL system.
With CONFIG_PER_VDEV_TX_DESC_POOL_HL the tx descs are separated, but without netif_stop and netif_wake mechanism the OS would keep sending data to driver even the tx descs are out of allocated. So we implement netif_stop and netif_wake functionality via existed QCA_LL_TX_FLOW_CT architecture. Besides that, add vdev->tx_fl_hwm check in OL_TX_FLOW_CT_UNPAUSE_OS_Q to avoid to trigger original LL flow control mechanism. Change-Id: I6af319cf75ae5198c79d4d3bf01e3e20dc718a87 CRs-Fixed: 693874
-rw-r--r--CORE/CLD_TXRX/TXRX/ol_tx.c12
-rw-r--r--CORE/CLD_TXRX/TXRX/ol_tx_desc.c11
-rw-r--r--CORE/CLD_TXRX/TXRX/ol_tx_send.c3
-rw-r--r--CORE/CLD_TXRX/TXRX/ol_txrx.h4
4 files changed, 29 insertions, 1 deletions
diff --git a/CORE/CLD_TXRX/TXRX/ol_tx.c b/CORE/CLD_TXRX/TXRX/ol_tx.c
index 28178e579e04..1d9233bb8a60 100644
--- a/CORE/CLD_TXRX/TXRX/ol_tx.c
+++ b/CORE/CLD_TXRX/TXRX/ol_tx.c
@@ -510,6 +510,18 @@ ol_tx_hl_base(
if (adf_os_atomic_read(&vdev->tx_desc_count) <= ((ol_tx_desc_pool_size_hl(pdev->ctrl_pdev) >> 1) - 20)) {
tx_desc = ol_tx_desc_hl(pdev, vdev, msdu, &tx_msdu_info);
} else {
+#ifdef QCA_LL_TX_FLOW_CT
+ adf_os_spin_lock_bh(&pdev->tx_mutex);
+ if ( !(adf_os_atomic_read(&vdev->os_q_paused)) ) {
+ /* pause netif_queue */
+ adf_os_atomic_set(&vdev->os_q_paused, 1);
+ adf_os_spin_unlock_bh(&pdev->tx_mutex);
+ vdev->osif_flow_control_cb(vdev->osif_dev,
+ vdev->vdev_id, A_FALSE);
+ } else {
+ adf_os_spin_unlock_bh(&pdev->tx_mutex);
+ }
+#endif /* QCA_LL_TX_FLOW_CT */
tx_desc = NULL;
}
#else
diff --git a/CORE/CLD_TXRX/TXRX/ol_tx_desc.c b/CORE/CLD_TXRX/TXRX/ol_tx_desc.c
index 969dbc290293..45fbc598fbd4 100644
--- a/CORE/CLD_TXRX/TXRX/ol_tx_desc.c
+++ b/CORE/CLD_TXRX/TXRX/ol_tx_desc.c
@@ -42,6 +42,7 @@
#ifdef QCA_SUPPORT_SW_TXRX_ENCAP
#include <ol_txrx_encap.h> /* OL_TX_RESTORE_HDR, etc*/
#endif
+#include <ol_txrx.h>
#ifdef QCA_SUPPORT_TXDESC_SANITY_CHECKS
extern u_int32_t *g_dbg_htt_desc_end_addr, *g_dbg_htt_desc_start_addr;
@@ -140,6 +141,16 @@ ol_tx_desc_free(struct ol_txrx_pdev_t *pdev, struct ol_tx_desc_t *tx_desc)
pdev->tx_desc.freelist = (union ol_tx_desc_list_elem_t *) tx_desc;
pdev->tx_desc.num_free++;
#if defined(CONFIG_PER_VDEV_TX_DESC_POOL)
+#ifdef QCA_LL_TX_FLOW_CT
+ if ( (adf_os_atomic_read(&tx_desc->vdev->os_q_paused)) &&
+ (adf_os_atomic_read(&tx_desc->vdev->tx_desc_count) <
+ TXRX_HL_TX_FLOW_CTRL_VDEV_LOW_WATER_MARK) ) {
+ /* wakeup netif_queue */
+ adf_os_atomic_set(&tx_desc->vdev->os_q_paused, 0);
+ tx_desc->vdev->osif_flow_control_cb(tx_desc->vdev->osif_dev,
+ tx_desc->vdev->vdev_id, A_TRUE);
+ }
+#endif /* QCA_LL_TX_FLOW_CT */
adf_os_atomic_dec(&tx_desc->vdev->tx_desc_count);
tx_desc->vdev = NULL;
#endif
diff --git a/CORE/CLD_TXRX/TXRX/ol_tx_send.c b/CORE/CLD_TXRX/TXRX/ol_tx_send.c
index 67f2e525ade4..faf499ddf2a4 100644
--- a/CORE/CLD_TXRX/TXRX/ol_tx_send.c
+++ b/CORE/CLD_TXRX/TXRX/ol_tx_send.c
@@ -114,7 +114,8 @@
do { \
struct ol_txrx_vdev_t *vdev; \
TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) { \
- if (adf_os_atomic_read(&vdev->os_q_paused)) { \
+ if (adf_os_atomic_read(&vdev->os_q_paused) && \
+ (vdev->tx_fl_hwm != 0)) { \
adf_os_spin_lock(&pdev->tx_mutex); \
if (pdev->tx_desc.num_free > vdev->tx_fl_hwm) { \
adf_os_atomic_set(&vdev->os_q_paused, 0); \
diff --git a/CORE/CLD_TXRX/TXRX/ol_txrx.h b/CORE/CLD_TXRX/TXRX/ol_txrx.h
index 41ef6fa5eaee..fb29eca3095e 100644
--- a/CORE/CLD_TXRX/TXRX/ol_txrx.h
+++ b/CORE/CLD_TXRX/TXRX/ol_txrx.h
@@ -51,4 +51,8 @@ ol_tx_desc_pool_size_hl(ol_pdev_handle ctrl_pdev);
#define OL_TX_DESC_POOL_SIZE_MAX_HL 5000
#endif
+#ifdef CONFIG_PER_VDEV_TX_DESC_POOL
+#define TXRX_HL_TX_FLOW_CTRL_VDEV_LOW_WATER_MARK 400
+#endif
+
#endif /* _OL_TXRX__H_ */