soc: qcom: pil: Add support for the CX IPeak mitigation

Clear the CX iPeak bit if it was set by MSS before crash.
MSS sets this bit if it was in Turbo state. In a situation
where all the votes were set (including MSS), It would have
resulted in CDSP throttling. But when MSS is in crashed state,
It cannot be cleared by MSS, So PIL needs to do this. It
would allow possible clearance of throttle state.

Change-Id: Ia561436a362dc5b0e1cb22c30ce9f5b8bb027a1f
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>

4 files changed, 28 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
index 54a3c5689b9c..be5633024986 100644
--- a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
+++ b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
@@ -16,6 +16,8 @@ Required properties:
 		      If "halt_base" is in same 4K pages this register then
 		      this will be defined else "halt_q6", "halt_modem",
 		      "halt_nc" is required.
+		      "cxip_lm_vote_clear" needs to defined , in case PIL has to
+		      clear the CX Ipeak bit if it was set by MSS.
 - interrupts:         The modem watchdog interrupt
 - vdd_cx-supply:      Reference to the regulator that supplies the vdd_cx domain.
 - vdd_cx-voltage:     Voltage corner/level(max) for cx rail.
@@ -84,6 +86,8 @@ Optional properties:
 		    wordline clamp, and compiler memory clamp during MSS restart.
 - qcom,qdsp6v56-1-10: Boolean- Present if the qdsp version is v56 1.10
 - qcom,override-acc-1: Override the default ACC settings with this value if present.
+- qcom,cx-ipeak-vote: Boolean- Present if we need to set bit 5 of cxip_lm_vote_clear
+			 during modem shutdown
 
 Example:
 	qcom,mss@fc880000 {
diff --git a/drivers/soc/qcom/pil-msa.c b/drivers/soc/qcom/pil-msa.c
index 00ab1ce3b6b4..3c3ae693f615 100644
--- a/drivers/soc/qcom/pil-msa.c
+++ b/drivers/soc/qcom/pil-msa.c
@@ -75,6 +75,9 @@
 #define MSS_RESTART_ID			0xA
 
 #define MSS_MAGIC			0XAABADEAD
+/* CX_IPEAK Parameters */
+#define CX_IPEAK_MSS			BIT(5)
+
 enum scm_cmd {
 	PAS_MEM_SETUP_CMD = 2,
 };
@@ -304,6 +307,14 @@ int pil_mss_shutdown(struct pil_desc *pil)
 									ret);
 	}
 
+	/*
+	 *  If MSS was in turbo state before fatal error occurs, it would
+	 *  have set the vote bit. Since MSS is restarting, So PIL need to
+	 *  clear this bit. This may clear the throttle state.
+	 */
+	if (drv->cx_ipeak_vote)
+		writel_relaxed(CX_IPEAK_MSS, drv->cxip_lm_vote_clear);
+
 	ret = pil_mss_restart_reg(drv, 1);
 
 	if (drv->is_booted) {
diff --git a/drivers/soc/qcom/pil-q6v5-mss.c b/drivers/soc/qcom/pil-q6v5-mss.c
index bf6b11194111..4ece8cf7907f 100644
--- a/drivers/soc/qcom/pil-q6v5-mss.c
+++ b/drivers/soc/qcom/pil-q6v5-mss.c
@@ -270,6 +270,17 @@ static int pil_mss_loadable_init(struct modem_data *drv,
 		q6_desc->ops = &pil_msa_mss_ops_selfauth;
 	}
 
+	q6->cx_ipeak_vote = of_property_read_bool(pdev->dev.of_node,
+							"qcom,cx-ipeak-vote");
+	if (q6->cx_ipeak_vote) {
+		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+						    "cxip_lm_vote_clear");
+		q6->cxip_lm_vote_clear = devm_ioremap_resource(&pdev->dev,
+								res);
+		if (!q6->cxip_lm_vote_clear)
+			return -ENOMEM;
+	}
+
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "restart_reg");
 	if (!res) {
 		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
diff --git a/drivers/soc/qcom/pil-q6v5.h b/drivers/soc/qcom/pil-q6v5.h
index 9e8b8511e69b..23a7dfb62078 100644
--- a/drivers/soc/qcom/pil-q6v5.h
+++ b/drivers/soc/qcom/pil-q6v5.h
@@ -41,6 +41,7 @@ struct q6v5_data {
 	void __iomem *axi_halt_mss;
 	void __iomem *axi_halt_nc;
 	void __iomem *restart_reg;
+	void __iomem *cxip_lm_vote_clear;
 	struct regulator *vreg;
 	struct regulator *vreg_cx;
 	struct regulator *vreg_mx;
@@ -69,6 +70,7 @@ struct q6v5_data {
 	int override_acc_1;
 	bool ahb_clk_vote;
 	bool mx_spike_wa;
+	bool cx_ipeak_vote;
 };
 
 int pil_q6v5_make_proxy_votes(struct pil_desc *pil);