diff options
| author | AnilKumar Chimata <anilc@codeaurora.org> | 2016-12-13 14:55:10 +0530 |
|---|---|---|
| committer | Brahmaji K <bkomma@codeaurora.org> | 2017-02-03 16:37:31 +0530 |
| commit | 479ce2576da720fa1566f85ccc700f184c256b64 (patch) | |
| tree | b1019be05975b828eed50ddde81f65666d207701 | |
| parent | 336e24550387c399c29c3c5a2637c8f29c0a33c7 (diff) | |
ARM: dts: msm: Add ufs ice device node for sdm660
Add ufs ice device tree data to dts files with all
the necessary parameters, to enable the ICE driver
for crypto operations related to disk encryption.
Change-Id: I87463a1c1a064ba2a0597d095e6807931e7b5666
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/sdm660.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/sdm660.dtsi b/arch/arm/boot/dts/qcom/sdm660.dtsi index 358ff9c96292..1d78228ab062 100644 --- a/arch/arm/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660.dtsi @@ -1251,6 +1251,29 @@ < 2457600 >; }; + ufs_ice: ufsice@1db0000 { + compatible = "qcom,ice"; + reg = <0x1db0000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", "bus_clk", + "iface_clk", "ice_core_clk"; + clocks = <&clock_gcc GCC_UFS_AXI_CLK>, + <&clock_gcc GCC_UFS_CLKREF_CLK>, + <&clock_gcc GCC_UFS_AHB_CLK>, + <&clock_gcc GCC_UFS_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; + vdd-hba-supply = <&gdsc_ufs>; + qcom,msm-bus,name = "ufs_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 650 0 0>, /* No vote */ + <1 650 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + }; + sdhc_1: sdhci@c0c4000 { compatible = "qcom,sdhci-msm-v5"; reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>; @@ -2129,6 +2152,7 @@ interrupts = <0 265 0>; phys = <&ufsphy1>; phy-names = "ufsphy"; + ufs-qcom-crypto = <&ufs_ice>; clock-names = "core_clk", |