diff options
| author | Linux Build Service Account <lnxbuild@localhost> | 2018-02-21 06:59:19 -0800 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2018-02-21 06:59:18 -0800 |
| commit | 3f33435ef15fa7d065d7de941fda1167e00a4b6d (patch) | |
| tree | c43d8c3d3b2b3ea144247d088e07a987dd1d317b | |
| parent | 4bf5a81b41a643a4ab64855d2e6627c743979125 (diff) | |
| parent | ed6956bb2f5f5f70f3667c52097afa9b21957b8c (diff) | |
Merge "drm/msm/sde: setup alpha and bit format on qseedv3"
| -rw-r--r-- | drivers/gpu/drm/msm/sde/sde_hw_sspp.c | 28 |
1 files changed, 13 insertions, 15 deletions
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c index be620aebf850..f5b433c61776 100644 --- a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c +++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c @@ -595,10 +595,8 @@ static void _sde_hw_sspp_setup_scaler3(struct sde_hw_pipe *ctx, || !scaler3_cfg || !ctx || !ctx->cap || !ctx->cap->sblk) return; - if (!scaler3_cfg->enable) { - SDE_REG_WRITE(&ctx->hw, QSEED3_OP_MODE + idx, 0x0); - return; - } + if (!scaler3_cfg->enable) + goto end; op_mode |= BIT(0); op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16; @@ -608,9 +606,6 @@ static void _sde_hw_sspp_setup_scaler3(struct sde_hw_pipe *ctx, op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24; } - if (!SDE_FORMAT_IS_DX(sspp->layout.format)) - op_mode |= BIT(14); - op_mode |= (scaler3_cfg->blend_cfg & 1) << 31; op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0; @@ -638,10 +633,6 @@ static void _sde_hw_sspp_setup_scaler3(struct sde_hw_pipe *ctx, _sde_hw_sspp_setup_scaler3_lut(ctx, scaler3_cfg); if (ctx->cap->sblk->scaler_blk.version == 0x1002) { - if (sspp->layout.format->alpha_enable) { - op_mode |= BIT(10); - op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x1) << 30; - } phase_init = ((scaler3_cfg->init_phase_x[0] & 0x3F) << 0) | ((scaler3_cfg->init_phase_y[0] & 0x3F) << 8) | @@ -649,10 +640,6 @@ static void _sde_hw_sspp_setup_scaler3(struct sde_hw_pipe *ctx, ((scaler3_cfg->init_phase_y[1] & 0x3F) << 24); SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT + idx, phase_init); } else { - if (sspp->layout.format->alpha_enable) { - op_mode |= BIT(10); - op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x3) << 29; - } SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_Y_H + idx, scaler3_cfg->init_phase_x[0] & 0x1FFFFF); SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_Y_V + idx, @@ -683,6 +670,17 @@ static void _sde_hw_sspp_setup_scaler3(struct sde_hw_pipe *ctx, SDE_REG_WRITE(&ctx->hw, QSEED3_DST_SIZE + idx, dst); +end: + if (!SDE_FORMAT_IS_DX(sspp->layout.format)) + op_mode |= BIT(14); + + if (sspp->layout.format->alpha_enable) { + op_mode |= BIT(10); + if (ctx->cap->sblk->scaler_blk.version == 0x1002) + op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x1) << 30; + else + op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x3) << 29; + } SDE_REG_WRITE(&ctx->hw, QSEED3_OP_MODE + idx, op_mode); } |