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| author | Narender Ankam <nankam@codeaurora.org> | 2019-12-26 20:07:47 +0530 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2020-03-30 04:37:11 -0700 |
| commit | 3ee7a97688b46dc830a032e881e9d726a9430130 (patch) | |
| tree | 0f69e4319081414f5a3607baeef497a540a9b902 | |
| parent | a2864d557b2fc670dc01596d4fc184c7c2d063aa (diff) | |
msm: mdss: hdmi: reset TMDS_Bit_Clock_Ratio bit
When TMDS clock rate is lte 340MHz and downstream
sink doesn't support LTE_340MHz_scramble, reset
TMDS_Bit_Clock_Ratio bit in the sink.
Change-Id: Ib5a60c17d78e0c70071bec93e5081419d21bddd0
Signed-off-by: Narender Ankam <nankam@codeaurora.org>
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_hdmi_panel.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/video/fbdev/msm/mdss_hdmi_panel.c b/drivers/video/fbdev/msm/mdss_hdmi_panel.c index 20afa08155c1..f0447116539f 100644 --- a/drivers/video/fbdev/msm/mdss_hdmi_panel.c +++ b/drivers/video/fbdev/msm/mdss_hdmi_panel.c @@ -797,6 +797,15 @@ static int hdmi_panel_setup_scrambler(struct hdmi_panel *panel) rc = hdmi_setup_ddc_timers(panel->ddc, HDMI_TX_DDC_TIMER_SCRAMBLER_STATUS, timeout_hsync); } else { + tmds_clock_ratio = 0; + rc = hdmi_scdc_write(panel->ddc, + HDMI_TX_SCDC_TMDS_BIT_CLOCK_RATIO_UPDATE, + tmds_clock_ratio); + if (rc) { + pr_err("TMDS CLK RATIO ERR\n"); + return rc; + } + hdmi_scdc_write(panel->ddc, HDMI_TX_SCDC_SCRAMBLING_ENABLE, 0x0); |