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authorCarl Vanderlip <carlv@codeaurora.org>2012-12-10 16:48:18 -0800
committerDavid Keitel <dkeitel@codeaurora.org>2016-03-23 20:13:50 -0700
commit365d648992cf79cd4809ff19e6e5cfd4282576c0 (patch)
tree2fc0b82c9fc497c4ba766a62afefd44163a1e410
parentb4a1c0593986f791c80d55729d115d14b99a4207 (diff)
video: msm: Initialize Histogram LUT
Initialize the Histogram LUT during MDP probe. This is required otherwise the first histogram LUT request shows a brief period of garbled colors. Change-Id: I60b3077883d0f57dfe3987d7b459477a43da09a5 Signed-off-by: Carl Vanderlip <carlv@codeaurora.org>
-rw-r--r--drivers/video/fbdev/msm/mdss_mdp_pp.c34
1 files changed, 30 insertions, 4 deletions
diff --git a/drivers/video/fbdev/msm/mdss_mdp_pp.c b/drivers/video/fbdev/msm/mdss_mdp_pp.c
index 2dbba8100e25..0d606eaf7460 100644
--- a/drivers/video/fbdev/msm/mdss_mdp_pp.c
+++ b/drivers/video/fbdev/msm/mdss_mdp_pp.c
@@ -188,6 +188,8 @@ static void pp_update_gc_one_lut(u32 offset,
struct mdp_ar_gc_lut_data *lut_data);
static void pp_update_argc_lut(u32 offset,
struct mdp_pgc_lut_data *config);
+static void pp_update_hist_lut(u32 offset, struct mdp_hist_lut_data *cfg);
+
int mdss_mdp_csc_setup_data(u32 block, u32 blk_idx, u32 tbl_idx,
struct mdp_csc_cfg *data)
@@ -354,6 +356,17 @@ static void pp_gamut_config(struct mdp_gamut_cfg_data *gamut_cfg,
else if (gamut_cfg->flags & MDP_PP_OPS_ENABLE)
*gamut_sts |= PP_STS_ENABLE;
}
+
+/* Note: Assumes that its inputs have been checked by calling function */
+static void pp_update_hist_lut(u32 offset, struct mdp_hist_lut_data *cfg)
+{
+ int i;
+ for (i = 0; i < ENHIST_LUT_ENTRIES; i++)
+ MDSS_MDP_REG_WRITE(offset, cfg->data[i]);
+ /* swap */
+ MDSS_MDP_REG_WRITE(offset + 4, 1);
+}
+
static int pp_dspp_setup(u32 disp_num, struct mdss_mdp_ctl *ctl,
struct mdss_mdp_mixer *mixer)
{
@@ -466,10 +479,7 @@ static int pp_dspp_setup(u32 disp_num, struct mdss_mdp_ctl *ctl,
enhist_cfg = &mdss_pp_res->enhist_disp_cfg[disp_num];
if (enhist_cfg->ops & MDP_PP_OPS_WRITE) {
offset = base + MDSS_MDP_REG_DSPP_HIST_LUT_BASE;
- for (i = 0; i < ENHIST_LUT_ENTRIES; i++)
- MDSS_MDP_REG_WRITE(offset, enhist_cfg->data[i]);
- /* swap */
- MDSS_MDP_REG_WRITE(offset + 4, 1);
+ pp_update_hist_lut(offset, enhist_cfg);
}
if (enhist_cfg->ops & MDP_PP_OPS_DISABLE)
pp_sts->enhist_sts &= ~PP_STS_ENABLE;
@@ -555,6 +565,10 @@ int mdss_mdp_pp_setup(struct mdss_mdp_ctl *ctl)
int mdss_mdp_pp_init(struct device *dev)
{
int ret = 0;
+ int i;
+ u32 offset;
+ uint32_t data[ENHIST_LUT_ENTRIES];
+
mutex_lock(&mdss_pp_mutex);
if (!mdss_pp_res) {
mdss_pp_res = devm_kzalloc(dev, sizeof(*mdss_pp_res),
@@ -563,6 +577,18 @@ int mdss_mdp_pp_init(struct device *dev)
pr_err("%s mdss_pp_res allocation failed!", __func__);
ret = -ENOMEM;
}
+
+ for (i = 0; i < ENHIST_LUT_ENTRIES; i++)
+ data[i] = i;
+
+ /* Initialize Histogram LUT for all DSPPs */
+ for (i = 0; i < MDSS_MDP_MAX_DSPP; i++) {
+ offset = MDSS_MDP_REG_DSPP_OFFSET(i) +
+ MDSS_MDP_REG_DSPP_HIST_LUT_BASE;
+ mdss_pp_res->enhist_disp_cfg[i].data = data;
+ pp_update_hist_lut(offset,
+ &mdss_pp_res->enhist_disp_cfg[i]);
+ }
}
mutex_unlock(&mdss_pp_mutex);
return ret;