diff options
| author | Chandan Uddaraju <chandanu@codeaurora.org> | 2016-04-27 15:16:25 -0700 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-05-09 18:35:24 -0700 |
| commit | 35618cee112744d1d8453ca718af7056bfffa2a1 (patch) | |
| tree | f6d6b269e712b8bace91a38d5c4de39be7543e5e | |
| parent | 3ee6103a8dcace1b8f6aa20fc3c5844ca51dd829 (diff) | |
ARM: dts: msm: add MDSS Display-Port PLL device node for msmcobalt
List all the resources needed by the MDSS DP PLL device and add the
corresponding device node for msmcobalt. The DP PLL is the source for
all the branch clocks needed to drive pixel data over the DP interface.
CRs-Fixed: 1009740
Change-Id: I1a373a7602f8dbad3fb547690a87a28aea73aadd
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt-mdss-pll.dtsi | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mdss-pll.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-mdss-pll.dtsi index f5c5a5e939ac..97c63e02b716 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-mdss-pll.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-mdss-pll.dtsi @@ -75,4 +75,38 @@ }; }; }; + + mdss_dp_pll: qcom,mdss_dp_pll@ca20000 { + compatible = "qcom,mdss_dp_pll_cobalt"; + label = "MDSS DP PLL"; + cell-index = <0>; + #clock-cells = <1>; + + reg = <0xca20c00 0x190>, + <0xca20000 0x910>, + <0x0c8c2300 0x8>; + reg-names = "pll_base", "phy_base", "gdsc_base"; + + gdsc-supply = <&gdsc_mdss>; + + clocks = <&clock_mmss clk_mmss_mdss_ahb_clk>; + clock-names = "iface_clk"; + clock-rate = <0>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + }; + }; + }; |