diff options
| author | Andrey Markovytch <andreym@codeaurora.org> | 2016-08-11 13:10:59 +0300 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-08-11 03:13:58 -0700 |
| commit | 32d2461585fd563649efcee7e350c5ccba2e3b3a (patch) | |
| tree | 2fba7ac6e62ecea1de3410005edee0504b80e0c6 | |
| parent | 9d822a9489cceee0be66a722211426c544b04cdf (diff) | |
ice: added missing register dump in case of error for ICE 3.0
QCOM_ICE_INVALID_CCFG_ERR_STTS is now also dumped in case of error
for ICE 3.0
Change-Id: Ib7f522d0143f5131880c8c1badf4e64461810e72
Signed-off-by: Andrey Markovytch <andreym@codeaurora.org>
| -rw-r--r-- | drivers/crypto/msm/ice.c | 7 | ||||
| -rw-r--r-- | drivers/crypto/msm/iceregs.h | 11 |
2 files changed, 18 insertions, 0 deletions
diff --git a/drivers/crypto/msm/ice.c b/drivers/crypto/msm/ice.c index 3e856d0bbbe9..795d553f3318 100644 --- a/drivers/crypto/msm/ice.c +++ b/drivers/crypto/msm/ice.c @@ -1237,6 +1237,13 @@ static void qcom_ice_debug(struct platform_device *pdev) qcom_ice_readl(ice_dev, QCOM_ICE_REGS_NON_SEC_IRQ_MASK), qcom_ice_readl(ice_dev, QCOM_ICE_REGS_NON_SEC_IRQ_CLR)); + if (ICE_REV(ice_dev->ice_hw_version, MAJOR) > 2) { + pr_err("%s: ICE INVALID CCFG ERR STTS: 0x%08x\n", + ice_dev->ice_instance_type, + qcom_ice_readl(ice_dev, + QCOM_ICE_INVALID_CCFG_ERR_STTS)); + } + if ((ICE_REV(ice_dev->ice_hw_version, MAJOR) > 2) || ((ICE_REV(ice_dev->ice_hw_version, MAJOR) == 2) && (ICE_REV(ice_dev->ice_hw_version, MINOR) >= 1))) { diff --git a/drivers/crypto/msm/iceregs.h b/drivers/crypto/msm/iceregs.h index 4fa682e4a26d..b59dccb679da 100644 --- a/drivers/crypto/msm/iceregs.h +++ b/drivers/crypto/msm/iceregs.h @@ -39,8 +39,19 @@ #define QCOM_ICE_REGS_PARAMETERS_3 0x001C #define QCOM_ICE_REGS_PARAMETERS_4 0x0020 #define QCOM_ICE_REGS_PARAMETERS_5 0x0024 + + +/* QCOM ICE v3.X only */ +#define QCOM_ICE_GENERAL_ERR_STTS 0x0040 +#define QCOM_ICE_INVALID_CCFG_ERR_STTS 0x0030 +#define QCOM_ICE_GENERAL_ERR_MASK 0x0044 + + +/* QCOM ICE v2.X only */ #define QCOM_ICE_REGS_NON_SEC_IRQ_STTS 0x0040 #define QCOM_ICE_REGS_NON_SEC_IRQ_MASK 0x0044 + + #define QCOM_ICE_REGS_NON_SEC_IRQ_CLR 0x0048 #define QCOM_ICE_REGS_STREAM1_ERROR_SYNDROME1 0x0050 #define QCOM_ICE_REGS_STREAM1_ERROR_SYNDROME2 0x0054 |