diff options
| author | Satya Durga Srinivasu Prabhala <satyap@codeaurora.org> | 2016-03-22 11:57:22 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 21:26:09 -0700 |
| commit | 2e4ef2d3dc44cc494dd3780abdd00abd2b6c0be7 (patch) | |
| tree | 381050efebd1bf22102dae9bc05bc6d7568a6bbb | |
| parent | 09b5ecaf8ca3b2a6ee223861eac11cbabacd37a2 (diff) | |
defconfig: arm64: enable IPC_LOGGING & EXTCON for msmcortex
IPC_LOGGING allows the debug logging for IPC Drivers and
QPNP_SMBCHARGER depends on EXTCON.
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
| -rw-r--r-- | arch/arm64/configs/msmcortex-perf_defconfig | 2 | ||||
| -rw-r--r-- | arch/arm64/configs/msmcortex_defconfig | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/configs/msmcortex-perf_defconfig b/arch/arm64/configs/msmcortex-perf_defconfig index 8adae38ccb64..4684e4c94ced 100644 --- a/arch/arm64/configs/msmcortex-perf_defconfig +++ b/arch/arm64/configs/msmcortex-perf_defconfig @@ -251,6 +251,7 @@ CONFIG_TRACER_PKT=y CONFIG_MSM_CORE_CTL_HELPER=y CONFIG_REMOTE_SPINLOCK_MSM=y CONFIG_ARM_SMMU=y +CONFIG_EXTCON=y CONFIG_PHY_XGENE=y CONFIG_ANDROID=y CONFIG_ANDROID_BINDER_IPC=y @@ -286,6 +287,7 @@ CONFIG_PANIC_TIMEOUT=5 CONFIG_SCHEDSTATS=y CONFIG_TIMER_STATS=y # CONFIG_DEBUG_PREEMPT is not set +CONFIG_IPC_LOGGING=y CONFIG_FUNCTION_TRACER=y CONFIG_SCHED_TRACER=y CONFIG_MEMTEST=y diff --git a/arch/arm64/configs/msmcortex_defconfig b/arch/arm64/configs/msmcortex_defconfig index f9a0df9ac808..6a4dd47123fc 100644 --- a/arch/arm64/configs/msmcortex_defconfig +++ b/arch/arm64/configs/msmcortex_defconfig @@ -279,6 +279,7 @@ CONFIG_ARM_SMMU=y CONFIG_IOMMU_DEBUG=y CONFIG_IOMMU_DEBUG_TRACKING=y CONFIG_IOMMU_TESTS=y +CONFIG_EXTCON=y CONFIG_PHY_XGENE=y CONFIG_ANDROID=y CONFIG_ANDROID_BINDER_IPC=y @@ -318,6 +319,7 @@ CONFIG_PANIC_TIMEOUT=5 CONFIG_SCHEDSTATS=y CONFIG_TIMER_STATS=y # CONFIG_DEBUG_PREEMPT is not set +CONFIG_IPC_LOGGING=y CONFIG_QCOM_RTB=y CONFIG_QCOM_RTB_SEPARATE_CPUS=y CONFIG_FUNCTION_TRACER=y |