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| author | Linux Build Service Account <lnxbuild@quicinc.com> | 2018-02-06 23:46:58 -0800 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2018-02-06 23:46:57 -0800 |
| commit | 2be3fbd7ed1d59e232591a49d5616b1bc45df20d (patch) | |
| tree | 287e89d2fd30e58856285a7e9bf3f4b6fac3d9aa | |
| parent | 84d2490998f71c372f975b6a775fc323e3127214 (diff) | |
| parent | e8df2440a48f8459083f1d7625d2e125e2b34881 (diff) | |
Merge "drm/msm: restore perfcounter after turning on GPMU"
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index e493c2fee762..53951a3d355a 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1174,10 +1174,6 @@ static int a5xx_pm_resume(struct msm_gpu *gpu) if (ret) return ret; - - /* Restore all the counters before turning on the GPMU */ - a5xx_counters_restore(gpu); - /* Turn the RBCCU domain first to limit the chances of voltage droop */ gpu_write(gpu, REG_A5XX_GPMU_RBCCU_POWER_CNTL, 0x778000); @@ -1201,6 +1197,8 @@ static int a5xx_pm_resume(struct msm_gpu *gpu) DRM_ERROR("%s: timeout waiting for SP GDSC enable\n", gpu->name); + a5xx_counters_restore(gpu); + return ret; } |