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authorDeepak Katragadda <dkatraga@codeaurora.org>2016-10-05 18:26:32 -0700
committerDeepak Katragadda <dkatraga@codeaurora.org>2016-10-05 18:26:32 -0700
commit280dd014654312714dc757dae3bb55acc4dfa2ec (patch)
treed53be6124190c94f42a7ce35b8d0d0bfc60a7664
parent057bdafd976ca7609ed223dbd4473d535bcb6459 (diff)
clk: msm: clock-mmss-cobalt: Update the CPP clock frequency table
Update the frequency table for the cpp_clk_src RCG to support running it at 384 MHz and 404 MHz. Change-Id: I288f3ae985d27a563daff56eca5dda0e72021272 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
-rw-r--r--drivers/clk/msm/clock-mmss-cobalt.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/msm/clock-mmss-cobalt.c b/drivers/clk/msm/clock-mmss-cobalt.c
index 873dd40d3a44..98b1409d1654 100644
--- a/drivers/clk/msm/clock-mmss-cobalt.c
+++ b/drivers/clk/msm/clock-mmss-cobalt.c
@@ -399,6 +399,8 @@ static struct clk_freq_tbl ftbl_cpp_clk_src[] = {
static struct clk_freq_tbl ftbl_cpp_clk_src_vq[] = {
F_MM( 100000000, mmsscc_gpll0, 6, 0, 0),
F_MM( 200000000, mmsscc_gpll0, 3, 0, 0),
+ F_MM( 384000000, mmpll4_pll_out, 2, 0, 0),
+ F_MM( 404000000, mmpll0_pll_out, 2, 0, 0),
F_MM( 480000000, mmpll7_pll_out, 2, 0, 0),
F_MM( 576000000, mmpll10_pll_out, 1, 0, 0),
F_MM( 600000000, mmsscc_gpll0, 1, 0, 0),