diff options
| author | Sujit Reddy Thumma <sthumma@codeaurora.org> | 2014-02-14 08:37:47 +0530 |
|---|---|---|
| committer | Subhash Jadavani <subhashj@codeaurora.org> | 2016-05-27 10:29:02 -0700 |
| commit | 1fc03424501669b8d6df474c42328123a4297055 (patch) | |
| tree | cc3361e3c1f9ad62b78f2196cce3a4e0f5687842 | |
| parent | c0a43df5f6fd68fa027e85449c9803ad11675dba (diff) | |
mmc: sdhci: clear interrupt status during controller reset
In some cases, it is possible that the hardware might trigger
an interrupt just about the same time the software tries to
reset the controller. In such case, the hardware interrupt will
be handled after the current thread release spin lock. This leads
to spurious interrupt handling after the completion of reset.
Change-Id: I75211adee1179b0636a918f5ceb68a072ad02a6c
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
| -rw-r--r-- | drivers/mmc/host/sdhci.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 022c6319a0c8..51eae3ff259e 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -250,6 +250,10 @@ void sdhci_reset(struct sdhci_host *host, u8 mask) (mask & SDHCI_RESET_ALL)) host->ops->check_power_status(host, REQ_BUS_OFF); + /* clear pending normal/error interrupt status */ + sdhci_writel(host, sdhci_readl(host, SDHCI_INT_STATUS), + SDHCI_INT_STATUS); + /* hw clears the bit when it's done */ while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { if (timeout == 0) { |