ARM: dts: msm: add PCIe PHY sequence for MSM8996 agave

Add PHY init sequence based on new settings so that PCIe
PHY can be brought up on MSM8996 agave.

Change-Id: Iece881346523cf3f5b06314f38fc65d5afdb2986
Signed-off-by: Tony Truong <truong@codeaurora.org>

1 files changed, 231 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi b/arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi
index 464ee6a77134..fcec6b2fed06 100644
--- a/arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi
@@ -45,12 +45,166 @@
 };
 
 &pcie0 {
+	qcom,phy-sequence = <0x404 0x01 0x00
+				0x034 0x1c 0x00
+				0x038 0x10 0x00
+				0x174 0x33 0x00
+				0x194 0x06 0x00
+				0x0c8 0x42 0x00
+				0x128 0x00 0x00
+				0x144 0xff 0x00
+				0x148 0x1f 0x00
+				0x178 0x01 0x00
+				0x19c 0x01 0x00
+				0x18c 0x00 0x00
+				0x184 0x0a 0x00
+				0x00c 0x09 0x00
+				0x0d0 0x82 0x00
+				0x0e4 0x03 0x00
+				0x0e0 0x55 0x00
+				0x0dc 0x55 0x00
+				0x054 0x00 0x00
+				0x050 0x1a 0x00
+				0x04c 0x0a 0x00
+				0x174 0x33 0x00
+				0x03c 0x02 0x00
+				0x040 0x1f 0x00
+				0x0ac 0x04 0x00
+				0x078 0x0b 0x00
+				0x084 0x16 0x00
+				0x090 0x28 0x00
+				0x10c 0x00 0x00
+				0x108 0x80 0x00
+				0x010 0x01 0x00
+				0x01c 0x31 0x00
+				0x020 0x01 0x00
+				0x014 0x02 0x00
+				0x018 0x00 0x00
+				0x024 0x2f 0x00
+				0x028 0x19 0x00
+				0x0c4 0x15 0x00
+				0x070 0x0f 0x00
+				0x048 0x0f 0x00
+				0x074 0x19 0x00
+				0x038 0x10 0x00
+				0x178 0x00 0x00
+				0x0c4 0x40 0x00
+				0x400 0x00 0x00
+				0x408 0x03 0x00>;
+
+	qcom,port-phy-sequence = <0x1068 0x45 0x00
+				0x1094 0x06 0x00
+				0x1310 0x1c 0x00
+				0x1318 0x17 0x00
+				0x12d8 0x01 0x00
+				0x12dc 0x00 0x00
+				0x12e0 0xdb 0x00
+				0x1320 0x18 0x00
+				0x121c 0x04 0x00
+				0x1210 0x04 0x00
+				0x1458 0x4c 0x00
+				0x14a0 0x00 0x00
+				0x14a4 0x01 0x00
+				0x14a8 0x05 0x00
+				0x1248 0x4b 0x00
+				0x131c 0x14 0x00
+				0x1454 0x05 0x00
+				0x1404 0x02 0x00
+				0x146c 0x00 0x00
+				0x1460 0xa3 0x00
+				0x1318 0x19 0x00
+				0x1428 0x0e 0x00
+				0x1054 0x08 0x00
+				0x14f8 0x04 0x00
+				0x14ec 0x06 0x00
+				0x104c 0x2e 0x00
+				0x1404 0x03 0x0a
+				0x1400 0x00 0x00
+				0x1408 0x0a 0x00>;
+
 	/delete-property/ qcom,l1-supported;
 	/delete-property/ qcom,l1ss-supported;
 	/delete-property/ qcom,aux-clk-sync;
 };
 
 &pcie1 {
+	qcom,phy-sequence = <0x404 0x01 0x00
+				0x034 0x1c 0x00
+				0x038 0x10 0x00
+				0x174 0x33 0x00
+				0x194 0x06 0x00
+				0x0c8 0x42 0x00
+				0x128 0x00 0x00
+				0x144 0xff 0x00
+				0x148 0x1f 0x00
+				0x178 0x01 0x00
+				0x19c 0x01 0x00
+				0x18c 0x00 0x00
+				0x184 0x0a 0x00
+				0x00c 0x09 0x00
+				0x0d0 0x82 0x00
+				0x0e4 0x03 0x00
+				0x0e0 0x55 0x00
+				0x0dc 0x55 0x00
+				0x054 0x00 0x00
+				0x050 0x1a 0x00
+				0x04c 0x0a 0x00
+				0x174 0x33 0x00
+				0x03c 0x02 0x00
+				0x040 0x1f 0x00
+				0x0ac 0x04 0x00
+				0x078 0x0b 0x00
+				0x084 0x16 0x00
+				0x090 0x28 0x00
+				0x10c 0x00 0x00
+				0x108 0x80 0x00
+				0x010 0x01 0x00
+				0x01c 0x31 0x00
+				0x020 0x01 0x00
+				0x014 0x02 0x00
+				0x018 0x00 0x00
+				0x024 0x2f 0x00
+				0x028 0x19 0x00
+				0x0c4 0x15 0x00
+				0x070 0x0f 0x00
+				0x048 0x0f 0x00
+				0x074 0x19 0x00
+				0x038 0x10 0x00
+				0x178 0x00 0x00
+				0x0c4 0x40 0x00
+				0x400 0x00 0x00
+				0x408 0x03 0x00>;
+
+	qcom,port-phy-sequence = <0x2068 0x45 0x00
+				0x2094 0x06 0x00
+				0x2310 0x1c 0x00
+				0x2318 0x17 0x00
+				0x22d8 0x01 0x00
+				0x22dc 0x00 0x00
+				0x22e0 0xdb 0x00
+				0x2320 0x18 0x00
+				0x221c 0x04 0x00
+				0x2210 0x04 0x00
+				0x2458 0x4c 0x00
+				0x24a0 0x00 0x00
+				0x24a4 0x01 0x00
+				0x24a8 0x05 0x00
+				0x2248 0x4b 0x00
+				0x231c 0x14 0x00
+				0x2454 0x05 0x00
+				0x2404 0x02 0x00
+				0x246c 0x00 0x00
+				0x2460 0xa3 0x00
+				0x2318 0x19 0x00
+				0x2428 0x0e 0x00
+				0x2054 0x08 0x00
+				0x24f8 0x04 0x00
+				0x24ec 0x06 0x00
+				0x204c 0x2e 0x00
+				0x2404 0x03 0x0a
+				0x2400 0x00 0x00
+				0x2408 0x0a 0x00>;
+
 	qcom,msi-gicm-addr = <0x09BD0040>;
 	qcom,msi-gicm-base = <0x240>;
 
@@ -60,6 +214,83 @@
 };
 
 &pcie2 {
+	qcom,phy-sequence = <0x404 0x01 0x00
+				0x034 0x1c 0x00
+				0x038 0x10 0x00
+				0x174 0x33 0x00
+				0x194 0x06 0x00
+				0x0c8 0x42 0x00
+				0x128 0x00 0x00
+				0x144 0xff 0x00
+				0x148 0x1f 0x00
+				0x178 0x01 0x00
+				0x19c 0x01 0x00
+				0x18c 0x00 0x00
+				0x184 0x0a 0x00
+				0x00c 0x09 0x00
+				0x0d0 0x82 0x00
+				0x0e4 0x03 0x00
+				0x0e0 0x55 0x00
+				0x0dc 0x55 0x00
+				0x054 0x00 0x00
+				0x050 0x1a 0x00
+				0x04c 0x0a 0x00
+				0x174 0x33 0x00
+				0x03c 0x02 0x00
+				0x040 0x1f 0x00
+				0x0ac 0x04 0x00
+				0x078 0x0b 0x00
+				0x084 0x16 0x00
+				0x090 0x28 0x00
+				0x10c 0x00 0x00
+				0x108 0x80 0x00
+				0x010 0x01 0x00
+				0x01c 0x31 0x00
+				0x020 0x01 0x00
+				0x014 0x02 0x00
+				0x018 0x00 0x00
+				0x024 0x2f 0x00
+				0x028 0x19 0x00
+				0x0c4 0x15 0x00
+				0x070 0x0f 0x00
+				0x048 0x0f 0x00
+				0x074 0x19 0x00
+				0x038 0x10 0x00
+				0x178 0x00 0x00
+				0x0c4 0x40 0x00
+				0x400 0x00 0x00
+				0x408 0x03 0x00>;
+
+	qcom,port-phy-sequence = <0x3068 0x45 0x00
+				0x3094 0x06 0x00
+				0x3310 0x1c 0x00
+				0x3318 0x17 0x00
+				0x32d8 0x01 0x00
+				0x32dc 0x00 0x00
+				0x32e0 0xdb 0x00
+				0x3320 0x18 0x00
+				0x321c 0x04 0x00
+				0x3210 0x04 0x00
+				0x3458 0x4c 0x00
+				0x34a0 0x00 0x00
+				0x34a4 0x01 0x00
+				0x34a8 0x05 0x00
+				0x3248 0x4b 0x00
+				0x331c 0x14 0x00
+				0x3454 0x05 0x00
+				0x3404 0x02 0x00
+				0x346c 0x00 0x00
+				0x3460 0xa3 0x00
+				0x3318 0x19 0x00
+				0x3428 0x0e 0x00
+				0x3054 0x08 0x00
+				0x34f8 0x04 0x00
+				0x34ec 0x06 0x00
+				0x304c 0x2e 0x00
+				0x3404 0x03 0x0a
+				0x3400 0x00 0x00
+				0x3408 0x0a 0x00>;
+
 	/delete-property/ qcom,l1-supported;
 	/delete-property/ qcom,l1ss-supported;
 	/delete-property/ qcom,aux-clk-sync;