clk: mdss: Replace thulium with msm8996 in pll

Use appropriate SOC name.

Change-Id: I10b554129775e4b73e15ab173de7f8f3ef0a6b58
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>

10 files changed, 153 insertions, 153 deletions

diff --git a/Documentation/devicetree/bindings/fb/mdss-pll.txt b/Documentation/devicetree/bindings/fb/mdss-pll.txt
index 4b571cefe8a1..d1749b0ba0ab 100644
--- a/Documentation/devicetree/bindings/fb/mdss-pll.txt
+++ b/Documentation/devicetree/bindings/fb/mdss-pll.txt
@@ -11,7 +11,7 @@ Required properties:
 			"qcom,mdss_dsi_pll_8994", "qcom,mdss_dsi_pll_8909",
 			"qcom,mdss_hdmi_pll", "qcom,mdss_hdmi_pll_8994",
 			"qcom,mdss_dsi_pll_8992", "qcom,mdss_hdmi_pll_8992",
-			"qcom,mdss_dsi_pll_thulium", "qcom,mdss_hdmi_pll_thulium"
+			"qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996"
 - cell-index:		Specifies the controller used
 - reg:			offset and length of the register set for the device.
 - reg-names :		names to refer to register sets related to this device
diff --git a/drivers/clk/msm/mdss/Makefile b/drivers/clk/msm/mdss/Makefile
index 7d3911af49f1..f3d6106facde 100644
--- a/drivers/clk/msm/mdss/Makefile
+++ b/drivers/clk/msm/mdss/Makefile
@@ -4,9 +4,9 @@ obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-util.o mdss-dsi-20nm-pll-util.o
 obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-28hpm.o
 obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-28lpm.o
 obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-20nm.o
-obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-thulium.o
-obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-thulium-util.o
+obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996.o
+obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996-util.o
 obj-$(CONFIG_MSM_MDSS_PLL) += mdss-edp-pll-28hpm.o
 obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-28hpm.o
 obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-20nm.o
-obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-thulium.o
+obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-8996.o
diff --git a/drivers/clk/msm/mdss/mdss-dsi-pll-thulium-util.c b/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c
index 3a2603246558..0a9aa8d37d78 100644
--- a/drivers/clk/msm/mdss/mdss-dsi-pll-thulium-util.c
+++ b/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c
@@ -20,27 +20,27 @@
 
 #include "mdss-pll.h"
 #include "mdss-dsi-pll.h"
-#include "mdss-dsi-pll-thulium.h"
+#include "mdss-dsi-pll-8996.h"
 
 #define DSI_PLL_POLL_MAX_READS                  15
 #define DSI_PLL_POLL_TIMEOUT_US                 1000
 
-int set_mdss_byte_mux_sel_thulium(struct mux_clk *clk, int sel)
+int set_mdss_byte_mux_sel_8996(struct mux_clk *clk, int sel)
 {
 	return 0;
 }
 
-int get_mdss_byte_mux_sel_thulium(struct mux_clk *clk)
+int get_mdss_byte_mux_sel_8996(struct mux_clk *clk)
 {
 	return 0;
 }
 
-int set_mdss_pixel_mux_sel_thulium(struct mux_clk *clk, int sel)
+int set_mdss_pixel_mux_sel_8996(struct mux_clk *clk, int sel)
 {
 	return 0;
 }
 
-int get_mdss_pixel_mux_sel_thulium(struct mux_clk *clk)
+int get_mdss_pixel_mux_sel_8996(struct mux_clk *clk)
 {
 	return 0;
 }
@@ -70,7 +70,7 @@ int post_n1_div_set_div(struct div_clk *clk, int div)
 	pr_debug("div=%d postdiv=%x n1div=%x\n",
 			div, pout->pll_postdiv, pout->pll_n1div);
 
-	/* registers commited at pll_db_commit_thulium() */
+	/* registers commited at pll_db_commit_8996() */
 
 	return 0;
 }
@@ -165,7 +165,7 @@ int n2_div_get_div(struct div_clk *clk)
 	return n2div;
 }
 
-static bool pll_is_pll_locked_thulium(struct mdss_pll_resources *pll)
+static bool pll_is_pll_locked_8996(struct mdss_pll_resources *pll)
 {
 	u32 status;
 	bool pll_locked;
@@ -194,21 +194,21 @@ static bool pll_is_pll_locked_thulium(struct mdss_pll_resources *pll)
 	return pll_locked;
 }
 
-static void dsi_pll_start_thulium(void __iomem *pll_base)
+static void dsi_pll_start_8996(void __iomem *pll_base)
 {
 	pr_debug("start PLL at base=%p\n", pll_base);
 
 	MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_PLL_CNTRL, 1);
 }
 
-static void dsi_pll_stop_thulium(void __iomem *pll_base)
+static void dsi_pll_stop_8996(void __iomem *pll_base)
 {
 	pr_debug("stop PLL at base=%p\n", pll_base);
 
 	MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_PLL_CNTRL, 0);
 }
 
-int dsi_pll_enable_seq_thulium(struct mdss_pll_resources *pll)
+int dsi_pll_enable_seq_8996(struct mdss_pll_resources *pll)
 {
 	int rc = 0;
 
@@ -217,14 +217,14 @@ int dsi_pll_enable_seq_thulium(struct mdss_pll_resources *pll)
 		return -EINVAL;
 	}
 
-	dsi_pll_start_thulium(pll->pll_base);
+	dsi_pll_start_8996(pll->pll_base);
 
 	/*
 	 * both DSIPHY_PLL_CLKBUFLR_EN and DSIPHY_CMN_GLBL_TEST_CTRL
-	 * enabled at mdss_dsi_thulium_phy_config()
+	 * enabled at mdss_dsi_8996_phy_config()
 	 */
 
-	if (!pll_is_pll_locked_thulium(pll)) {
+	if (!pll_is_pll_locked_8996(pll)) {
 		pr_err("DSI PLL lock failed\n");
 		rc = -EINVAL;
 		goto init_lock_err;
@@ -280,7 +280,7 @@ static void dsi_pll_disable(struct clk *c)
 
 	pll->handoff_resources = false;
 
-	dsi_pll_stop_thulium(pll->pll_base);
+	dsi_pll_stop_8996(pll->pll_base);
 
 	/* stop pll output */
 	MDSS_PLL_REG_W(pll->pll_base, DSIPHY_PLL_CLKBUFLR_EN, 0);
@@ -296,7 +296,7 @@ static void dsi_pll_disable(struct clk *c)
 	return;
 }
 
-static void mdss_dsi_pll_thulium_input_init(struct dsi_pll_db *pdb)
+static void mdss_dsi_pll_8996_input_init(struct dsi_pll_db *pdb)
 {
 	pdb->in.fref = 19200000;	/* 19.2 Mhz*/
 	pdb->in.fdata = 0;		/* bit clock rate */
@@ -335,7 +335,7 @@ static void mdss_dsi_pll_thulium_input_init(struct dsi_pll_db *pdb)
 	pdb->in.pll_r3ctrl = 1;		/* 1 */
 }
 
-static void pll_thulium_dec_frac_calc(struct dsi_pll_db *pdb,
+static void pll_8996_dec_frac_calc(struct dsi_pll_db *pdb,
 			 s64 vco_clk_rate, s64 fref)
 {
 	struct dsi_pll_input *pin = &pdb->in;
@@ -374,7 +374,7 @@ static void pll_thulium_dec_frac_calc(struct dsi_pll_db *pdb,
 	pout->cmn_ldo_cntrl = 0x1c;
 }
 
-static u32 pll_thulium_kvco_slop(u32 vrate)
+static u32 pll_8996_kvco_slop(u32 vrate)
 {
 	u32 slop = 0;
 
@@ -388,7 +388,7 @@ static u32 pll_thulium_kvco_slop(u32 vrate)
 	return slop;
 }
 
-static void pll_thulium_calc_vco_count(struct dsi_pll_db *pdb,
+static void pll_8996_calc_vco_count(struct dsi_pll_db *pdb,
 			 s64 vco_clk_rate, s64 fref)
 {
 	struct dsi_pll_input *pin = &pdb->in;
@@ -413,7 +413,7 @@ static void pll_thulium_calc_vco_count(struct dsi_pll_db *pdb,
 	data -= 1;
 	pout->pll_kvco_div_ref = data;
 
-	cnt = pll_thulium_kvco_slop(vco_clk_rate);
+	cnt = pll_8996_kvco_slop(vco_clk_rate);
 	cnt *= 2;
 	cnt /= 100;
 	cnt *= pin->kvco_measure_time;
@@ -494,7 +494,7 @@ static void pll_db_commit_common(void __iomem *pll_base,
 	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_CRCTRL, data);
 }
 
-static void pll_db_commit_thulium(void __iomem *pll_base,
+static void pll_db_commit_8996(void __iomem *pll_base,
 					struct dsi_pll_db *pdb)
 {
 	struct dsi_pll_input *pin = &pdb->in;
@@ -581,7 +581,7 @@ static void pll_db_commit_thulium(void __iomem *pll_base,
 	wmb();	/* make sure register committed */
 }
 
-int pll_vco_set_rate_thulium(struct clk *c, unsigned long rate)
+int pll_vco_set_rate_8996(struct clk *c, unsigned long rate)
 {
 	int rc;
 	struct dsi_pll_vco_clk *vco = to_vco_clk(c);
@@ -606,28 +606,28 @@ int pll_vco_set_rate_thulium(struct clk *c, unsigned long rate)
 	pll->vco_current_rate = rate;
 	pll->vco_ref_clk_rate = vco->ref_clk_rate;
 
-	mdss_dsi_pll_thulium_input_init(pdb);
+	mdss_dsi_pll_8996_input_init(pdb);
 
-	pll_thulium_dec_frac_calc(pdb, pll->vco_current_rate,
+	pll_8996_dec_frac_calc(pdb, pll->vco_current_rate,
 					pll->vco_ref_clk_rate);
 
-	pll_thulium_calc_vco_count(pdb, pll->vco_current_rate,
+	pll_8996_calc_vco_count(pdb, pll->vco_current_rate,
 					pll->vco_ref_clk_rate);
 
 	/* commit slave if split display is enabled */
 	slave = pll->slave;
 	if (slave)
-		pll_db_commit_thulium(slave->pll_base, pdb);
+		pll_db_commit_8996(slave->pll_base, pdb);
 
 	/* commit master itself */
-	pll_db_commit_thulium(pll->pll_base, pdb);
+	pll_db_commit_8996(pll->pll_base, pdb);
 
 	mdss_pll_resource_enable(pll, false);
 
 	return rc;
 }
 
-unsigned long pll_vco_get_rate_thulium(struct clk *c)
+unsigned long pll_vco_get_rate_8996(struct clk *c)
 {
 	u64 vco_rate, multiplier = (1 << 20);
 	s32 div_frac_start;
@@ -669,7 +669,7 @@ unsigned long pll_vco_get_rate_thulium(struct clk *c)
 	return (unsigned long)vco_rate;
 }
 
-long pll_vco_round_rate_thulium(struct clk *c, unsigned long rate)
+long pll_vco_round_rate_8996(struct clk *c, unsigned long rate)
 {
 	unsigned long rrate = rate;
 	u32 div;
@@ -690,7 +690,7 @@ long pll_vco_round_rate_thulium(struct clk *c, unsigned long rate)
 	return rrate;
 }
 
-enum handoff pll_vco_handoff_thulium(struct clk *c)
+enum handoff pll_vco_handoff_8996(struct clk *c)
 {
 	int rc;
 	enum handoff ret = HANDOFF_DISABLED_CLK;
@@ -706,10 +706,10 @@ enum handoff pll_vco_handoff_thulium(struct clk *c)
 		return ret;
 	}
 
-	if (pll_is_pll_locked_thulium(pll)) {
+	if (pll_is_pll_locked_8996(pll)) {
 		pll->handoff_resources = true;
 		pll->pll_on = true;
-		c->rate = pll_vco_get_rate_thulium(c);
+		c->rate = pll_vco_get_rate_8996(c);
 		ret = HANDOFF_ENABLED_CLK;
 	} else {
 		mdss_pll_resource_enable(pll, false);
@@ -718,7 +718,7 @@ enum handoff pll_vco_handoff_thulium(struct clk *c)
 	return ret;
 }
 
-int pll_vco_prepare_thulium(struct clk *c)
+int pll_vco_prepare_8996(struct clk *c)
 {
 	int rc = 0;
 	struct dsi_pll_vco_clk *vco = to_vco_clk(c);
@@ -744,7 +744,7 @@ error:
 	return rc;
 }
 
-void pll_vco_unprepare_thulium(struct clk *c)
+void pll_vco_unprepare_8996(struct clk *c)
 {
 	struct dsi_pll_vco_clk *vco = to_vco_clk(c);
 	struct mdss_pll_resources *pll = vco->priv;
diff --git a/drivers/clk/msm/mdss/mdss-dsi-pll-thulium.c b/drivers/clk/msm/mdss/mdss-dsi-pll-8996.c
index 66c3884f027b..56f06e7f10ff 100644
--- a/drivers/clk/msm/mdss/mdss-dsi-pll-thulium.c
+++ b/drivers/clk/msm/mdss/mdss-dsi-pll-8996.c
@@ -20,11 +20,11 @@
 #include <linux/clk/msm-clk.h>
 #include <linux/workqueue.h>
 #include <linux/clk/msm-clock-generic.h>
-#include <dt-bindings/clock/msm-clocks-thulium.h>
+#include <dt-bindings/clock/msm-clocks-8996.h>
 
 #include "mdss-pll.h"
 #include "mdss-dsi-pll.h"
-#include "mdss-dsi-pll-thulium.h"
+#include "mdss-dsi-pll-8996.h"
 
 #define VCO_DELAY_USEC		1
 
@@ -38,11 +38,11 @@ static struct clk_ops clk_ops_gen_mux_dsi;
 
 /* Op structures */
 static struct clk_ops clk_ops_dsi_vco = {
-	.set_rate = pll_vco_set_rate_thulium,
-	.round_rate = pll_vco_round_rate_thulium,
-	.handoff = pll_vco_handoff_thulium,
-	.prepare = pll_vco_prepare_thulium,
-	.unprepare = pll_vco_unprepare_thulium,
+	.set_rate = pll_vco_set_rate_8996,
+	.round_rate = pll_vco_round_rate_8996,
+	.handoff = pll_vco_handoff_8996,
+	.prepare = pll_vco_prepare_8996,
+	.unprepare = pll_vco_unprepare_8996,
 };
 
 static struct clk_div_ops post_n1_div_ops = {
@@ -56,13 +56,13 @@ static struct clk_div_ops n2_div_ops = {	/* hr_oclk3 */
 };
 
 static struct clk_mux_ops mdss_byte_mux_ops = {
-	.set_mux_sel = set_mdss_byte_mux_sel_thulium,
-	.get_mux_sel = get_mdss_byte_mux_sel_thulium,
+	.set_mux_sel = set_mdss_byte_mux_sel_8996,
+	.get_mux_sel = get_mdss_byte_mux_sel_8996,
 };
 
 static struct clk_mux_ops mdss_pixel_mux_ops = {
-	.set_mux_sel = set_mdss_pixel_mux_sel_thulium,
-	.get_mux_sel = get_mdss_pixel_mux_sel_thulium,
+	.set_mux_sel = set_mdss_pixel_mux_sel_8996,
+	.get_mux_sel = get_mdss_pixel_mux_sel_8996,
 };
 
 static struct dsi_pll_vco_clk dsi_vco_clk = {
@@ -70,9 +70,9 @@ static struct dsi_pll_vco_clk dsi_vco_clk = {
 	.min_rate = 1300000000,
 	.max_rate = 2600000000,
 	.pll_en_seq_cnt = 1,
-	.pll_enable_seqs[0] = dsi_pll_enable_seq_thulium,
+	.pll_enable_seqs[0] = dsi_pll_enable_seq_8996,
 	.c = {
-		.dbg_name = "dsi_vco_clk_thulium",
+		.dbg_name = "dsi_vco_clk_8996",
 		.ops = &clk_ops_dsi_vco,
 		CLK_INIT(dsi_vco_clk.c),
 	},
@@ -165,7 +165,7 @@ static struct mux_clk mdss_byte_clk_mux = {
 	}
 };
 
-static struct clk_lookup mdss_dsi_pllcc_thulium[] = {
+static struct clk_lookup mdss_dsi_pllcc_8996[] = {
 	CLK_LIST(mdss_byte_clk_mux),
 	CLK_LIST(byte_clk_src),
 	CLK_LIST(mdss_pixel_clk_mux),
@@ -175,7 +175,7 @@ static struct clk_lookup mdss_dsi_pllcc_thulium[] = {
 	CLK_LIST(dsi_vco_clk),
 };
 
-int dsi_pll_clock_register_thulium(struct platform_device *pdev,
+int dsi_pll_clock_register_8996(struct platform_device *pdev,
 				struct mdss_pll_resources *pll_res)
 {
 	int rc;
@@ -237,10 +237,10 @@ int dsi_pll_clock_register_thulium(struct platform_device *pdev,
 	clk_ops_gen_mux_dsi.round_rate = parent_round_rate;
 	clk_ops_gen_mux_dsi.set_rate = parent_set_rate;
 
-	if (pll_res->target_id == MDSS_PLL_TARGET_THULIUM) {
+	if (pll_res->target_id == MDSS_PLL_TARGET_8996) {
 		rc = of_msm_clock_register(pdev->dev.of_node,
-				mdss_dsi_pllcc_thulium,
-				ARRAY_SIZE(mdss_dsi_pllcc_thulium));
+				mdss_dsi_pllcc_8996,
+				ARRAY_SIZE(mdss_dsi_pllcc_8996));
 		if (rc) {
 			pr_err("Clock register failed\n");
 			rc = -EPROBE_DEFER;
diff --git a/drivers/clk/msm/mdss/mdss-dsi-pll-thulium.h b/drivers/clk/msm/mdss/mdss-dsi-pll-8996.h
index 381e16d87bdb..30986d8a0ecc 100644
--- a/drivers/clk/msm/mdss/mdss-dsi-pll-thulium.h
+++ b/drivers/clk/msm/mdss/mdss-dsi-pll-8996.h
@@ -10,8 +10,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef MDSS_DSI_PLL_THULIUM_H
-#define MDSS_DSI_PLL_THULIUM_H
+#ifndef MDSS_DSI_PLL_8996_H
+#define MDSS_DSI_PLL_8996_H
 
 #define DSIPHY_CMN_CLK_CFG0		0x0010
 #define DSIPHY_CMN_CLK_CFG1		0x0014
@@ -144,19 +144,19 @@ struct dsi_pll_db {
 	struct dsi_pll_output out;
 };
 
-int pll_vco_set_rate_thulium(struct clk *c, unsigned long rate);
-long pll_vco_round_rate_thulium(struct clk *c, unsigned long rate);
-enum handoff pll_vco_handoff_thulium(struct clk *c);
-int pll_vco_prepare_thulium(struct clk *c);
-void pll_vco_unprepare_thulium(struct clk *c);
-int set_mdss_byte_mux_sel_thulium(struct mux_clk *clk, int sel);
-int get_mdss_byte_mux_sel_thulium(struct mux_clk *clk);
-int set_mdss_pixel_mux_sel_thulium(struct mux_clk *clk, int sel);
-int get_mdss_pixel_mux_sel_thulium(struct mux_clk *clk);
+int pll_vco_set_rate_8996(struct clk *c, unsigned long rate);
+long pll_vco_round_rate_8996(struct clk *c, unsigned long rate);
+enum handoff pll_vco_handoff_8996(struct clk *c);
+int pll_vco_prepare_8996(struct clk *c);
+void pll_vco_unprepare_8996(struct clk *c);
+int set_mdss_byte_mux_sel_8996(struct mux_clk *clk, int sel);
+int get_mdss_byte_mux_sel_8996(struct mux_clk *clk);
+int set_mdss_pixel_mux_sel_8996(struct mux_clk *clk, int sel);
+int get_mdss_pixel_mux_sel_8996(struct mux_clk *clk);
 int post_n1_div_set_div(struct div_clk *clk, int div);
 int post_n1_div_get_div(struct div_clk *clk);
 int n2_div_set_div(struct div_clk *clk, int div);
 int n2_div_get_div(struct div_clk *clk);
-int dsi_pll_enable_seq_thulium(struct mdss_pll_resources *pll);
+int dsi_pll_enable_seq_8996(struct mdss_pll_resources *pll);
 
-#endif  /* MDSS_DSI_PLL_THULIUM_H */
+#endif  /* MDSS_DSI_PLL_8996_H */
diff --git a/drivers/clk/msm/mdss/mdss-dsi-pll.h b/drivers/clk/msm/mdss/mdss-dsi-pll.h
index 0856109c5554..5e6ac6af0595 100644
--- a/drivers/clk/msm/mdss/mdss-dsi-pll.h
+++ b/drivers/clk/msm/mdss/mdss-dsi-pll.h
@@ -56,7 +56,7 @@ int dsi_pll_clock_register_20nm(struct platform_device *pdev,
 				struct mdss_pll_resources *pll_res);
 int dsi_pll_clock_register_lpm(struct platform_device *pdev,
 				struct mdss_pll_resources *pll_res);
-int dsi_pll_clock_register_thulium(struct platform_device *pdev,
+int dsi_pll_clock_register_8996(struct platform_device *pdev,
 				struct mdss_pll_resources *pll_res);
 
 int set_byte_mux_sel(struct mux_clk *clk, int sel);
diff --git a/drivers/clk/msm/mdss/mdss-hdmi-pll-thulium.c b/drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c
index 8bcd795f9633..2a5620615f2e 100644
--- a/drivers/clk/msm/mdss/mdss-hdmi-pll-thulium.c
+++ b/drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c
@@ -18,7 +18,7 @@
 #include <linux/clk/msm-clk-provider.h>
 #include <linux/clk/msm-clk.h>
 #include <linux/clk/msm-clock-generic.h>
-#include <dt-bindings/clock/msm-clocks-thulium.h>
+#include <dt-bindings/clock/msm-clocks-8996.h>
 
 #include "mdss-pll.h"
 #include "mdss-hdmi-pll.h"
@@ -308,7 +308,7 @@ enum hdmi_pll_freqs {
 	HDMI_PCLK_MAX
 };
 
-struct hdmi_thulium_phy_pll_reg_cfg {
+struct hdmi_8996_phy_pll_reg_cfg {
 	u32 tx_l0_tx_band;
 	u32 tx_l1_tx_band;
 	u32 tx_l2_tx_band;
@@ -350,12 +350,12 @@ struct hdmi_thulium_phy_pll_reg_cfg {
 	u32 phy_mode;
 };
 
-static inline struct hdmi_pll_vco_clk *to_hdmi_thulium_vco_clk(struct clk *clk)
+static inline struct hdmi_pll_vco_clk *to_hdmi_8996_vco_clk(struct clk *clk)
 {
 	return container_of(clk, struct hdmi_pll_vco_clk, c);
 }
 
-static inline u64 hdmi_thulium_get_post_div_lt_2g(u64 bclk)
+static inline u64 hdmi_8996_get_post_div_lt_2g(u64 bclk)
 {
 	if (bclk >= HDMI_2400MHZ_BIT_CLK_HZ)
 		return 2;
@@ -375,7 +375,7 @@ static inline u64 hdmi_thulium_get_post_div_lt_2g(u64 bclk)
 	return HDMI_64B_ERR_VAL;
 }
 
-static inline u64 hdmi_thulium_get_coreclk_div_lt_2g(u64 bclk)
+static inline u64 hdmi_8996_get_coreclk_div_lt_2g(u64 bclk)
 {
 	if (bclk >= HDMI_1334MHZ_BIT_CLK_HZ)
 		return 1;
@@ -393,7 +393,7 @@ static inline u64 hdmi_thulium_get_coreclk_div_lt_2g(u64 bclk)
 	return HDMI_64B_ERR_VAL;
 }
 
-static inline u64 hdmi_thulium_get_coreclk_div_ratio(u64 clks_pll_divsel,
+static inline u64 hdmi_8996_get_coreclk_div_ratio(u64 clks_pll_divsel,
 						  u64 coreclk_div)
 {
 	if (clks_pll_divsel == 0)
@@ -404,7 +404,7 @@ static inline u64 hdmi_thulium_get_coreclk_div_ratio(u64 clks_pll_divsel,
 	return HDMI_64B_ERR_VAL;
 }
 
-static inline u64 hdmi_thulium_get_tx_band(u64 bclk)
+static inline u64 hdmi_8996_get_tx_band(u64 bclk)
 {
 	if (bclk >= 2400000000)
 		return 0;
@@ -418,7 +418,7 @@ static inline u64 hdmi_thulium_get_tx_band(u64 bclk)
 	return HDMI_64B_ERR_VAL;
 }
 
-static inline u64 hdmi_thulium_get_hsclk(u64 fdata)
+static inline u64 hdmi_8996_get_hsclk(u64 fdata)
 {
 	if (fdata >= 9600000000)
 		return 0;
@@ -432,7 +432,7 @@ static inline u64 hdmi_thulium_get_hsclk(u64 fdata)
 	return HDMI_64B_ERR_VAL;
 }
 
-static inline u64 hdmi_thulium_get_cpctrl(u64 frac_start, bool gen_ssc)
+static inline u64 hdmi_8996_get_cpctrl(u64 frac_start, bool gen_ssc)
 {
 	if ((frac_start != 0) ||
 	    (gen_ssc == true))
@@ -445,7 +445,7 @@ static inline u64 hdmi_thulium_get_cpctrl(u64 frac_start, bool gen_ssc)
 	return 0x23;
 }
 
-static inline u64 hdmi_thulium_get_rctrl(u64 frac_start, bool gen_ssc)
+static inline u64 hdmi_8996_get_rctrl(u64 frac_start, bool gen_ssc)
 {
 	if ((frac_start != 0) || (gen_ssc == true))
 		return 0x16;
@@ -453,7 +453,7 @@ static inline u64 hdmi_thulium_get_rctrl(u64 frac_start, bool gen_ssc)
 	return 0x10;
 }
 
-static inline u64 hdmi_thulium_get_cctrl(u64 frac_start, bool gen_ssc)
+static inline u64 hdmi_8996_get_cctrl(u64 frac_start, bool gen_ssc)
 {
 	if ((frac_start != 0) || (gen_ssc == true))
 		return 0x28;
@@ -461,7 +461,7 @@ static inline u64 hdmi_thulium_get_cctrl(u64 frac_start, bool gen_ssc)
 	return 0x1;
 }
 
-static inline u64 hdmi_thulium_get_integloop_gain(u64 frac_start, bool gen_ssc)
+static inline u64 hdmi_8996_get_integloop_gain(u64 frac_start, bool gen_ssc)
 {
 	if ((frac_start != 0) || (gen_ssc == true))
 		return 0x80;
@@ -469,7 +469,7 @@ static inline u64 hdmi_thulium_get_integloop_gain(u64 frac_start, bool gen_ssc)
 	return 0xC4;
 }
 
-static inline u64 hdmi_thulium_get_vco_tune(u64 fdata, u64 div)
+static inline u64 hdmi_8996_get_vco_tune(u64 fdata, u64 div)
 {
 	u64 vco_tune;
 
@@ -481,7 +481,7 @@ static inline u64 hdmi_thulium_get_vco_tune(u64 fdata, u64 div)
 	return vco_tune;
 }
 
-static inline u64 hdmi_thulium_get_pll_cmp(u64 pll_cmp_cnt, u64 core_clk)
+static inline u64 hdmi_8996_get_pll_cmp(u64 pll_cmp_cnt, u64 core_clk)
 {
 	u64 pll_cmp;
 	u64 rem;
@@ -494,8 +494,8 @@ static inline u64 hdmi_thulium_get_pll_cmp(u64 pll_cmp_cnt, u64 core_clk)
 	return pll_cmp;
 }
 
-static int hdmi_thulium_calculate(u32 pix_clk,
-			       struct hdmi_thulium_phy_pll_reg_cfg *cfg)
+static int hdmi_8996_calculate(u32 pix_clk,
+			       struct hdmi_8996_phy_pll_reg_cfg *cfg)
 {
 	int rc = -EINVAL;
 	u64 fdata, clk_divtx, tmds_clk;
@@ -528,16 +528,16 @@ static int hdmi_thulium_calculate(u32 pix_clk,
 	else
 		tmds_clk = bclk;
 
-	post_div_lt_2g = hdmi_thulium_get_post_div_lt_2g(bclk);
+	post_div_lt_2g = hdmi_8996_get_post_div_lt_2g(bclk);
 	if (post_div_lt_2g == HDMI_64B_ERR_VAL)
 		goto fail;
 
-	coreclk_div1_lt_2g = hdmi_thulium_get_coreclk_div_lt_2g(bclk);
+	coreclk_div1_lt_2g = hdmi_8996_get_coreclk_div_lt_2g(bclk);
 
-	core_clk_div_ratio = hdmi_thulium_get_coreclk_div_ratio(
+	core_clk_div_ratio = hdmi_8996_get_coreclk_div_ratio(
 				HDMI_CLKS_PLL_DIVSEL, HDMI_CORECLK_DIV);
 
-	tx_band = hdmi_thulium_get_tx_band(bclk);
+	tx_band = hdmi_8996_get_tx_band(bclk);
 	if (tx_band == HDMI_64B_ERR_VAL)
 		goto fail;
 
@@ -545,7 +545,7 @@ static int hdmi_thulium_calculate(u32 pix_clk,
 
 	if (bclk >= HDMI_2400MHZ_BIT_CLK_HZ) {
 		fdata = bclk;
-		hsclk = hdmi_thulium_get_hsclk(fdata);
+		hsclk = hdmi_8996_get_hsclk(fdata);
 		if (hsclk == HDMI_64B_ERR_VAL)
 			goto fail;
 
@@ -560,7 +560,7 @@ static int hdmi_thulium_calculate(u32 pix_clk,
 		vco_freq = bclk * (post_div_lt_2g * tx_band_div_ratio);
 		fdata = vco_freq;
 		do_div(fdata, post_div_lt_2g);
-		hsclk = hdmi_thulium_get_hsclk(fdata);
+		hsclk = hdmi_8996_get_hsclk(fdata);
 		if (hsclk == HDMI_64B_ERR_VAL)
 			goto fail;
 
@@ -581,15 +581,15 @@ static int hdmi_thulium_calculate(u32 pix_clk,
 	if (rem >= (pll_divisor >> 1))
 		frac_start++;
 
-	cpctrl = hdmi_thulium_get_cpctrl(frac_start, false);
-	rctrl = hdmi_thulium_get_rctrl(frac_start, false);
-	cctrl = hdmi_thulium_get_cctrl(frac_start, false);
-	integloop_gain = hdmi_thulium_get_integloop_gain(frac_start, false);
-	vco_tune = hdmi_thulium_get_vco_tune(fdata, post_div_gt_2g);
+	cpctrl = hdmi_8996_get_cpctrl(frac_start, false);
+	rctrl = hdmi_8996_get_rctrl(frac_start, false);
+	cctrl = hdmi_8996_get_cctrl(frac_start, false);
+	integloop_gain = hdmi_8996_get_integloop_gain(frac_start, false);
+	vco_tune = hdmi_8996_get_vco_tune(fdata, post_div_gt_2g);
 
 	core_clk = clk_divtx;
 	do_div(core_clk, core_clk_div_ratio);
-	pll_cmp = hdmi_thulium_get_pll_cmp(1024, core_clk);
+	pll_cmp = hdmi_8996_get_pll_cmp(1024, core_clk);
 
 	/* Debug dump */
 	DEV_DBG("%s: VCO freq: %llu\n", __func__, vco_freq);
@@ -668,7 +668,7 @@ static int hdmi_thulium_calculate(u32 pix_clk,
 	}
 
 	cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0;
-	DEV_DBG("HDMI thulium PLL: PLL Settings\n");
+	DEV_DBG("HDMI 8996 PLL: PLL Settings\n");
 	DEV_DBG("PLL PARAM: tx_l0_tx_band = 0x%x\n", cfg->tx_l0_tx_band);
 	DEV_DBG("PLL PARAM: tx_l1_tx_band = 0x%x\n", cfg->tx_l1_tx_band);
 	DEV_DBG("PLL PARAM: tx_l2_tx_band = 0x%x\n", cfg->tx_l2_tx_band);
@@ -731,14 +731,14 @@ fail:
 	return rc;
 }
 
-static int hdmi_thulium_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk)
+static int hdmi_8996_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk)
 {
 	int rc = 0;
-	struct hdmi_pll_vco_clk *vco = to_hdmi_thulium_vco_clk(c);
+	struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c);
 	struct mdss_pll_resources *io = vco->priv;
-	struct hdmi_thulium_phy_pll_reg_cfg cfg = {0};
+	struct hdmi_8996_phy_pll_reg_cfg cfg = {0};
 
-	rc = hdmi_thulium_calculate(tmds_clk, &cfg);
+	rc = hdmi_8996_calculate(tmds_clk, &cfg);
 	if (rc) {
 		DEV_ERR("%s: PLL calculation failed\n", __func__);
 		return rc;
@@ -966,7 +966,7 @@ static int hdmi_thulium_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk)
 	return 0;
 }
 
-static int hdmi_thulium_phy_ready_status(struct mdss_pll_resources *io)
+static int hdmi_8996_phy_ready_status(struct mdss_pll_resources *io)
 {
 	u32 status;
 	int phy_ready = 0;
@@ -998,7 +998,7 @@ static int hdmi_thulium_phy_ready_status(struct mdss_pll_resources *io)
 	return phy_ready;
 }
 
-static int hdmi_thulium_pll_lock_status(struct mdss_pll_resources *io)
+static int hdmi_8996_pll_lock_status(struct mdss_pll_resources *io)
 {
 	u32 status;
 	int pll_locked = 0;
@@ -1029,10 +1029,10 @@ static int hdmi_thulium_pll_lock_status(struct mdss_pll_resources *io)
 	return pll_locked;
 }
 
-static int hdmi_thulium_perform_sw_calibration(struct clk *c)
+static int hdmi_8996_perform_sw_calibration(struct clk *c)
 {
 	int rc = 0;
-	struct hdmi_pll_vco_clk *vco = to_hdmi_thulium_vco_clk(c);
+	struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c);
 	struct mdss_pll_resources *io = vco->priv;
 
 	u32 max_code = 0x190;
@@ -1169,10 +1169,10 @@ static int hdmi_thulium_perform_sw_calibration(struct clk *c)
 	return rc;
 }
 
-static int hdmi_thulium_vco_enable(struct clk *c)
+static int hdmi_8996_vco_enable(struct clk *c)
 {
 	int rc = 0;
-	struct hdmi_pll_vco_clk *vco = to_hdmi_thulium_vco_clk(c);
+	struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c);
 	struct mdss_pll_resources *io = vco->priv;
 
 	MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x1);
@@ -1181,13 +1181,13 @@ static int hdmi_thulium_vco_enable(struct clk *c)
 	MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x19);
 	udelay(100);
 
-	rc = hdmi_thulium_perform_sw_calibration(c);
+	rc = hdmi_8996_perform_sw_calibration(c);
 	if (rc) {
 		DEV_ERR("%s: software calibration failed\n", __func__);
 		return rc;
 	}
 
-	rc = hdmi_thulium_pll_lock_status(io);
+	rc = hdmi_8996_pll_lock_status(io);
 	if (!rc) {
 		DEV_ERR("%s: PLL not locked\n", __func__);
 		return rc;
@@ -1213,7 +1213,7 @@ static int hdmi_thulium_vco_enable(struct clk *c)
 	MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_STEP_SIZE2, 0x0);
 	MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_EN_CENTER, 0x2);
 
-	rc = hdmi_thulium_phy_ready_status(io);
+	rc = hdmi_8996_phy_ready_status(io);
 	if (!rc) {
 		DEV_ERR("%s: PHY not READY\n", __func__);
 		return rc;
@@ -1228,9 +1228,9 @@ static int hdmi_thulium_vco_enable(struct clk *c)
 	return 0;
 }
 
-static int hdmi_thulium_vco_set_rate(struct clk *c, unsigned long rate)
+static int hdmi_8996_vco_set_rate(struct clk *c, unsigned long rate)
 {
-	struct hdmi_pll_vco_clk *vco = to_hdmi_thulium_vco_clk(c);
+	struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c);
 	struct mdss_pll_resources *io = vco->priv;
 	void __iomem		*pll_base;
 	void __iomem		*phy_base;
@@ -1251,14 +1251,14 @@ static int hdmi_thulium_vco_set_rate(struct clk *c, unsigned long rate)
 
 	DEV_DBG("HDMI PIXEL CLK rate=%ld\n", rate);
 
-	rc = hdmi_thulium_phy_pll_set_clk_rate(c, rate);
+	rc = hdmi_8996_phy_pll_set_clk_rate(c, rate);
 	if (rc)
 		DEV_ERR("%s: Failed to set clk rate\n", __func__);
 
 	mdss_pll_resource_enable(io, false);
 
 	if (set_power_dwn)
-		hdmi_thulium_vco_enable(c);
+		hdmi_8996_vco_enable(c);
 
 	vco->rate = rate;
 	vco->rate_set = true;
@@ -1266,14 +1266,14 @@ static int hdmi_thulium_vco_set_rate(struct clk *c, unsigned long rate)
 	return 0;
 }
 
-static unsigned long hdmi_thulium_vco_get_rate(struct clk *c)
+static unsigned long hdmi_8996_vco_get_rate(struct clk *c)
 {
 	unsigned long freq = 0;
 
 	return freq;
 }
 
-static long hdmi_thulium_vco_round_rate(struct clk *c, unsigned long rate)
+static long hdmi_8996_vco_round_rate(struct clk *c, unsigned long rate)
 {
 	unsigned long rrate = rate;
 
@@ -1282,16 +1282,16 @@ static long hdmi_thulium_vco_round_rate(struct clk *c, unsigned long rate)
 	return rrate;
 }
 
-static int hdmi_thulium_vco_prepare(struct clk *c)
+static int hdmi_8996_vco_prepare(struct clk *c)
 {
-	struct hdmi_pll_vco_clk *vco = to_hdmi_thulium_vco_clk(c);
+	struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c);
 	struct mdss_pll_resources *io = vco->priv;
 	int ret = 0;
 
 	DEV_DBG("rate=%ld\n", vco->rate);
 
 	if (!vco->rate_set && vco->rate)
-		ret = hdmi_thulium_vco_set_rate(c, vco->rate);
+		ret = hdmi_8996_vco_set_rate(c, vco->rate);
 
 	if (!ret) {
 		ret = mdss_pll_resource_enable(io, true);
@@ -1302,9 +1302,9 @@ static int hdmi_thulium_vco_prepare(struct clk *c)
 	return ret;
 }
 
-static void hdmi_thulium_vco_unprepare(struct clk *c)
+static void hdmi_8996_vco_unprepare(struct clk *c)
 {
-	struct hdmi_pll_vco_clk *vco = to_hdmi_thulium_vco_clk(c);
+	struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c);
 	struct mdss_pll_resources *io = vco->priv;
 
 	vco->rate_set = false;
@@ -1325,10 +1325,10 @@ static void hdmi_thulium_vco_unprepare(struct clk *c)
 	io->pll_on = false;
 }
 
-static enum handoff hdmi_thulium_vco_handoff(struct clk *c)
+static enum handoff hdmi_8996_vco_handoff(struct clk *c)
 {
 	enum handoff ret = HANDOFF_DISABLED_CLK;
-	struct hdmi_pll_vco_clk *vco = to_hdmi_thulium_vco_clk(c);
+	struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c);
 	struct mdss_pll_resources *io = vco->priv;
 
 	if (is_gdsc_disabled(io))
@@ -1341,10 +1341,10 @@ static enum handoff hdmi_thulium_vco_handoff(struct clk *c)
 
 	io->handoff_resources = true;
 
-	if (hdmi_thulium_pll_lock_status(io)) {
-		if (hdmi_thulium_phy_ready_status(io)) {
+	if (hdmi_8996_pll_lock_status(io)) {
+		if (hdmi_8996_phy_ready_status(io)) {
 			io->pll_on = true;
-			c->rate = hdmi_thulium_vco_get_rate(c);
+			c->rate = hdmi_8996_vco_get_rate(c);
 			ret = HANDOFF_ENABLED_CLK;
 		} else {
 			io->handoff_resources = false;
@@ -1361,20 +1361,20 @@ static enum handoff hdmi_thulium_vco_handoff(struct clk *c)
 	return ret;
 }
 
-static struct clk_ops hdmi_thulium_vco_clk_ops = {
-	.enable = hdmi_thulium_vco_enable,
-	.set_rate = hdmi_thulium_vco_set_rate,
-	.get_rate = hdmi_thulium_vco_get_rate,
-	.round_rate = hdmi_thulium_vco_round_rate,
-	.prepare = hdmi_thulium_vco_prepare,
-	.unprepare = hdmi_thulium_vco_unprepare,
-	.handoff = hdmi_thulium_vco_handoff,
+static struct clk_ops hdmi_8996_vco_clk_ops = {
+	.enable = hdmi_8996_vco_enable,
+	.set_rate = hdmi_8996_vco_set_rate,
+	.get_rate = hdmi_8996_vco_get_rate,
+	.round_rate = hdmi_8996_vco_round_rate,
+	.prepare = hdmi_8996_vco_prepare,
+	.unprepare = hdmi_8996_vco_unprepare,
+	.handoff = hdmi_8996_vco_handoff,
 };
 
 static struct hdmi_pll_vco_clk hdmi_vco_clk = {
 	.c = {
-		.dbg_name = "hdmi_thulium_vco_clk",
-		.ops = &hdmi_thulium_vco_clk_ops,
+		.dbg_name = "hdmi_8996_vco_clk",
+		.ops = &hdmi_8996_vco_clk_ops,
 		CLK_INIT(hdmi_vco_clk.c),
 	},
 };
@@ -1383,7 +1383,7 @@ static struct clk_lookup hdmipllcc_8996[] = {
 	CLK_LIST(hdmi_vco_clk),
 };
 
-int hdmi_thulium_pll_clock_register(struct platform_device *pdev,
+int hdmi_8996_pll_clock_register(struct platform_device *pdev,
 				 struct mdss_pll_resources *pll_res)
 {
 	int rc = -ENOTSUPP;
diff --git a/drivers/clk/msm/mdss/mdss-hdmi-pll.h b/drivers/clk/msm/mdss/mdss-hdmi-pll.h
index 7ce7747aefa5..35e6e1fbe16d 100644
--- a/drivers/clk/msm/mdss/mdss-hdmi-pll.h
+++ b/drivers/clk/msm/mdss/mdss-hdmi-pll.h
@@ -39,6 +39,6 @@ int hdmi_pll_clock_register(struct platform_device *pdev,
 int hdmi_20nm_pll_clock_register(struct platform_device *pdev,
 				struct mdss_pll_resources *pll_res);
 
-int hdmi_thulium_pll_clock_register(struct platform_device *pdev,
+int hdmi_8996_pll_clock_register(struct platform_device *pdev,
 				 struct mdss_pll_resources *pll_res);
 #endif
diff --git a/drivers/clk/msm/mdss/mdss-pll.c b/drivers/clk/msm/mdss/mdss-pll.c
index 861f94a92550..eb26fc43e109 100644
--- a/drivers/clk/msm/mdss/mdss-pll.c
+++ b/drivers/clk/msm/mdss/mdss-pll.c
@@ -145,9 +145,9 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
 	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8992")) {
 		pll_res->pll_interface_type = MDSS_DSI_PLL_20NM;
 		pll_res->target_id = MDSS_PLL_TARGET_8992;
-	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_thulium")) {
-		pll_res->pll_interface_type = MDSS_DSI_PLL_THULIUM;
-		pll_res->target_id = MDSS_PLL_TARGET_THULIUM;
+	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8996")) {
+		pll_res->pll_interface_type = MDSS_DSI_PLL_8996;
+		pll_res->target_id = MDSS_PLL_TARGET_8996;
 	} else if (!strcmp(compatible_stream, "qcom,mdss_edp_pll")) {
 		pll_res->pll_interface_type = MDSS_EDP_PLL;
 	} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll")) {
@@ -156,8 +156,8 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
 		pll_res->pll_interface_type = MDSS_HDMI_PLL_20NM;
 	} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8992")) {
 		pll_res->pll_interface_type = MDSS_HDMI_PLL_20NM;
-	} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_thulium")) {
-		pll_res->pll_interface_type = MDSS_HDMI_PLL_THULIUM;
+	} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996")) {
+		pll_res->pll_interface_type = MDSS_HDMI_PLL_8996;
 	} else {
 		goto err;
 	}
@@ -190,8 +190,8 @@ static int mdss_pll_clock_register(struct platform_device *pdev,
 	case MDSS_DSI_PLL_20NM:
 		rc = dsi_pll_clock_register_20nm(pdev, pll_res);
 		break;
-	case MDSS_DSI_PLL_THULIUM:
-		rc = dsi_pll_clock_register_thulium(pdev, pll_res);
+	case MDSS_DSI_PLL_8996:
+		rc = dsi_pll_clock_register_8996(pdev, pll_res);
 		break;
 	case MDSS_EDP_PLL:
 		rc = edp_pll_clock_register(pdev, pll_res);
@@ -201,8 +201,8 @@ static int mdss_pll_clock_register(struct platform_device *pdev,
 	case MDSS_HDMI_PLL_20NM:
 		rc = hdmi_20nm_pll_clock_register(pdev, pll_res);
 		break;
-	case MDSS_HDMI_PLL_THULIUM:
-		rc = hdmi_thulium_pll_clock_register(pdev, pll_res);
+	case MDSS_HDMI_PLL_8996:
+		rc = hdmi_8996_pll_clock_register(pdev, pll_res);
 		break;
 	case MDSS_UNKNOWN_PLL:
 	default:
@@ -405,11 +405,11 @@ static int mdss_pll_remove(struct platform_device *pdev)
 static const struct of_device_id mdss_pll_dt_match[] = {
 	{.compatible = "qcom,mdss_dsi_pll_8974"},
 	{.compatible = "qcom,mdss_dsi_pll_8994"},
-	{.compatible = "qcom,mdss_dsi_pll_thulium"},
+	{.compatible = "qcom,mdss_dsi_pll_8996"},
 	{.compatible = "qcom,mdss_hdmi_pll_8994"},
 	{.compatible = "qcom,mdss_dsi_pll_8992"},
 	{.compatible = "qcom,mdss_hdmi_pll_8992"},
-	{.compatible = "qcom,mdss_hdmi_pll_thulium"},
+	{.compatible = "qcom,mdss_hdmi_pll_8996"},
 	{.compatible = "qcom,mdss_dsi_pll_8916"},
 	{.compatible = "qcom,mdss_dsi_pll_8939"},
 	{.compatible = "qcom,mdss_dsi_pll_8909"},
diff --git a/drivers/clk/msm/mdss/mdss-pll.h b/drivers/clk/msm/mdss/mdss-pll.h
index de78d2f43e8b..f959097803f3 100644
--- a/drivers/clk/msm/mdss/mdss-pll.h
+++ b/drivers/clk/msm/mdss/mdss-pll.h
@@ -31,11 +31,11 @@ enum {
 	MDSS_DSI_PLL_LPM,
 	MDSS_DSI_PLL_HPM,
 	MDSS_DSI_PLL_20NM,
-	MDSS_DSI_PLL_THULIUM,
+	MDSS_DSI_PLL_8996,
 	MDSS_EDP_PLL,
 	MDSS_HDMI_PLL,
 	MDSS_HDMI_PLL_20NM,
-	MDSS_HDMI_PLL_THULIUM,
+	MDSS_HDMI_PLL_8996,
 	MDSS_UNKNOWN_PLL,
 };
 
@@ -43,7 +43,7 @@ enum {
 	MDSS_PLL_TARGET_8974,
 	MDSS_PLL_TARGET_8994,
 	MDSS_PLL_TARGET_8992,
-	MDSS_PLL_TARGET_THULIUM,
+	MDSS_PLL_TARGET_8996,
 	MDSS_PLL_TARGET_8916,
 	MDSS_PLL_TARGET_8939,
 	MDSS_PLL_TARGET_8909,