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authorArchana Sathyakumar <asathyak@codeaurora.org>2017-07-26 07:37:51 -0600
committerGeorg Veichtlbauer <georg@vware.at>2023-07-16 12:47:42 +0200
commit1daa7ea39076e334a07ffb90f55ae33398b3477f (patch)
tree6666828766ea9d19bb1f4d3f2628ccd65eefb063
parent07f7c9961c7cd0090dd1771f61245746af7fe1ea (diff)
pinctrl: qcom: Update irq handle for GPIO pins
Default handle_irq for tlmm irq chip is handle_edge_irq. For direct connect GPIOs, the handle_irq is not changed unlike non-direct connect GPIOs. This causes an interrupt storm for level trigger types as handle_edge_irq does not mask the interrupt within the function. Change this to handle_fasteoi_irq such that both level and edge interrupts are handled correctly. Change-Id: I79f0d4d92145f85a8043875301400ecf36b46c7b Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 22496ad167a0..d4a1f5378ac5 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -905,7 +905,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
ret = gpiochip_irqchip_add(chip,
&msm_gpio_irq_chip,
0,
- handle_edge_irq,
+ handle_fasteoi_irq,
IRQ_TYPE_NONE);
if (ret) {
dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");