diff options
| author | Tony Truong <truong@codeaurora.org> | 2015-01-28 18:20:25 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 11:09:04 -0700 |
| commit | 1d3fd3942ece7292d8aac3661831bab30b8f71f0 (patch) | |
| tree | 47b62a4c4a749de54ba6ddab66dd099d1a8fd7a8 | |
| parent | b0ac5910b0590417758ad326389ce183b0c5207a (diff) | |
msm: pcie: add support to enable clk power management for EP
Add support to enable the clock power management for the
endpoint.
Change-Id: I02bebfeb5d32eb8e1f75ee5feb4c4fff956ece66
Signed-off-by: Tony Truong <truong@codeaurora.org>
| -rw-r--r-- | Documentation/devicetree/bindings/pci/msm_pcie.txt | 2 | ||||
| -rw-r--r-- | drivers/pci/host/pci-msm.c | 26 |
2 files changed, 28 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/msm_pcie.txt b/Documentation/devicetree/bindings/pci/msm_pcie.txt index 3b0400743651..10cf6c54649b 100644 --- a/Documentation/devicetree/bindings/pci/msm_pcie.txt +++ b/Documentation/devicetree/bindings/pci/msm_pcie.txt @@ -57,6 +57,8 @@ Optional Properties: - qcom,aux-clk-sync: The AUX clock is synchronous to the Core clock to support L1ss. - qcom,common-clk-en: Enables the common clock configuration for the endpoint. + - qcom,clk-power-manage-en: Enables the clock power management for the + endpoint. - qcom,n-fts: The number of fast training sequences sent when the link state is changed from L0s to L0. - qcom,ep-wakeirq: The endpoint will issue wake signal when it is up, and the diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c index 7f3ab113bfbd..7e2d8c1db627 100644 --- a/drivers/pci/host/pci-msm.c +++ b/drivers/pci/host/pci-msm.c @@ -494,6 +494,7 @@ struct msm_pcie_dev_t { bool l1_supported; bool l1ss_supported; bool common_clk_en; + bool clk_power_manage_en; bool aux_clk_sync; uint32_t n_fts; bool ext_ref_clk; @@ -1104,6 +1105,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) dev->l1ss_supported ? "" : "not"); pr_alert("common_clk_en is %d\n", dev->common_clk_en); + pr_alert("clk_power_manage_en is %d\n", + dev->clk_power_manage_en); pr_alert("aux_clk_sync is %d\n", dev->aux_clk_sync); pr_alert("ext_ref_clk is %d\n", @@ -2669,6 +2672,23 @@ static void msm_pcie_config_link_state(struct msm_pcie_dev_t *dev) readl_relaxed(dev->conf + ep_link_ctrlstts_offset)); } + if (dev->clk_power_manage_en) { + val = readl_relaxed(dev->conf + ep_link_cap_offset); + if (val & BIT(18)) { + msm_pcie_write_mask(dev->conf + ep_link_ctrlstts_offset, + 0, BIT(8)); + + if (dev->shadow_en) + dev->ep_shadow[0][ep_link_ctrlstts_offset / 4] = + readl_relaxed(dev->conf + + ep_link_ctrlstts_offset); + + PCIE_DBG2(dev, "EP's CAP_LINKCTRLSTATUS:0x%x\n", + readl_relaxed(dev->conf + + ep_link_ctrlstts_offset)); + } + } + if (dev->l0s_supported) { msm_pcie_write_mask(dev->dm_core + PCIE20_CAP_LINKCTRLSTATUS, 0, BIT(0)); @@ -4372,6 +4392,12 @@ static int msm_pcie_probe(struct platform_device *pdev) "qcom,common-clk-en"); PCIE_DBG(&msm_pcie_dev[rc_idx], "Common clock is %s enabled.\n", msm_pcie_dev[rc_idx].common_clk_en ? "" : "not"); + msm_pcie_dev[rc_idx].clk_power_manage_en = + of_property_read_bool((&pdev->dev)->of_node, + "qcom,clk-power-manage-en"); + PCIE_DBG(&msm_pcie_dev[rc_idx], + "Clock power management is %s enabled.\n", + msm_pcie_dev[rc_idx].clk_power_manage_en ? "" : "not"); msm_pcie_dev[rc_idx].aux_clk_sync = of_property_read_bool((&pdev->dev)->of_node, "qcom,aux-clk-sync"); |