diff options
| author | Mitchel Humpherys <mitchelh@codeaurora.org> | 2014-08-12 11:03:23 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 11:11:10 -0700 |
| commit | 1ac0dcf474288ef34f260e2372fd4dbc8a25827f (patch) | |
| tree | 7d58d1c8d78209e36ffb0ba92a24efbdb13333a2 | |
| parent | 0fd67fedf7c5e708988df216bd3a3af60670ec27 (diff) | |
iommu/arm-smmu: work around transaction hardware bug
Work around a hardware bug where some SMMUs cache invalid PTEs and mess
up the transaction logic. PTEs must be zero'd out completely rather than
just setting the last two bits to zero to work around this bug.
Change-Id: I98ac18142eda6f7817c78ab27a4850cdecf24913
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
| -rw-r--r-- | drivers/iommu/arm-smmu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 9222dd2fb4c8..04ef1920cf7c 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1585,6 +1585,8 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_domain *smmu_domain, } do { + if (!(pteval & ARM_SMMU_PTE_PAGE)) + pteval = 0; *pte = pfn_pte(pfn, __pgprot(pteval)); } while (pte++, pfn++, addr += PAGE_SIZE, --i); } while (addr != end); |