diff options
| author | Ingrid Gallardo <ingridg@codeaurora.org> | 2016-06-08 10:51:09 -0700 |
|---|---|---|
| committer | Harsh Sahu <hsahu@codeaurora.org> | 2016-12-12 14:06:52 -0800 |
| commit | 1a71e5ed0c887d12226d5f4557b4ad8c83b6f3a0 (patch) | |
| tree | ee842d22406fcad2035fb1a4949e3b349005d60e | |
| parent | 306732cd443da8774c229e48d19f0ad61d8da0ce (diff) | |
msm: mdss: enable pll regulator during phy on sequence
Make sure pll regulator is enabled as part of the phy
on sequence. This fixes some corruption observed
when pll is disabled as part of the phy shut-down
sequence.
Change-Id: I1ace97dbf5b8e5ed8fceedddf714758a5f708cfb
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
| -rw-r--r-- | drivers/video/fbdev/msm/msm_mdss_io_8974.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/video/fbdev/msm/msm_mdss_io_8974.c b/drivers/video/fbdev/msm/msm_mdss_io_8974.c index 3dc2e952b5dd..e6151b4c75a1 100644 --- a/drivers/video/fbdev/msm/msm_mdss_io_8974.c +++ b/drivers/video/fbdev/msm/msm_mdss_io_8974.c @@ -947,8 +947,11 @@ static void mdss_dsi_8996_phy_power_off( { int ln; void __iomem *base; + u32 data; - MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, 0x7f); + /* Turn off PLL power */ + data = MIPI_INP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0); + MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, data & ~BIT(7)); /* 4 lanes + clk lane configuration */ for (ln = 0; ln < 5; ln++) { @@ -1004,6 +1007,7 @@ static void mdss_dsi_8996_phy_power_on( void __iomem *base; struct mdss_dsi_phy_ctrl *pd; char *ip; + u32 data; pd = &(((ctrl->panel_data).panel_info.mipi).dsi_phy_db); @@ -1023,6 +1027,10 @@ static void mdss_dsi_8996_phy_power_on( } mdss_dsi_8996_phy_regulator_enable(ctrl); + + /* Turn on PLL power */ + data = MIPI_INP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0); + MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, data | BIT(7)); } static void mdss_dsi_phy_power_on( @@ -1126,6 +1134,7 @@ static void mdss_dsi_8996_phy_config(struct mdss_dsi_ctrl_pdata *ctrl) mdss_dsi_8996_pll_source_standalone(ctrl); } + MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, 0x7f); wmb(); /* make sure registers committed */ } |