msm: mdss: Provide generic io access mechanism to all mdss modules

Generalize and move HDMI Tx controller's io access mechanism to
mdss_io_util so that other mdss modules can reuse it.

Change-Id: I097af956706dcbf2e9fa1f6b5983a550a462fed1
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>

8 files changed, 239 insertions, 382 deletions

diff --git a/drivers/video/fbdev/msm/mdss_hdmi_edid.c b/drivers/video/fbdev/msm/mdss_hdmi_edid.c
index c2e07fd874c7..55f428ce417f 100644
--- a/drivers/video/fbdev/msm/mdss_hdmi_edid.c
+++ b/drivers/video/fbdev/msm/mdss_hdmi_edid.c
@@ -1392,7 +1392,7 @@ void *hdmi_edid_init(struct hdmi_edid_init_data *init_data)
 {
 	struct hdmi_edid_ctrl *edid_ctrl = NULL;
 
-	if (!init_data || !init_data->base ||
+	if (!init_data || !init_data->io ||
 		!init_data->mutex || !init_data->sysfs_kobj ||
 		!init_data->ddc_ctrl) {
 		DEV_ERR("%s: invalid input\n", __func__);
diff --git a/drivers/video/fbdev/msm/mdss_hdmi_edid.h b/drivers/video/fbdev/msm/mdss_hdmi_edid.h
index 9561b4246f73..b96da82308b7 100644
--- a/drivers/video/fbdev/msm/mdss_hdmi_edid.h
+++ b/drivers/video/fbdev/msm/mdss_hdmi_edid.h
@@ -16,7 +16,7 @@
 #include "mdss_hdmi_util.h"
 
 struct hdmi_edid_init_data {
-	void __iomem *base;
+	struct dss_io_data *io;
 	struct mutex *mutex;
 	struct kobject *sysfs_kobj;
 
diff --git a/drivers/video/fbdev/msm/mdss_hdmi_tx.c b/drivers/video/fbdev/msm/mdss_hdmi_tx.c
index ad646c0ca812..13264eb65cf2 100644
--- a/drivers/video/fbdev/msm/mdss_hdmi_tx.c
+++ b/drivers/video/fbdev/msm/mdss_hdmi_tx.c
@@ -101,9 +101,9 @@ static const char *hdmi_tx_clk_name(u32 clk)
 	}
 } /* hdmi_tx_clk_name */
 
-static const char *hdmi_tx_io_name(u32 io)
+static const char *hdmi_tx_io_name(u32 type)
 {
-	switch (io) {
+	switch (type) {
 	case HDMI_TX_CORE_IO:	return "core_physical";
 	case HDMI_TX_PHY_IO:	return "phy_physical";
 	case HDMI_TX_QFPROM_IO:	return "qfprom_physical";
@@ -385,7 +385,7 @@ static int hdmi_tx_init_features(struct hdmi_tx_ctrl *hdmi_ctrl)
 		return -EINVAL;
 	}
 
-	edid_init_data.base = hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO].base;
+	edid_init_data.io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
 	edid_init_data.mutex = &hdmi_ctrl->mutex;
 	edid_init_data.sysfs_kobj = hdmi_ctrl->kobj;
 	edid_init_data.ddc_ctrl = &hdmi_ctrl->ddc_ctrl;
@@ -405,14 +405,14 @@ static int hdmi_tx_init_features(struct hdmi_tx_ctrl *hdmi_ctrl)
 
 static inline u32 hdmi_tx_is_controller_on(struct hdmi_tx_ctrl *hdmi_ctrl)
 {
-	return HDMI_REG_R_ND(hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO].base,
-		HDMI_CTRL) & BIT(0);
+	struct dss_io_data *io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+	return DSS_REG_R_ND(io, HDMI_CTRL) & BIT(0);
 } /* hdmi_tx_is_controller_on */
 
 static inline u32 hdmi_tx_is_dvi_mode(struct hdmi_tx_ctrl *hdmi_ctrl)
 {
-	return !(HDMI_REG_R_ND(hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO].base,
-		HDMI_CTRL) & BIT(1));
+	struct dss_io_data *io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+	return !(DSS_REG_R_ND(io, HDMI_CTRL) & BIT(1));
 } /* hdmi_tx_is_dvi_mode */
 
 static int hdmi_tx_init_panel_info(uint32_t resolution,
@@ -551,9 +551,14 @@ static void hdmi_tx_hpd_state_work(struct work_struct *work)
 	}
 
 	io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+	if (!io->base) {
+		DEV_ERR("%s: Core io is not initialized\n", __func__);
+		return;
+	}
+
 	DEV_DBG("%s: Got HPD interrupt\n", __func__);
 
-	hpd_state = (HDMI_REG_R(io->base, HDMI_HPD_INT_STATUS) & BIT(1)) >> 1;
+	hpd_state = (DSS_REG_R(io, HDMI_HPD_INT_STATUS) & BIT(1)) >> 1;
 	mutex_lock(&hdmi_ctrl->mutex);
 	if ((hdmi_ctrl->hpd_prev_state != hdmi_ctrl->hpd_state) ||
 		(hdmi_ctrl->hpd_state != hpd_state)) {
@@ -605,22 +610,23 @@ static void hdmi_tx_hpd_state_work(struct work_struct *work)
 	}
 
 	/* Set IRQ for HPD */
-	HDMI_REG_W(io->base, HDMI_HPD_INT_CTRL, 4 | (hpd_state ? 0 : 2));
+	DSS_REG_W(io, HDMI_HPD_INT_CTRL, 4 | (hpd_state ? 0 : 2));
 } /* hdmi_tx_hpd_state_work */
 
-static int hdmi_tx_check_capability(void __iomem *base)
+static int hdmi_tx_check_capability(struct dss_io_data *io)
 {
 	u32 hdmi_disabled, hdcp_disabled;
 
-	if (!base) {
+	if (!io) {
 		DEV_ERR("%s: invalid input\n", __func__);
 		return -EINVAL;
 	}
 
-	/* QFPROM_RAW_FEAT_CONFIG_ROW0_LSB */
-	hdcp_disabled = HDMI_REG_R_ND(base, 0x000000F8) & BIT(31);
-	/* QFPROM_RAW_FEAT_CONFIG_ROW0_MSB */
-	hdmi_disabled = HDMI_REG_R_ND(base, 0x000000FC) & BIT(0);
+	hdcp_disabled = DSS_REG_R_ND(io,
+		QFPROM_RAW_FEAT_CONFIG_ROW0_LSB) & BIT(31);
+
+	hdmi_disabled = DSS_REG_R_ND(io,
+		QFPROM_RAW_FEAT_CONFIG_ROW0_MSB) & BIT(0);
 
 	DEV_DBG("%s: Features <HDMI:%s, HDCP:%s>\n", __func__,
 		hdmi_disabled ? "OFF" : "ON", hdcp_disabled ? "OFF" : "ON");
@@ -772,35 +778,35 @@ static void hdmi_tx_video_setup(struct hdmi_tx_ctrl *hdmi_ctrl,
 		timing->back_porch_h + timing->pulse_width_h - 1;
 	total_v = timing->active_v + timing->front_porch_v +
 		timing->back_porch_v + timing->pulse_width_v - 1;
-	HDMI_REG_W(io->base, HDMI_TOTAL,
+	DSS_REG_W(io, HDMI_TOTAL,
 		((total_v << 16) & 0x0FFF0000) |
 		((total_h << 0) & 0x00000FFF));
 
 	start_h = timing->back_porch_h + timing->pulse_width_h;
 	end_h   = (total_h + 1) - timing->front_porch_h;
-	HDMI_REG_W(io->base, HDMI_ACTIVE_H,
+	DSS_REG_W(io, HDMI_ACTIVE_H,
 		((end_h << 16) & 0x0FFF0000) |
 		((start_h << 0) & 0x00000FFF));
 
 	start_v = timing->back_porch_v + timing->pulse_width_v - 1;
 	end_v   = total_v - timing->front_porch_v;
-	HDMI_REG_W(io->base, HDMI_ACTIVE_V,
+	DSS_REG_W(io, HDMI_ACTIVE_V,
 		((end_v << 16) & 0x0FFF0000) |
 		((start_v << 0) & 0x00000FFF));
 
 	if (timing->interlaced) {
-		HDMI_REG_W(io->base, HDMI_V_TOTAL_F2,
+		DSS_REG_W(io, HDMI_V_TOTAL_F2,
 			((total_v + 1) << 0) & 0x00000FFF);
 
-		HDMI_REG_W(io->base, HDMI_ACTIVE_V_F2,
+		DSS_REG_W(io, HDMI_ACTIVE_V_F2,
 			(((start_v + 1) << 0) & 0x00000FFF) |
 			(((end_v + 1) << 16) & 0x0FFF0000));
 	} else {
-		HDMI_REG_W(io->base, HDMI_V_TOTAL_F2, 0);
-		HDMI_REG_W(io->base, HDMI_ACTIVE_V_F2, 0);
+		DSS_REG_W(io, HDMI_V_TOTAL_F2, 0);
+		DSS_REG_W(io, HDMI_ACTIVE_V_F2, 0);
 	}
 
-	HDMI_REG_W(io->base, HDMI_FRAME_CTRL,
+	DSS_REG_W(io, HDMI_FRAME_CTRL,
 		((timing->interlaced << 31) & 0x80000000) |
 		((timing->active_low_h << 29) & 0x20000000) |
 		((timing->active_low_v << 28) & 0x10000000));
@@ -929,28 +935,28 @@ static void hdmi_tx_set_avi_infoframe(struct hdmi_tx_ctrl *hdmi_ctrl)
 	regVal = regVal << 8 | avi_iframe[4];
 	regVal = regVal << 8 | avi_iframe[3];
 	regVal = regVal << 8 | checksum;
-	HDMI_REG_W(io->base, HDMI_AVI_INFO0, regVal);
+	DSS_REG_W(io, HDMI_AVI_INFO0, regVal);
 
 	regVal = avi_iframe[9];
 	regVal = regVal << 8 | avi_iframe[8];
 	regVal = regVal << 8 | avi_iframe[7];
 	regVal = regVal << 8 | avi_iframe[6];
-	HDMI_REG_W(io->base, HDMI_AVI_INFO1, regVal);
+	DSS_REG_W(io, HDMI_AVI_INFO1, regVal);
 
 	regVal = avi_iframe[13];
 	regVal = regVal << 8 | avi_iframe[12];
 	regVal = regVal << 8 | avi_iframe[11];
 	regVal = regVal << 8 | avi_iframe[10];
-	HDMI_REG_W(io->base, HDMI_AVI_INFO2, regVal);
+	DSS_REG_W(io, HDMI_AVI_INFO2, regVal);
 
 	regVal = avi_iframe[1];
 	regVal = regVal << 16 | avi_iframe[15];
 	regVal = regVal << 8 | avi_iframe[14];
-	HDMI_REG_W(io->base, HDMI_AVI_INFO3, regVal);
+	DSS_REG_W(io, HDMI_AVI_INFO3, regVal);
 
 	/* 0x3 for AVI InfFrame enable (every frame) */
-	HDMI_REG_W(io->base, HDMI_INFOFRAME_CTRL0,
-		HDMI_REG_R(io->base, HDMI_INFOFRAME_CTRL0) |
+	DSS_REG_W(io, HDMI_INFOFRAME_CTRL0,
+		DSS_REG_R(io, HDMI_INFOFRAME_CTRL0) |
 		0x00000003L);
 } /* hdmi_tx_set_avi_infoframe */
 
@@ -986,14 +992,14 @@ static void hdmi_tx_set_spd_infoframe(struct hdmi_tx_ctrl *hdmi_ctrl)
 	 * 0x19 Length of Source Product Description InfoFrame
 	 */
 	packet_header  = 0x83 | (0x01 << 8) | (0x19 << 16);
-	HDMI_REG_W(io->base, HDMI_GENERIC1_HDR, packet_header);
+	DSS_REG_W(io, HDMI_GENERIC1_HDR, packet_header);
 	check_sum += IFRAME_CHECKSUM_32(packet_header);
 
 	packet_payload = (vendor_name[3] & 0x7f)
 		| ((vendor_name[4] & 0x7f) << 8)
 		| ((vendor_name[5] & 0x7f) << 16)
 		| ((vendor_name[6] & 0x7f) << 24);
-	HDMI_REG_W(io->base, HDMI_GENERIC1_1, packet_payload);
+	DSS_REG_W(io, HDMI_GENERIC1_1, packet_payload);
 	check_sum += IFRAME_CHECKSUM_32(packet_payload);
 
 	/* Product Description (7-bit ASCII code) */
@@ -1001,28 +1007,28 @@ static void hdmi_tx_set_spd_infoframe(struct hdmi_tx_ctrl *hdmi_ctrl)
 		| ((product_description[0] & 0x7f) << 8)
 		| ((product_description[1] & 0x7f) << 16)
 		| ((product_description[2] & 0x7f) << 24);
-	HDMI_REG_W(io->base, HDMI_GENERIC1_2, packet_payload);
+	DSS_REG_W(io, HDMI_GENERIC1_2, packet_payload);
 	check_sum += IFRAME_CHECKSUM_32(packet_payload);
 
 	packet_payload = (product_description[3] & 0x7f)
 		| ((product_description[4] & 0x7f) << 8)
 		| ((product_description[5] & 0x7f) << 16)
 		| ((product_description[6] & 0x7f) << 24);
-	HDMI_REG_W(io->base, HDMI_GENERIC1_3, packet_payload);
+	DSS_REG_W(io, HDMI_GENERIC1_3, packet_payload);
 	check_sum += IFRAME_CHECKSUM_32(packet_payload);
 
 	packet_payload = (product_description[7] & 0x7f)
 		| ((product_description[8] & 0x7f) << 8)
 		| ((product_description[9] & 0x7f) << 16)
 		| ((product_description[10] & 0x7f) << 24);
-	HDMI_REG_W(io->base, HDMI_GENERIC1_4, packet_payload);
+	DSS_REG_W(io, HDMI_GENERIC1_4, packet_payload);
 	check_sum += IFRAME_CHECKSUM_32(packet_payload);
 
 	packet_payload = (product_description[11] & 0x7f)
 		| ((product_description[12] & 0x7f) << 8)
 		| ((product_description[13] & 0x7f) << 16)
 		| ((product_description[14] & 0x7f) << 24);
-	HDMI_REG_W(io->base, HDMI_GENERIC1_5, packet_payload);
+	DSS_REG_W(io, HDMI_GENERIC1_5, packet_payload);
 	check_sum += IFRAME_CHECKSUM_32(packet_payload);
 
 	/*
@@ -1039,7 +1045,7 @@ static void hdmi_tx_set_spd_infoframe(struct hdmi_tx_ctrl *hdmi_ctrl)
 	 * 09h PC general
 	 */
 	packet_payload = (product_description[15] & 0x7f) | 0x00 << 8;
-	HDMI_REG_W(io->base, HDMI_GENERIC1_6, packet_payload);
+	DSS_REG_W(io, HDMI_GENERIC1_6, packet_payload);
 	check_sum += IFRAME_CHECKSUM_32(packet_payload);
 
 	/* Vendor Name (7bit ASCII code) */
@@ -1048,7 +1054,7 @@ static void hdmi_tx_set_spd_infoframe(struct hdmi_tx_ctrl *hdmi_ctrl)
 		| ((vendor_name[2] & 0x7f) << 24);
 	check_sum += IFRAME_CHECKSUM_32(packet_payload);
 	packet_payload |= ((0x100 - (0xff & check_sum)) & 0xff);
-	HDMI_REG_W(io->base, HDMI_GENERIC1_0, packet_payload);
+	DSS_REG_W(io, HDMI_GENERIC1_0, packet_payload);
 
 	/*
 	 * GENERIC1_LINE | GENERIC1_CONT | GENERIC1_SEND
@@ -1056,9 +1062,9 @@ static void hdmi_tx_set_spd_infoframe(struct hdmi_tx_ctrl *hdmi_ctrl)
 	 * Enable this packet to transmit every frame
 	 * Enable HDMI TX engine to transmit Generic packet 1
 	 */
-	packet_control = HDMI_REG_R_ND(io->base, HDMI_GEN_PKT_CTRL);
+	packet_control = DSS_REG_R_ND(io, HDMI_GEN_PKT_CTRL);
 	packet_control |= ((0x1 << 24) | (1 << 5) | (1 << 4));
-	HDMI_REG_W(io->base, HDMI_GEN_PKT_CTRL, packet_control);
+	DSS_REG_W(io, HDMI_GEN_PKT_CTRL, packet_control);
 } /* hdmi_tx_set_spd_infoframe */
 
 /* todo: revisit when new HPD debouncing logic is avialble */
@@ -1075,11 +1081,17 @@ static void hdmi_tx_hpd_state_timer(unsigned long data)
 static void hdmi_tx_set_mode(struct hdmi_tx_ctrl *hdmi_ctrl, u32 power_on)
 {
 	u32 reg_val = 0;
+	struct dss_io_data *io = NULL;
 
 	if (!hdmi_ctrl) {
 		DEV_ERR("%s: invalid input\n", __func__);
 		return;
 	}
+	io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+	if (!io->base) {
+		DEV_ERR("%s: Core io is not initialized\n", __func__);
+		return;
+	}
 
 	if (power_on) {
 		/* ENABLE */
@@ -1101,8 +1113,7 @@ static void hdmi_tx_set_mode(struct hdmi_tx_ctrl *hdmi_ctrl, u32 power_on)
 		reg_val = BIT(1);
 	}
 
-	HDMI_REG_W(hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO].base, HDMI_CTRL,
-		reg_val);
+	DSS_REG_W(io, HDMI_CTRL, reg_val);
 
 	DEV_DBG("HDMI Core: %s, HDMI_CTRL=0x%08x\n",
 		power_on ? "Enable" : "Disable", reg_val);
@@ -1311,36 +1322,34 @@ static void hdmi_tx_phy_reset(struct hdmi_tx_ctrl *hdmi_ctrl)
 
 	io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
 	if (!io->base) {
-		DEV_ERR("%s: io not inititalized\n", __func__);
+		DEV_ERR("%s: core io not inititalized\n", __func__);
 		return;
 	}
 
-	val = HDMI_REG_R_ND(io->base, HDMI_PHY_CTRL);
+	val = DSS_REG_R_ND(io, HDMI_PHY_CTRL);
 
 	phy_reset_polarity = val >> 3 & 0x1;
 	pll_reset_polarity = val >> 1 & 0x1;
 
 	if (phy_reset_polarity == 0)
-		HDMI_REG_W_ND(io->base, HDMI_PHY_CTRL, val | SW_RESET);
+		DSS_REG_W_ND(io, HDMI_PHY_CTRL, val | SW_RESET);
 	else
-		HDMI_REG_W_ND(io->base, HDMI_PHY_CTRL, val & (~SW_RESET));
+		DSS_REG_W_ND(io, HDMI_PHY_CTRL, val & (~SW_RESET));
 
 	if (pll_reset_polarity == 0)
-		HDMI_REG_W_ND(io->base, HDMI_PHY_CTRL, val | SW_RESET_PLL);
+		DSS_REG_W_ND(io, HDMI_PHY_CTRL, val | SW_RESET_PLL);
 	else
-		HDMI_REG_W_ND(io->base,
-			HDMI_PHY_CTRL, val & (~SW_RESET_PLL));
+		DSS_REG_W_ND(io, HDMI_PHY_CTRL, val & (~SW_RESET_PLL));
 
 	if (phy_reset_polarity == 0)
-		HDMI_REG_W_ND(io->base, HDMI_PHY_CTRL, val & (~SW_RESET));
+		DSS_REG_W_ND(io, HDMI_PHY_CTRL, val & (~SW_RESET));
 	else
-		HDMI_REG_W_ND(io->base, HDMI_PHY_CTRL, val | SW_RESET);
+		DSS_REG_W_ND(io, HDMI_PHY_CTRL, val | SW_RESET);
 
 	if (pll_reset_polarity == 0)
-		HDMI_REG_W_ND(io->base,
-			HDMI_PHY_CTRL, val & (~SW_RESET_PLL));
+		DSS_REG_W_ND(io, HDMI_PHY_CTRL, val & (~SW_RESET_PLL));
 	else
-		HDMI_REG_W_ND(io->base, HDMI_PHY_CTRL, val | SW_RESET_PLL);
+		DSS_REG_W_ND(io, HDMI_PHY_CTRL, val | SW_RESET_PLL);
 } /* hdmi_tx_phy_reset */
 
 static void hdmi_tx_init_phy(struct hdmi_tx_ctrl *hdmi_ctrl)
@@ -1354,40 +1363,53 @@ static void hdmi_tx_init_phy(struct hdmi_tx_ctrl *hdmi_ctrl)
 
 	io = &hdmi_ctrl->pdata.io[HDMI_TX_PHY_IO];
 	if (!io->base) {
-		DEV_ERR("%s: Core io is not initialized\n", __func__);
+		DEV_ERR("%s: phy io is not initialized\n", __func__);
 		return;
 	}
 
-	HDMI_REG_W_ND(io->base, HDMI_PHY_ANA_CFG0, 0x1B);
-	HDMI_REG_W_ND(io->base, HDMI_PHY_ANA_CFG1, 0xF2);
-	HDMI_REG_W_ND(io->base, HDMI_PHY_BIST_CFG0, 0x0);
-	HDMI_REG_W_ND(io->base, HDMI_PHY_BIST_PATN0, 0x0);
-	HDMI_REG_W_ND(io->base, HDMI_PHY_BIST_PATN1, 0x0);
-	HDMI_REG_W_ND(io->base, HDMI_PHY_BIST_PATN2, 0x0);
-	HDMI_REG_W_ND(io->base, HDMI_PHY_BIST_PATN3, 0x0);
+	DSS_REG_W_ND(io, HDMI_PHY_ANA_CFG0, 0x1B);
+	DSS_REG_W_ND(io, HDMI_PHY_ANA_CFG1, 0xF2);
+	DSS_REG_W_ND(io, HDMI_PHY_BIST_CFG0, 0x0);
+	DSS_REG_W_ND(io, HDMI_PHY_BIST_PATN0, 0x0);
+	DSS_REG_W_ND(io, HDMI_PHY_BIST_PATN1, 0x0);
+	DSS_REG_W_ND(io, HDMI_PHY_BIST_PATN2, 0x0);
+	DSS_REG_W_ND(io, HDMI_PHY_BIST_PATN3, 0x0);
 
-	HDMI_REG_W_ND(io->base, HDMI_PHY_PD_CTRL1, 0x20);
+	DSS_REG_W_ND(io, HDMI_PHY_PD_CTRL1, 0x20);
 } /* hdmi_tx_init_phy */
 
 static void hdmi_tx_powerdown_phy(struct hdmi_tx_ctrl *hdmi_ctrl)
 {
+	struct dss_io_data *io = NULL;
+
 	if (!hdmi_ctrl) {
 		DEV_ERR("%s: invalid input\n", __func__);
 		return;
 	}
+	io = &hdmi_ctrl->pdata.io[HDMI_TX_PHY_IO];
+	if (!io->base) {
+		DEV_ERR("%s: phy io is not initialized\n", __func__);
+		return;
+	}
 
-	HDMI_REG_W_ND(hdmi_ctrl->pdata.io[HDMI_TX_PHY_IO].base,
-		HDMI_PHY_PD_CTRL0, 0x7F);
+	DSS_REG_W_ND(io, HDMI_PHY_PD_CTRL0, 0x7F);
 } /* hdmi_tx_powerdown_phy */
 
 static int hdmi_tx_start(struct hdmi_tx_ctrl *hdmi_ctrl)
 {
 	int rc = 0;
+	struct dss_io_data *io = NULL;
 
 	if (!hdmi_ctrl) {
 		DEV_ERR("%s: invalid input\n", __func__);
 		return -EINVAL;
 	}
+	io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+	if (!io->base) {
+		DEV_ERR("%s: core io is not initialized\n", __func__);
+		return -EINVAL;
+	}
+
 	/* todo: Audio */
 
 	hdmi_tx_set_mode(hdmi_ctrl, false);
@@ -1401,8 +1423,7 @@ static int hdmi_tx_start(struct hdmi_tx_ctrl *hdmi_ctrl)
 	mutex_unlock(&hdmi_ctrl->mutex);
 
 	hdmi_tx_init_phy(hdmi_ctrl);
-	HDMI_REG_W(hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO].base,
-		HDMI_USEC_REFTIMER, 0x0001001B);
+	DSS_REG_W(io, HDMI_USEC_REFTIMER, 0x0001001B);
 
 	hdmi_tx_set_mode(hdmi_ctrl, true);
 
@@ -1413,8 +1434,7 @@ static int hdmi_tx_start(struct hdmi_tx_ctrl *hdmi_ctrl)
 	hdmi_tx_set_spd_infoframe(hdmi_ctrl);
 
 	/* Set IRQ for HPD */
-	HDMI_REG_W(hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO].base,
-		HDMI_HPD_INT_CTRL, 4 | (hdmi_ctrl->hpd_state ? 0 : 2));
+	DSS_REG_W(io, HDMI_HPD_INT_CTRL, 4 | (hdmi_ctrl->hpd_state ? 0 : 2));
 
 	/* todo: HDCP/CEC */
 
@@ -1451,6 +1471,7 @@ static int hdmi_tx_power_off(struct mdss_panel_data *panel_data)
 static int hdmi_tx_power_on(struct mdss_panel_data *panel_data)
 {
 	int rc = 0;
+	struct dss_io_data *io = NULL;
 	struct hdmi_tx_ctrl *hdmi_ctrl =
 		hdmi_tx_get_drvdata_from_panel_data(panel_data);
 
@@ -1458,6 +1479,11 @@ static int hdmi_tx_power_on(struct mdss_panel_data *panel_data)
 		DEV_ERR("%s: invalid input\n", __func__);
 		return -EINVAL;
 	}
+	io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+	if (!io->base) {
+		DEV_ERR("%s: core io is not initialized\n", __func__);
+		return -EINVAL;
+	}
 
 	rc = hdmi_tx_core_on(hdmi_ctrl);
 	if (rc) {
@@ -1494,8 +1520,7 @@ static int hdmi_tx_power_on(struct mdss_panel_data *panel_data)
 		mutex_unlock(&hdmi_ctrl->mutex);
 	}
 
-	hdmi_reg_dump(hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO].base,
-		hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO].len, "HDMI-ON: ");
+	dss_reg_dump(io->base, io->len, "HDMI-ON: ", REG_DUMP);
 
 	DEV_INFO("%s: HDMI=%s DVI= %s\n", __func__,
 		hdmi_tx_is_controller_on(hdmi_ctrl) ? "ON" : "OFF" ,
@@ -1552,7 +1577,7 @@ static int hdmi_tx_hpd_on(struct hdmi_tx_ctrl *hdmi_ctrl)
 
 	io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
 	if (!io->base) {
-		DEV_ERR("%s: io not inititalized\n", __func__);
+		DEV_ERR("%s: core io not inititalized\n", __func__);
 		return -EINVAL;
 	}
 
@@ -1576,21 +1601,21 @@ static int hdmi_tx_hpd_on(struct hdmi_tx_ctrl *hdmi_ctrl)
 		}
 		mutex_unlock(&hdmi_ctrl->mutex);
 
-		hdmi_reg_dump(io->base, io->len, "HDMI-INIT: ");
+		dss_reg_dump(io->base, io->len, "HDMI-INIT: ", REG_DUMP);
 
 		hdmi_tx_set_mode(hdmi_ctrl, false);
 		hdmi_tx_phy_reset(hdmi_ctrl);
 		hdmi_tx_set_mode(hdmi_ctrl, true);
 
-		HDMI_REG_W(io->base, HDMI_USEC_REFTIMER, 0x0001001B);
+		DSS_REG_W(io, HDMI_USEC_REFTIMER, 0x0001001B);
 
 		/* set timeout to 4.1ms (max) for hardware debounce */
-		reg_val = HDMI_REG_R(io->base, HDMI_HPD_CTRL) | 0x1FFF;
+		reg_val = DSS_REG_R(io, HDMI_HPD_CTRL) | 0x1FFF;
 
 		/* Toggle HPD circuit to trigger HPD sense */
-		HDMI_REG_W(io->base, HDMI_HPD_CTRL,
+		DSS_REG_W(io, HDMI_HPD_CTRL,
 			~(1 << 28) & reg_val);
-		HDMI_REG_W(io->base, HDMI_HPD_CTRL, (1 << 28) | reg_val);
+		DSS_REG_W(io, HDMI_HPD_CTRL, (1 << 28) | reg_val);
 
 		hdmi_ctrl->hpd_initialized = true;
 
@@ -1652,13 +1677,14 @@ static irqreturn_t hdmi_tx_isr(int irq, void *data)
 
 	io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
 	if (!io->base) {
-		DEV_WARN("%s: io not initialized, ISR ignored\n", __func__);
+		DEV_WARN("%s: core io not initialized, ISR ignored\n",
+			__func__);
 		return IRQ_HANDLED;
 	}
 
 	/* Process HPD Interrupt */
-	hpd_int_status = HDMI_REG_R(io->base, HDMI_HPD_INT_STATUS);
-	hpd_int_ctrl = HDMI_REG_R(io->base, HDMI_HPD_INT_CTRL);
+	hpd_int_status = DSS_REG_R(io, HDMI_HPD_INT_STATUS);
+	hpd_int_ctrl = DSS_REG_R(io, HDMI_HPD_INT_CTRL);
 	if ((hpd_int_ctrl & BIT(2)) && (hpd_int_status & BIT(0))) {
 		u32 cable_detected = hpd_int_status & BIT(1);
 
@@ -1667,7 +1693,7 @@ static irqreturn_t hdmi_tx_isr(int irq, void *data)
 		 * Leaving the bit[2] on, else core goes off
 		 * on getting HPD during power off.
 		 */
-		HDMI_REG_W(io->base, HDMI_HPD_INT_CTRL, BIT(2) | BIT(0));
+		DSS_REG_W(io, HDMI_HPD_INT_CTRL, BIT(2) | BIT(0));
 
 		DEV_DBG("%s: HPD IRQ, Ctrl=%04x, State=%04x\n", __func__,
 			hpd_int_ctrl, hpd_int_status);
@@ -1785,7 +1811,7 @@ static int hdmi_tx_dev_init(struct hdmi_tx_ctrl *hdmi_ctrl)
 
 	pdata = &hdmi_ctrl->pdata;
 
-	rc = hdmi_tx_check_capability(pdata->io[HDMI_TX_QFPROM_IO].base);
+	rc = hdmi_tx_check_capability(&pdata->io[HDMI_TX_QFPROM_IO]);
 	if (rc) {
 		DEV_ERR("%s: no HDMI device\n", __func__);
 		goto fail_no_hdmi;
@@ -1802,8 +1828,7 @@ static int hdmi_tx_dev_init(struct hdmi_tx_ctrl *hdmi_ctrl)
 		goto fail_create_workq;
 	}
 
-	/* todo: May be move this ? */
-	hdmi_ctrl->ddc_ctrl.base = pdata->io[HDMI_TX_CORE_IO].base;
+	hdmi_ctrl->ddc_ctrl.io = &pdata->io[HDMI_TX_CORE_IO];
 	init_completion(&hdmi_ctrl->ddc_ctrl.ddc_sw_done);
 
 	INIT_WORK(&hdmi_ctrl->hpd_state_work, hdmi_tx_hpd_state_work);
diff --git a/drivers/video/fbdev/msm/mdss_hdmi_tx.h b/drivers/video/fbdev/msm/mdss_hdmi_tx.h
index 747059c0cb83..e09fe45b40a7 100644
--- a/drivers/video/fbdev/msm/mdss_hdmi_tx.h
+++ b/drivers/video/fbdev/msm/mdss_hdmi_tx.h
@@ -15,7 +15,6 @@
 
 #include <linux/switch.h>
 #include "mdss_hdmi_util.h"
-#include "mdss_io_util.h"
 
 enum hdmi_tx_clk_type {
 	HDMI_TX_AHB_CLK,
diff --git a/drivers/video/fbdev/msm/mdss_hdmi_util.c b/drivers/video/fbdev/msm/mdss_hdmi_util.c
index e759adfb23f9..136f0ec2bd9c 100644
--- a/drivers/video/fbdev/msm/mdss_hdmi_util.c
+++ b/drivers/video/fbdev/msm/mdss_hdmi_util.c
@@ -15,226 +15,6 @@
 #include <mach/board.h>
 #include "mdss_hdmi_util.h"
 
-const char *hdmi_reg_name(u32 offset)
-{
-	switch (offset) {
-	case 0x00000000: return "HDMI_CTRL";
-	case 0x00000010: return "HDMI_TEST_PATTERN";
-	case 0x00000014: return "HDMI_RANDOM_PATTERN";
-	case 0x00000018: return "HDMI_PKT_BLK_CTRL";
-	case 0x0000001C: return "HDMI_STATUS";
-	case 0x00000020: return "HDMI_AUDIO_PKT_CTRL";
-	case 0x00000024: return "HDMI_ACR_PKT_CTRL";
-	case 0x00000028: return "HDMI_VBI_PKT_CTRL";
-	case 0x0000002C: return "HDMI_INFOFRAME_CTRL0";
-	case 0x00000030: return "HDMI_INFOFRAME_CTRL1";
-	case 0x00000034: return "HDMI_GEN_PKT_CTRL";
-	case 0x0000003C: return "HDMI_ACP";
-	case 0x00000040: return "HDMI_GC";
-	case 0x00000044: return "HDMI_AUDIO_PKT_CTRL2";
-	case 0x00000048: return "HDMI_ISRC1_0";
-	case 0x0000004C: return "HDMI_ISRC1_1";
-	case 0x00000050: return "HDMI_ISRC1_2";
-	case 0x00000054: return "HDMI_ISRC1_3";
-	case 0x00000058: return "HDMI_ISRC1_4";
-	case 0x0000005C: return "HDMI_ISRC2_0";
-	case 0x00000060: return "HDMI_ISRC2_1";
-	case 0x00000064: return "HDMI_ISRC2_2";
-	case 0x00000068: return "HDMI_ISRC2_3";
-	case 0x0000006C: return "HDMI_AVI_INFO0";
-	case 0x00000070: return "HDMI_AVI_INFO1";
-	case 0x00000074: return "HDMI_AVI_INFO2";
-	case 0x00000078: return "HDMI_AVI_INFO3";
-	case 0x0000007C: return "HDMI_MPEG_INFO0";
-	case 0x00000080: return "HDMI_MPEG_INFO1";
-	case 0x00000084: return "HDMI_GENERIC0_HDR";
-	case 0x00000088: return "HDMI_GENERIC0_0";
-	case 0x0000008C: return "HDMI_GENERIC0_1";
-	case 0x00000090: return "HDMI_GENERIC0_2";
-	case 0x00000094: return "HDMI_GENERIC0_3";
-	case 0x00000098: return "HDMI_GENERIC0_4";
-	case 0x0000009C: return "HDMI_GENERIC0_5";
-	case 0x000000A0: return "HDMI_GENERIC0_6";
-	case 0x000000A4: return "HDMI_GENERIC1_HDR";
-	case 0x000000A8: return "HDMI_GENERIC1_0";
-	case 0x000000AC: return "HDMI_GENERIC1_1";
-	case 0x000000B0: return "HDMI_GENERIC1_2";
-	case 0x000000B4: return "HDMI_GENERIC1_3";
-	case 0x000000B8: return "HDMI_GENERIC1_4";
-	case 0x000000BC: return "HDMI_GENERIC1_5";
-	case 0x000000C0: return "HDMI_GENERIC1_6";
-	case 0x000000C4: return "HDMI_ACR_32_0";
-	case 0x000000C8: return "HDMI_ACR_32_1";
-	case 0x000000CC: return "HDMI_ACR_44_0";
-	case 0x000000D0: return "HDMI_ACR_44_1";
-	case 0x000000D4: return "HDMI_ACR_48_0";
-	case 0x000000D8: return "HDMI_ACR_48_1";
-	case 0x000000DC: return "HDMI_ACR_STATUS_0";
-	case 0x000000E0: return "HDMI_ACR_STATUS_1";
-	case 0x000000E4: return "HDMI_AUDIO_INFO0";
-	case 0x000000E8: return "HDMI_AUDIO_INFO1";
-	case 0x000000EC: return "HDMI_CS_60958_0";
-	case 0x000000F0: return "HDMI_CS_60958_1";
-	case 0x000000F8: return "HDMI_RAMP_CTRL0";
-	case 0x000000FC: return "HDMI_RAMP_CTRL1";
-	case 0x00000100: return "HDMI_RAMP_CTRL2";
-	case 0x00000104: return "HDMI_RAMP_CTRL3";
-	case 0x00000108: return "HDMI_CS_60958_2";
-	case 0x00000110: return "HDMI_HDCP_CTRL";
-	case 0x00000114: return "HDMI_HDCP_DEBUG_CTRL";
-	case 0x00000118: return "HDMI_HDCP_INT_CTRL";
-	case 0x0000011C: return "HDMI_HDCP_LINK0_STATUS";
-	case 0x00000120: return "HDMI_HDCP_DDC_CTRL_0";
-	case 0x00000124: return "HDMI_HDCP_DDC_CTRL_1";
-	case 0x00000128: return "HDMI_HDCP_DDC_STATUS";
-	case 0x0000012C: return "HDMI_HDCP_ENTROPY_CTRL0";
-	case 0x00000130: return "HDMI_HDCP_RESET";
-	case 0x00000134: return "HDMI_HDCP_RCVPORT_DATA0";
-	case 0x00000138: return "HDMI_HDCP_RCVPORT_DATA1";
-	case 0x0000013C: return "HDMI_HDCP_RCVPORT_DATA2_0";
-	case 0x00000140: return "HDMI_HDCP_RCVPORT_DATA2_1";
-	case 0x00000144: return "HDMI_HDCP_RCVPORT_DATA3";
-	case 0x00000148: return "HDMI_HDCP_RCVPORT_DATA4";
-	case 0x0000014C: return "HDMI_HDCP_RCVPORT_DATA5";
-	case 0x00000150: return "HDMI_HDCP_RCVPORT_DATA6";
-	case 0x00000154: return "HDMI_HDCP_RCVPORT_DATA7";
-	case 0x00000158: return "HDMI_HDCP_RCVPORT_DATA8";
-	case 0x0000015C: return "HDMI_HDCP_RCVPORT_DATA9";
-	case 0x00000160: return "HDMI_HDCP_RCVPORT_DATA10";
-	case 0x00000164: return "HDMI_HDCP_RCVPORT_DATA11";
-	case 0x00000168: return "HDMI_HDCP_RCVPORT_DATA12";
-	case 0x0000016C: return "HDMI_VENSPEC_INFO0";
-	case 0x00000170: return "HDMI_VENSPEC_INFO1";
-	case 0x00000174: return "HDMI_VENSPEC_INFO2";
-	case 0x00000178: return "HDMI_VENSPEC_INFO3";
-	case 0x0000017C: return "HDMI_VENSPEC_INFO4";
-	case 0x00000180: return "HDMI_VENSPEC_INFO5";
-	case 0x00000184: return "HDMI_VENSPEC_INFO6";
-	case 0x00000194: return "HDMI_HDCP_DEBUG";
-	case 0x0000019C: return "HDMI_TMDS_CTRL_CHAR";
-	case 0x000001A4: return "HDMI_TMDS_CTRL_SEL";
-	case 0x000001A8: return "HDMI_TMDS_SYNCCHAR01";
-	case 0x000001AC: return "HDMI_TMDS_SYNCCHAR23";
-	case 0x000001B4: return "HDMI_TMDS_DEBUG";
-	case 0x000001B8: return "HDMI_TMDS_CTL_BITS";
-	case 0x000001BC: return "HDMI_TMDS_DCBAL_CTRL";
-	case 0x000001C0: return "HDMI_TMDS_DCBAL_CHAR";
-	case 0x000001C8: return "HDMI_TMDS_CTL01_GEN";
-	case 0x000001CC: return "HDMI_TMDS_CTL23_GEN";
-	case 0x000001D0: return "HDMI_AUDIO_CFG";
-	case 0x00000204: return "HDMI_DEBUG";
-	case 0x00000208: return "HDMI_USEC_REFTIMER";
-	case 0x0000020C: return "HDMI_DDC_CTRL";
-	case 0x00000210: return "HDMI_DDC_ARBITRATION";
-	case 0x00000214: return "HDMI_DDC_INT_CTRL";
-	case 0x00000218: return "HDMI_DDC_SW_STATUS";
-	case 0x0000021C: return "HDMI_DDC_HW_STATUS";
-	case 0x00000220: return "HDMI_DDC_SPEED";
-	case 0x00000224: return "HDMI_DDC_SETUP";
-	case 0x00000228: return "HDMI_DDC_TRANS0";
-	case 0x0000022C: return "HDMI_DDC_TRANS1";
-	case 0x00000230: return "HDMI_DDC_TRANS2";
-	case 0x00000234: return "HDMI_DDC_TRANS3";
-	case 0x00000238: return "HDMI_DDC_DATA";
-	case 0x0000023C: return "HDMI_HDCP_SHA_CTRL";
-	case 0x00000240: return "HDMI_HDCP_SHA_STATUS";
-	case 0x00000244: return "HDMI_HDCP_SHA_DATA";
-	case 0x00000248: return "HDMI_HDCP_SHA_DBG_M0_0";
-	case 0x0000024C: return "HDMI_HDCP_SHA_DBG_M0_1";
-	case 0x00000250: return "HDMI_HPD_INT_STATUS";
-	case 0x00000254: return "HDMI_HPD_INT_CTRL";
-	case 0x00000258: return "HDMI_HPD_CTRL";
-	case 0x0000025C: return "HDMI_HDCP_ENTROPY_CTRL1";
-	case 0x00000260: return "HDMI_HDCP_SW_UPPER_AN";
-	case 0x00000264: return "HDMI_HDCP_SW_LOWER_AN";
-	case 0x00000268: return "HDMI_CRC_CTRL";
-	case 0x0000026C: return "HDMI_VID_CRC";
-	case 0x00000270: return "HDMI_AUD_CRC";
-	case 0x00000274: return "HDMI_VBI_CRC";
-	case 0x0000027C: return "HDMI_DDC_REF";
-	case 0x00000284: return "HDMI_HDCP_SW_UPPER_AKSV";
-	case 0x00000288: return "HDMI_HDCP_SW_LOWER_AKSV";
-	case 0x0000028C: return "HDMI_CEC_CTRL";
-	case 0x00000290: return "HDMI_CEC_WR_DATA";
-	case 0x00000294: return "HDMI_CEC_RETRANSMIT";
-	case 0x00000298: return "HDMI_CEC_STATUS";
-	case 0x0000029C: return "HDMI_CEC_INT";
-	case 0x000002A0: return "HDMI_CEC_ADDR";
-	case 0x000002A4: return "HDMI_CEC_TIME";
-	case 0x000002A8: return "HDMI_CEC_REFTIMER";
-	case 0x000002AC: return "HDMI_CEC_RD_DATA";
-	case 0x000002B0: return "HDMI_CEC_RD_FILTER";
-	case 0x000002B4: return "HDMI_ACTIVE_H";
-	case 0x000002B8: return "HDMI_ACTIVE_V";
-	case 0x000002BC: return "HDMI_ACTIVE_V_F2";
-	case 0x000002C0: return "HDMI_TOTAL";
-	case 0x000002C4: return "HDMI_V_TOTAL_F2";
-	case 0x000002C8: return "HDMI_FRAME_CTRL";
-	case 0x000002CC: return "HDMI_AUD_INT";
-	case 0x000002D0: return "HDMI_DEBUG_BUS_CTRL";
-	case 0x000002D4: return "HDMI_PHY_CTRL";
-	case 0x000002DC: return "HDMI_CEC_WR_RANGE";
-	case 0x000002E0: return "HDMI_CEC_RD_RANGE";
-	case 0x000002E4: return "HDMI_VERSION";
-	case 0x000002F4: return "HDMI_BIST_ENABLE";
-	case 0x000002F8: return "HDMI_TIMING_ENGINE_EN";
-	case 0x000002FC: return "HDMI_INTF_CONFIG";
-	case 0x00000300: return "HDMI_HSYNC_CTL";
-	case 0x00000304: return "HDMI_VSYNC_PERIOD_F0";
-	case 0x00000308: return "HDMI_VSYNC_PERIOD_F1";
-	case 0x0000030C: return "HDMI_VSYNC_PULSE_WIDTH_F0";
-	case 0x00000310: return "HDMI_VSYNC_PULSE_WIDTH_F1";
-	case 0x00000314: return "HDMI_DISPLAY_V_START_F0";
-	case 0x00000318: return "HDMI_DISPLAY_V_START_F1";
-	case 0x0000031C: return "HDMI_DISPLAY_V_END_F0";
-	case 0x00000320: return "HDMI_DISPLAY_V_END_F1";
-	case 0x00000324: return "HDMI_ACTIVE_V_START_F0";
-	case 0x00000328: return "HDMI_ACTIVE_V_START_F1";
-	case 0x0000032C: return "HDMI_ACTIVE_V_END_F0";
-	case 0x00000330: return "HDMI_ACTIVE_V_END_F1";
-	case 0x00000334: return "HDMI_DISPLAY_HCTL";
-	case 0x00000338: return "HDMI_ACTIVE_HCTL";
-	case 0x0000033C: return "HDMI_HSYNC_SKEW";
-	case 0x00000340: return "HDMI_POLARITY_CTL";
-	case 0x00000344: return "HDMI_TPG_MAIN_CONTROL";
-	case 0x00000348: return "HDMI_TPG_VIDEO_CONFIG";
-	case 0x0000034C: return "HDMI_TPG_COMPONENT_LIMITS";
-	case 0x00000350: return "HDMI_TPG_RECTANGLE";
-	case 0x00000354: return "HDMI_TPG_INITIAL_VALUE";
-	case 0x00000358: return "HDMI_TPG_BLK_WHT_PATTERN_FRAMES";
-	case 0x0000035C: return "HDMI_TPG_RGB_MAPPING";
-	default: return "???";
-	}
-} /* hdmi_reg_name */
-
-void hdmi_reg_w(void __iomem *addr, u32 offset, u32 value, u32 debug)
-{
-	u32 in_val;
-
-	writel_relaxed(value, addr+offset);
-	if (debug && PORT_DEBUG) {
-		in_val = readl_relaxed(addr+offset);
-		DEV_DBG("HDMI[%04x] => %08x [%08x] %s\n", offset, value,
-			in_val, hdmi_reg_name(offset));
-	}
-} /* hdmi_reg_w */
-
-u32 hdmi_reg_r(void __iomem *addr, u32 offset, u32 debug)
-{
-	u32 value = readl_relaxed(addr+offset);
-	if (debug && PORT_DEBUG)
-		DEV_DBG("HDMI[%04x] <= %08x %s\n", offset, value,
-			hdmi_reg_name(offset));
-	return value;
-} /* hdmi_reg_r */
-
-void hdmi_reg_dump(void __iomem *base, u32 length, const char *prefix)
-{
-	if (REG_DUMP)
-		print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 32, 4,
-			(void *)base, length, false);
-} /* hdmi_reg_dump */
-
 static struct hdmi_disp_mode_timing_type
 	hdmi_supported_video_mode_lut[HDMI_VFRMT_MAX] = {
 	HDMI_SETTINGS_640x480p60_4_3,
@@ -505,7 +285,7 @@ static int hdmi_ddc_clear_irq(struct hdmi_tx_ddc_ctrl *ddc_ctrl,
 {
 	u32 reg_val, time_out_count;
 
-	if (!ddc_ctrl || !ddc_ctrl->base) {
+	if (!ddc_ctrl || !ddc_ctrl->io) {
 		DEV_ERR("%s: invalid input\n", __func__);
 		return -EINVAL;
 	}
@@ -515,9 +295,9 @@ static int hdmi_ddc_clear_irq(struct hdmi_tx_ddc_ctrl *ddc_ctrl,
 	do {
 		--time_out_count;
 		/* Clear and Enable DDC interrupt */
-		HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_INT_CTRL,
+		DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_INT_CTRL,
 			BIT(2) | BIT(1));
-		reg_val = HDMI_REG_R_ND(ddc_ctrl->base, HDMI_DDC_INT_CTRL);
+		reg_val = DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_INT_CTRL);
 	} while ((reg_val & BIT(0)) && time_out_count);
 
 	if (!time_out_count) {
@@ -535,7 +315,7 @@ static int hdmi_ddc_read_retry(struct hdmi_tx_ddc_ctrl *ddc_ctrl,
 	int status = 0;
 	int log_retry_fail;
 
-	if (!ddc_ctrl || !ddc_ctrl->base || !ddc_data) {
+	if (!ddc_ctrl || !ddc_ctrl->io || !ddc_data) {
 		DEV_ERR("%s: invalid input\n", __func__);
 		return -EINVAL;
 	}
@@ -565,7 +345,7 @@ again:
 	 *    INDEX = 0x0 (initial offset into buffer)
 	 *    INDEX_WRITE = 0x1 (setting initial offset)
 	 */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA,
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA,
 		BIT(31) | (ddc_data->dev_addr << 8));
 
 	/*
@@ -576,7 +356,7 @@ again:
 	 *    INDEX = 0x0
 	 *    INDEX_WRITE = 0x0 (auto-increment by hardware)
 	 */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA, ddc_data->offset << 8);
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA, ddc_data->offset << 8);
 
 	/*
 	 * 3. Write to HDMI_I2C_DATA with the following fields set in order to
@@ -586,7 +366,7 @@ again:
 	 *    INDEX = 0x0
 	 *    INDEX_WRITE = 0x0 (auto-increment by hardware)
 	 */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA,
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA,
 		(ddc_data->dev_addr | BIT(0)) << 8);
 
 	/* Data setup is complete, now setup the transaction characteristics */
@@ -599,7 +379,7 @@ again:
 	 *    STOP0 = 0x0 (do NOT insert STOP bit)
 	 *    CNT0 = 0x1 (single byte transaction excluding address)
 	 */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_TRANS0, BIT(12) | BIT(16));
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_TRANS0, BIT(12) | BIT(16));
 
 	/*
 	 * 5. Write to HDMI_I2C_TRANSACTION1 with the following fields set in
@@ -609,7 +389,7 @@ again:
 	 *    STOP1 = 0x1 (insert STOP bit)
 	 *    CNT1 = data_len   (it's 128 (0x80) for a blk read)
 	 */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_TRANS1,
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_TRANS1,
 		BIT(0) | BIT(12) | BIT(13) | (ddc_data->request_len << 16));
 
 	/* Trigger the I2C transfer */
@@ -624,11 +404,11 @@ again:
 	 *    GO = 0x1 (kicks off hardware)
 	 */
 	INIT_COMPLETION(ddc_ctrl->ddc_sw_done);
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(0) | BIT(20));
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(0) | BIT(20));
 
 	time_out_count = wait_for_completion_interruptible_timeout(
 		&ddc_ctrl->ddc_sw_done, HZ/2);
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_INT_CTRL, BIT(1));
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_INT_CTRL, BIT(1));
 	if (!time_out_count) {
 		if (ddc_data->retry-- > 0) {
 			DEV_INFO("%s: failed timout, retry=%d\n", __func__,
@@ -637,26 +417,26 @@ again:
 		}
 		status = -ETIMEDOUT;
 		DEV_ERR("%s: timedout(7), Int Ctrl=%08x\n", __func__,
-			HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_INT_CTRL));
+			DSS_REG_R(ddc_ctrl->io, HDMI_DDC_INT_CTRL));
 		DEV_ERR("%s: DDC SW Status=%08x, HW Status=%08x\n",
 			__func__,
-			HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_SW_STATUS),
-			HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_HW_STATUS));
+			DSS_REG_R(ddc_ctrl->io, HDMI_DDC_SW_STATUS),
+			DSS_REG_R(ddc_ctrl->io, HDMI_DDC_HW_STATUS));
 		goto error;
 	}
 
 	/* Read DDC status */
-	reg_val = HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_SW_STATUS);
+	reg_val = DSS_REG_R(ddc_ctrl->io, HDMI_DDC_SW_STATUS);
 	reg_val &= BIT(12) | BIT(13) | BIT(14) | BIT(15);
 
 	/* Check if any NACK occurred */
 	if (reg_val) {
 		/* SW_STATUS_RESET */
-		HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(3));
+		DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(3));
 
 		if (ddc_data->retry == 1)
 			/* SOFT_RESET */
-			HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(1));
+			DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(1));
 
 		if (ddc_data->retry-- > 0) {
 			DEV_DBG("%s(%s): failed NACK=0x%08x, retry=%d\n",
@@ -687,13 +467,13 @@ again:
 	 *    INDEX_WRITE = 0x1 (explicitly define offset)
 	 */
 	/* Write this data to DDC buffer */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA,
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA,
 		BIT(0) | (3 << 16) | BIT(31));
 
 	/* Discard first byte */
-	HDMI_REG_R_ND(ddc_ctrl->base, HDMI_DDC_DATA);
+	DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_DATA);
 	for (ndx = 0; ndx < ddc_data->data_len; ++ndx) {
-		reg_val = HDMI_REG_R_ND(ddc_ctrl->base, HDMI_DDC_DATA);
+		reg_val = DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_DATA);
 		ddc_data->data_buf[ndx] = (u8)((reg_val & 0x0000FF00) >> 8);
 	}
 
@@ -705,22 +485,22 @@ error:
 
 void hdmi_ddc_config(struct hdmi_tx_ddc_ctrl *ddc_ctrl)
 {
-	if (!ddc_ctrl || !ddc_ctrl->base) {
+	if (!ddc_ctrl || !ddc_ctrl->io) {
 		DEV_ERR("%s: invalid input\n", __func__);
 		return;
 	}
 
 	/* Configure Pre-Scale multiplier & Threshold */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_SPEED, (10 << 16) | (2 << 0));
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_SPEED, (10 << 16) | (2 << 0));
 
 	/*
 	 * Setting 31:24 bits : Time units to wait before timeout
 	 * when clock is being stalled by external sink device
 	 */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_SETUP, 0xFF000000);
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_SETUP, 0xFF000000);
 
 	/* Enable reference timer to 27 micro-seconds */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_REF, (1 << 16) | (27 << 0));
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_REF, (1 << 16) | (27 << 0));
 } /* hdmi_ddc_config */
 
 int hdmi_ddc_isr(struct hdmi_tx_ddc_ctrl *ddc_ctrl)
@@ -728,15 +508,15 @@ int hdmi_ddc_isr(struct hdmi_tx_ddc_ctrl *ddc_ctrl)
 	int rc = -1;
 	u32 ddc_int_ctrl;
 
-	if (!ddc_ctrl || !ddc_ctrl->base) {
+	if (!ddc_ctrl || !ddc_ctrl->io) {
 		DEV_ERR("%s: invalid input\n", __func__);
 		return -EINVAL;
 	}
 
-	ddc_int_ctrl = HDMI_REG_R_ND(ddc_ctrl->base, HDMI_DDC_INT_CTRL);
+	ddc_int_ctrl = DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_INT_CTRL);
 	if ((ddc_int_ctrl & BIT(2)) && (ddc_int_ctrl & BIT(0))) {
 		/* SW_DONE INT occured, clr it */
-		HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_INT_CTRL,
+		DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_INT_CTRL,
 			ddc_int_ctrl | BIT(1));
 		complete(&ddc_ctrl->ddc_sw_done);
 		return 0;
@@ -779,7 +559,7 @@ int hdmi_ddc_read_seg(struct hdmi_tx_ddc_ctrl *ddc_ctrl,
 	int log_retry_fail;
 	int seg_addr = 0x60, seg_num = 0x01;
 
-	if (!ddc_ctrl || !ddc_ctrl->base || !ddc_data) {
+	if (!ddc_ctrl || !ddc_ctrl->io || !ddc_data) {
 		DEV_ERR("%s: invalid input\n", __func__);
 		return -EINVAL;
 	}
@@ -808,7 +588,7 @@ again:
 	 *    INDEX = 0x0 (initial offset into buffer)
 	 *    INDEX_WRITE = 0x1 (setting initial offset)
 	 */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA, BIT(31) | (seg_addr << 8));
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA, BIT(31) | (seg_addr << 8));
 
 	/*
 	 * 2. Write to HDMI_I2C_DATA with the following fields set in order to
@@ -818,7 +598,7 @@ again:
 	 *    INDEX = 0x0
 	 *    INDEX_WRITE = 0x0 (auto-increment by hardware)
 	 */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA, seg_num << 8);
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA, seg_num << 8);
 
 	/*
 	 * 3. Write to HDMI_I2C_DATA with the following fields set in order to
@@ -828,9 +608,9 @@ again:
 	 *    INDEX = 0x0
 	 *    INDEX_WRITE = 0x0 (auto-increment by hardware)
 	 */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA, ddc_data->dev_addr << 8);
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA, ddc_data->offset << 8);
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA,
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA, ddc_data->dev_addr << 8);
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA, ddc_data->offset << 8);
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA,
 		(ddc_data->dev_addr | BIT(0)) << 8);
 
 	/* Data setup is complete, now setup the transaction characteristics */
@@ -843,7 +623,7 @@ again:
 	 *    STOP0 = 0x0 (do NOT insert STOP bit)
 	 *    CNT0 = 0x1 (single byte transaction excluding address)
 	 */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_TRANS0, BIT(12) | BIT(16));
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_TRANS0, BIT(12) | BIT(16));
 
 	/*
 	 * 5. Write to HDMI_I2C_TRANSACTION1 with the following fields set in
@@ -853,7 +633,7 @@ again:
 	 *    STOP1 = 0x1 (insert STOP bit)
 	 *    CNT1 = data_len   (it's 128 (0x80) for a blk read)
 	 */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_TRANS1, BIT(12) | BIT(16));
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_TRANS1, BIT(12) | BIT(16));
 
 	/*
 	 * 5. Write to HDMI_I2C_TRANSACTION1 with the following fields set in
@@ -863,7 +643,7 @@ again:
 	 *    STOP1 = 0x1 (insert STOP bit)
 	 *    CNT1 = data_len   (it's 128 (0x80) for a blk read)
 	 */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_TRANS2,
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_TRANS2,
 		BIT(0) | BIT(12) | BIT(13) | (ddc_data->request_len << 16));
 
 	/* Trigger the I2C transfer */
@@ -877,13 +657,13 @@ again:
 	 *    GO = 0x1 (kicks off hardware)
 	 */
 	INIT_COMPLETION(ddc_ctrl->ddc_sw_done);
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(0) | BIT(21));
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(0) | BIT(21));
 
 	time_out_count = wait_for_completion_interruptible_timeout(
 		&ddc_ctrl->ddc_sw_done, HZ/2);
 
-	reg_val = HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_INT_CTRL);
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_INT_CTRL, reg_val & (~BIT(2)));
+	reg_val = DSS_REG_R(ddc_ctrl->io, HDMI_DDC_INT_CTRL);
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_INT_CTRL, reg_val & (~BIT(2)));
 	if (!time_out_count) {
 		if (ddc_data->retry-- > 0) {
 			DEV_INFO("%s: failed timout, retry=%d\n", __func__,
@@ -892,25 +672,25 @@ again:
 		}
 		status = -ETIMEDOUT;
 		DEV_ERR("%s: timedout(7), Int Ctrl=%08x\n", __func__,
-			HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_INT_CTRL));
+			DSS_REG_R(ddc_ctrl->io, HDMI_DDC_INT_CTRL));
 		DEV_ERR("%s: DDC SW Status=%08x, HW Status=%08x\n",
 			__func__,
-			HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_SW_STATUS),
-			HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_HW_STATUS));
+			DSS_REG_R(ddc_ctrl->io, HDMI_DDC_SW_STATUS),
+			DSS_REG_R(ddc_ctrl->io, HDMI_DDC_HW_STATUS));
 		goto error;
 	}
 
 	/* Read DDC status */
-	reg_val = HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_SW_STATUS);
+	reg_val = DSS_REG_R(ddc_ctrl->io, HDMI_DDC_SW_STATUS);
 	reg_val &= BIT(12) | BIT(13) | BIT(14) | BIT(15);
 
 	/* Check if any NACK occurred */
 	if (reg_val) {
 		/* SW_STATUS_RESET */
-		HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(3));
+		DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(3));
 		if (ddc_data->retry == 1)
 			/* SOFT_RESET */
-			HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(1));
+			DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(1));
 		if (ddc_data->retry-- > 0) {
 			DEV_DBG("%s(%s): failed NACK=0x%08x, retry=%d\n",
 				__func__, ddc_data->what, reg_val,
@@ -940,14 +720,14 @@ again:
 	 *    INDEX_WRITE = 0x1 (explicitly define offset)
 	 */
 	/* Write this data to DDC buffer */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA,
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA,
 		BIT(0) | (5 << 16) | BIT(31));
 
 	/* Discard first byte */
-	HDMI_REG_R_ND(ddc_ctrl->base, HDMI_DDC_DATA);
+	DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_DATA);
 
 	for (ndx = 0; ndx < ddc_data->data_len; ++ndx) {
-		reg_val = HDMI_REG_R_ND(ddc_ctrl->base, HDMI_DDC_DATA);
+		reg_val = DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_DATA);
 		ddc_data->data_buf[ndx] = (u8) ((reg_val & 0x0000FF00) >> 8);
 	}
 
@@ -964,7 +744,7 @@ int hdmi_ddc_write(struct hdmi_tx_ddc_ctrl *ddc_ctrl,
 	int status = 0, retry = 10;
 	u32 time_out_count;
 
-	if (!ddc_ctrl || !ddc_ctrl->base || !ddc_data) {
+	if (!ddc_ctrl || !ddc_ctrl->io || !ddc_data) {
 		DEV_ERR("%s: invalid input\n", __func__);
 		return -EINVAL;
 	}
@@ -991,7 +771,7 @@ again:
 	 *    INDEX = 0x0 (initial offset into buffer)
 	 *    INDEX_WRITE = 0x1 (setting initial offset)
 	 */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA,
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA,
 		BIT(31) | (ddc_data->dev_addr << 8));
 
 	/*
@@ -1002,7 +782,7 @@ again:
 	 *    INDEX = 0x0
 	 *    INDEX_WRITE = 0x0 (auto-increment by hardware)
 	 */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA, ddc_data->offset << 8);
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA, ddc_data->offset << 8);
 
 	/*
 	 * 3. Write to HDMI_I2C_DATA with the following fields set in order to
@@ -1013,7 +793,7 @@ again:
 	 *    INDEX_WRITE = 0x0 (auto-increment by hardware)
 	 */
 	for (ndx = 0; ndx < ddc_data->data_len; ++ndx)
-		HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA,
+		DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA,
 			((u32)ddc_data->data_buf[ndx]) << 8);
 
 	/* Data setup is complete, now setup the transaction characteristics */
@@ -1026,7 +806,7 @@ again:
 	 *    STOP0 = 0x0 (do NOT insert STOP bit)
 	 *    CNT0 = 0x1 (single byte transaction excluding address)
 	 */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_TRANS0, BIT(12) | BIT(16));
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_TRANS0, BIT(12) | BIT(16));
 
 	/*
 	 * 5. Write to HDMI_I2C_TRANSACTION1 with the following fields set in
@@ -1038,7 +818,7 @@ again:
 	 *    Byte count for second transition (excluding the first
 	 *    Byte which is usually the address)
 	 */
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_TRANS1,
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_TRANS1,
 		BIT(13) | ((ddc_data->data_len-1) << 16));
 
 	/* Trigger the I2C transfer */
@@ -1051,13 +831,13 @@ again:
 	 *    GO = 0x1 (kicks off hardware)
 	 */
 	INIT_COMPLETION(ddc_ctrl->ddc_sw_done);
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(0) | BIT(20));
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(0) | BIT(20));
 
 	time_out_count = wait_for_completion_interruptible_timeout(
 		&ddc_ctrl->ddc_sw_done, HZ/2);
 
-	reg_val = HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_INT_CTRL);
-	HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_INT_CTRL, reg_val & (~BIT(2)));
+	reg_val = DSS_REG_R(ddc_ctrl->io, HDMI_DDC_INT_CTRL);
+	DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_INT_CTRL, reg_val & (~BIT(2)));
 	if (!time_out_count) {
 		if (retry-- > 0) {
 			DEV_INFO("%s[%s]: failed timout, retry=%d\n", __func__,
@@ -1067,26 +847,26 @@ again:
 		status = -ETIMEDOUT;
 		DEV_ERR("%s[%s]: timedout, Int Ctrl=%08x\n",
 			__func__, ddc_data->what,
-			HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_INT_CTRL));
+			DSS_REG_R(ddc_ctrl->io, HDMI_DDC_INT_CTRL));
 		DEV_ERR("%s: DDC SW Status=%08x, HW Status=%08x\n",
 			__func__,
-			HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_SW_STATUS),
-			HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_HW_STATUS));
+			DSS_REG_R(ddc_ctrl->io, HDMI_DDC_SW_STATUS),
+			DSS_REG_R(ddc_ctrl->io, HDMI_DDC_HW_STATUS));
 		goto error;
 	}
 
 	/* Read DDC status */
-	reg_val = HDMI_REG_R_ND(ddc_ctrl->base, HDMI_DDC_SW_STATUS);
+	reg_val = DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_SW_STATUS);
 	reg_val &= 0x00001000 | 0x00002000 | 0x00004000 | 0x00008000;
 
 	/* Check if any NACK occurred */
 	if (reg_val) {
 		if (retry > 1)
 			/* SW_STATUS_RESET */
-			HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(3));
+			DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(3));
 		else
 			/* SOFT_RESET */
-			HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(1));
+			DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(1));
 
 		if (retry-- > 0) {
 			DEV_DBG("%s[%s]: failed NACK=%08x, retry=%d\n",
diff --git a/drivers/video/fbdev/msm/mdss_hdmi_util.h b/drivers/video/fbdev/msm/mdss_hdmi_util.h
index 6c788eca924a..e9e9ca48e323 100644
--- a/drivers/video/fbdev/msm/mdss_hdmi_util.h
+++ b/drivers/video/fbdev/msm/mdss_hdmi_util.h
@@ -12,6 +12,7 @@
 
 #ifndef __HDMI_UTIL_H__
 #define __HDMI_UTIL_H__
+#include "mdss_io_util.h"
 
 #define DEV_INFO(fmt, args...)	pr_info(fmt, ##args)
 #define DEV_WARN(fmt, args...)	pr_warn(fmt, ##args)
@@ -23,15 +24,7 @@
 #define DEV_DBG(args...)	(void)0
 #endif
 
-#define PORT_DEBUG 0
 #define REG_DUMP 0
-void hdmi_reg_w(void __iomem *addr, u32 offset, u32 value, u32 debug);
-u32 hdmi_reg_r(void __iomem *addr, u32 offset, u32 debug);
-
-#define HDMI_REG_W_ND(addr, offset, val)  hdmi_reg_w(addr, offset, val, false)
-#define HDMI_REG_W(addr, offset, val)     hdmi_reg_w(addr, offset, val, true)
-#define HDMI_REG_R_ND(addr, offset)       hdmi_reg_r(addr, offset, false)
-#define HDMI_REG_R(addr, offset)          hdmi_reg_r(addr, offset, true)
 
 /* HDMI_TX Registers */
 #define HDMI_CTRL                        (0x00000000)
@@ -220,7 +213,7 @@ u32 hdmi_reg_r(void __iomem *addr, u32 offset, u32 debug);
 #define HDMI_TPG_BLK_WHT_PATTERN_FRAMES  (0x00000358)
 #define HDMI_TPG_RGB_MAPPING             (0x0000035C)
 
-/* HDMI PHY Registers, use them with PHY base and _ND macro */
+/* HDMI PHY Registers */
 #define HDMI_PHY_ANA_CFG0                (0x00000000)
 #define HDMI_PHY_ANA_CFG1                (0x00000004)
 #define HDMI_PHY_PD_CTRL0                (0x00000010)
@@ -231,6 +224,10 @@ u32 hdmi_reg_r(void __iomem *addr, u32 offset, u32 debug);
 #define HDMI_PHY_BIST_PATN2              (0x00000044)
 #define HDMI_PHY_BIST_PATN3              (0x00000048)
 
+/* QFPROM Registers for HDMI/HDCP */
+#define QFPROM_RAW_FEAT_CONFIG_ROW0_LSB  (0x000000F8)
+#define QFPROM_RAW_FEAT_CONFIG_ROW0_MSB  (0x000000FC)
+
 /* all video formats defined by EIA CEA 861D */
 #define HDMI_VFRMT_640x480p60_4_3	0
 #define HDMI_VFRMT_720x480p60_4_3	1
@@ -397,7 +394,7 @@ struct hdmi_disp_mode_timing_type {
 };
 
 struct hdmi_tx_ddc_ctrl {
-	void __iomem *base;
+	struct dss_io_data *io;
 	struct completion ddc_sw_done;
 };
 
@@ -412,9 +409,6 @@ struct hdmi_tx_ddc_data {
 	int retry;
 };
 
-void hdmi_reg_dump(void __iomem *base, u32 length, const char *prefix);
-const char *hdmi_reg_name(u32 offset);
-
 const struct hdmi_disp_mode_timing_type *hdmi_get_supported_mode(u32 mode);
 void hdmi_set_supported_mode(u32 mode);
 const char *hdmi_get_video_fmt_2string(u32 format);
diff --git a/drivers/video/fbdev/msm/mdss_io_util.c b/drivers/video/fbdev/msm/mdss_io_util.c
index 4d06868c72a3..1ba2d21936e3 100644
--- a/drivers/video/fbdev/msm/mdss_io_util.c
+++ b/drivers/video/fbdev/msm/mdss_io_util.c
@@ -15,6 +15,56 @@
 #include <linux/regulator/consumer.h>
 #include "mdss_io_util.h"
 
+void dss_reg_w(struct dss_io_data *io, u32 offset, u32 value, u32 debug)
+{
+	u32 in_val;
+
+	if (!io || !io->base) {
+		pr_err("%s: invalid input\n", __func__);
+		return;
+	}
+
+	if (offset > io->len) {
+		pr_err("%s: offset out of range\n", __func__);
+		return;
+	}
+
+	writel_relaxed(value, io->base + offset);
+	if (debug) {
+		in_val = readl_relaxed(io->base + offset);
+		pr_debug("[%08x] => %08x [%08x]\n", (u32)(io->base + offset),
+			value, in_val);
+	}
+} /* dss_reg_w */
+
+u32 dss_reg_r(struct dss_io_data *io, u32 offset, u32 debug)
+{
+	u32 value;
+	if (!io || !io->base) {
+		pr_err("%s: invalid input\n", __func__);
+		return -EINVAL;
+	}
+
+	if (offset > io->len) {
+		pr_err("%s: offset out of range\n", __func__);
+		return -EINVAL;
+	}
+
+	value = readl_relaxed(io->base + offset);
+	if (debug)
+		pr_debug("[%08x] <= %08x\n", (u32)(io->base + offset), value);
+
+	return value;
+} /* dss_reg_r */
+
+void dss_reg_dump(void __iomem *base, u32 length, const char *prefix,
+	u32 debug)
+{
+	if (debug)
+		print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 32, 4,
+			(void *)base, length, false);
+} /* dss_reg_dump */
+
 static struct resource *msm_dss_get_res_byname(struct platform_device *pdev,
 	unsigned int type, const char *name)
 {
diff --git a/drivers/video/fbdev/msm/mdss_io_util.h b/drivers/video/fbdev/msm/mdss_io_util.h
index 9351bfca1612..20335455e54c 100644
--- a/drivers/video/fbdev/msm/mdss_io_util.h
+++ b/drivers/video/fbdev/msm/mdss_io_util.h
@@ -22,6 +22,15 @@ struct dss_io_data {
 	void __iomem *base;
 };
 
+void dss_reg_w(struct dss_io_data *io, u32 offset, u32 value, u32 debug);
+u32 dss_reg_r(struct dss_io_data *io, u32 offset, u32 debug);
+void dss_reg_dump(void __iomem *base, u32 len, const char *prefix, u32 debug);
+
+#define DSS_REG_W_ND(io, offset, val)  dss_reg_w(io, offset, val, false)
+#define DSS_REG_W(io, offset, val)     dss_reg_w(io, offset, val, true)
+#define DSS_REG_R_ND(io, offset)       dss_reg_r(io, offset, false)
+#define DSS_REG_R(io, offset)          dss_reg_r(io, offset, true)
+
 enum dss_vreg_type {
 	DSS_REG_LDO,
 	DSS_REG_VS,