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authorBaptiste Reynal <b.reynal@virtualopensystems.com>2015-03-04 16:51:06 +0100
committerDavid Keitel <dkeitel@codeaurora.org>2016-03-22 11:14:49 -0700
commit1805fabc3e76b80e2dcc73f78e70ee9b61406e9b (patch)
tree41a2588ee6f3841d206a936d74f7c0218de08a90
parentaaf63985193d717bba56d601a9521dbc412e0b50 (diff)
iommu/arm-smmu: fix ARM_SMMU_FEAT_TRANS_OPS condition
This patch is a fix to "iommu/arm-smmu: add support for iova_to_phys through ATS1PR". According to ARM documentation, translation registers are optional even in SMMUv1, so ID0_S1TS needs to be checked to verify their presence. Also, we check that the domain is a stage-1 domain. Change-Id: I2164ddb3806f941d21463731d0991ce1a83a5221 Signed-off-by: Baptiste Reynal <b.reynal@virtualopensystems.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
-rw-r--r--drivers/iommu/arm-smmu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 684a4311f560..6baa0f051584 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -3156,7 +3156,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
return -ENODEV;
}
- if (smmu->version == 1 || (!(id & ID0_ATOSNS) && (id & ID0_S1TS))) {
+ if ((id & ID0_S1TS) && ((smmu->version == 1) || (id & ID0_ATOSNS))) {
smmu->features |= ARM_SMMU_FEAT_TRANS_OPS;
dev_dbg(smmu->dev, "\taddress translation ops\n");
}