icnss: Remove hardware reset sequence

Remove WLAN hardware reset sequence from ICNSS platform as it
will be taken care by WLAN FW.

CRs-Fixed: 1089686
Change-Id: I363ee028eeb360ef998fd90c1ff94bb09c4ac8b4
Signed-off-by: Yuanyuan Liu <yuanliu@codeaurora.org>
Signed-off-by: Sarada Prasanna Garnayak <sgarna@codeaurora.org>

3 files changed, 1 insertions, 1095 deletions

diff --git a/Documentation/devicetree/bindings/cnss/icnss.txt b/Documentation/devicetree/bindings/cnss/icnss.txt
index e19a43446357..15feda3b7407 100644
--- a/Documentation/devicetree/bindings/cnss/icnss.txt
+++ b/Documentation/devicetree/bindings/cnss/icnss.txt
@@ -12,17 +12,9 @@ Required properties:
   - reg-names: Names of the memory regions defined in reg entry
   - interrupts: Copy engine interrupt table
   - qcom,wlan-msa-memory: MSA memory size
-  - clocks: List of clock phandles
-  - clock-names: List of clock names corresponding to the "clocks" property
   - iommus: SMMUs and corresponding Stream IDs needed by WLAN
   - qcom,wlan-smmu-iova-address: I/O virtual address range as <start length>
     format to be used for allocations associated between WLAN and SMMU
-  - <supply-name>-supply: phandle to the regulator device tree node
-                          Required "supply-name" is "vdd-0.8-cx-mx".
-  - qcom,<supply>-config - specifies voltage levels for supply. Should be
-                           specified in pairs (min, max), units uV.  There can
-                           be optional load in uA and Regulator settle delay in
-                           uS.
 
 Optional properties:
   - qcom,icnss-vadc: VADC handle for vph_pwr read APIs.
@@ -34,8 +26,6 @@ Example:
         compatible = "qcom,icnss";
         reg = <0x0a000000 0x1000000>;
         reg-names = "membase";
-        clocks = <&clock_gcc clk_aggre2_noc_clk>;
-        clock-names = "smmu_aggre2_noc_clk";
         iommus = <&anoc2_smmu 0x1900>,
                  <&anoc2_smmu 0x1901>;
         qcom,wlan-smmu-iova-address = <0 0x10000000>;
@@ -53,6 +43,4 @@ Example:
 		   <0 140 0 /* CE10 */ >,
 		   <0 141 0 /* CE11 */ >;
         qcom,wlan-msa-memory = <0x200000>;
-	vdd-0.8-cx-mx-supply = <&pm8998_l5>;
-	qcom,vdd-0.8-cx-mx-config = <800000 800000 2400 1000>;
     };
diff --git a/arch/arm/boot/dts/qcom/msm8998.dtsi b/arch/arm/boot/dts/qcom/msm8998.dtsi
index f570819fa70f..8ce9e7c22761 100644
--- a/arch/arm/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998.dtsi
@@ -2970,13 +2970,9 @@
 	 qcom,icnss@18800000 {
 		compatible = "qcom,icnss";
 		reg = <0x18800000 0x800000>,
-		      <0x10AC000 0x20>,
 		      <0xa0000000 0x10000000>,
 		      <0xb0000000 0x10000>;
-		reg-names = "membase", "mpm_config",
-			    "smmu_iova_base", "smmu_iova_ipa";
-		clocks = <&clock_gcc clk_rf_clk2_pin>;
-		clock-names = "cxo_ref_clk_pin";
+		reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa";
 		iommus = <&anoc2_smmu 0x1900>,
 			 <&anoc2_smmu 0x1901>;
 		interrupts = <0 413 0 /* CE0 */ >,
@@ -2992,12 +2988,6 @@
 			     <0 424 0 /* CE10 */ >,
 			     <0 425 0 /* CE11 */ >;
 		qcom,wlan-msa-memory = <0x100000>;
-		vdd-0.8-cx-mx-supply = <&pm8998_l5>;
-		vdd-1.8-xo-supply = <&pm8998_l7_pin_ctrl>;
-		vdd-1.3-rfa-supply = <&pm8998_l17_pin_ctrl>;
-		vdd-3.3-ch0-supply = <&pm8998_l25_pin_ctrl>;
-		qcom,vdd-0.8-cx-mx-config = <800000 800000>;
-		qcom,vdd-3.3-ch0-config = <3104000 3312000>;
 		qcom,icnss-vadc = <&pm8998_vadc>;
 		qcom,icnss-adc_tm = <&pm8998_adc_tm>;
 	};
diff --git a/drivers/soc/qcom/icnss.c b/drivers/soc/qcom/icnss.c
index 5f1064201b3a..49510bfd6b24 100644
--- a/drivers/soc/qcom/icnss.c
+++ b/drivers/soc/qcom/icnss.c
@@ -65,126 +65,6 @@ module_param(qmi_timeout, ulong, 0600);
 #define NUM_REG_LOG_PAGES		4
 #define ICNSS_MAGIC			0x5abc5abc
 
-/*
- * Registers: MPM2_PSHOLD
- * Base Address: 0x10AC000
- */
-#define MPM_WCSSAON_CONFIG_OFFSET				0x18
-#define MPM_WCSSAON_CONFIG_ARES_N				BIT(0)
-#define MPM_WCSSAON_CONFIG_WLAN_DISABLE				BIT(1)
-#define MPM_WCSSAON_CONFIG_MSM_CLAMP_EN_OVRD			BIT(6)
-#define MPM_WCSSAON_CONFIG_MSM_CLAMP_EN_OVRD_VAL		BIT(7)
-#define MPM_WCSSAON_CONFIG_FORCE_ACTIVE				BIT(14)
-#define MPM_WCSSAON_CONFIG_FORCE_XO_ENABLE			BIT(19)
-#define MPM_WCSSAON_CONFIG_DISCONNECT_CLR			BIT(21)
-#define MPM_WCSSAON_CONFIG_M2W_CLAMP_EN				BIT(22)
-
-/*
- * Registers: WCSS_SR_SHADOW_REGISTERS
- * Base Address: 0x18820000
- */
-#define SR_WCSSAON_SR_LSB_OFFSET				0x22070
-#define SR_WCSSAON_SR_LSB_RETENTION_STATUS			BIT(20)
-
-#define SR_PMM_SR_MSB						0x2206C
-#define SR_PMM_SR_MSB_AHB_CLOCK_MASK				GENMASK(26, 22)
-#define SR_PMM_SR_MSB_XO_CLOCK_MASK				GENMASK(31, 27)
-
-/*
- * Registers: WCSS_HM_A_WCSS_CLK_CTL_WCSS_CC_REG
- * Base Address: 0x189D0000
- */
-#define WCSS_WLAN1_GDSCR_OFFSET					0x1D3004
-#define WCSS_WLAN1_GDSCR_SW_COLLAPSE				BIT(0)
-#define WCSS_WLAN1_GDSCR_HW_CONTROL				BIT(1)
-#define WCSS_WLAN1_GDSCR_PWR_ON					BIT(31)
-
-#define WCSS_RFACTRL_GDSCR_OFFSET				0x1D60C8
-#define WCSS_RFACTRL_GDSCR_SW_COLLAPSE				BIT(0)
-#define WCSS_RFACTRL_GDSCR_HW_CONTROL				BIT(1)
-#define WCSS_RFACTRL_GDSCR_PWR_ON				BIT(31)
-
-#define WCSS_CLK_CTL_WCSS_CSS_GDSCR_OFFSET			0x1D1004
-#define WCSS_CLK_CTL_WCSS_CSS_GDSCR_SW_COLLAPSE			BIT(0)
-#define WCSS_CLK_CTL_WCSS_CSS_GDSCR_HW_CONTROL			BIT(1)
-#define WCSS_CLK_CTL_WCSS_CSS_GDSCR_PWR_ON			BIT(31)
-
-#define WCSS_CLK_CTL_NOC_CMD_RCGR_OFFSET			0x1D1030
-#define WCSS_CLK_CTL_NOC_CMD_RCGR_UPDATE			BIT(0)
-
-#define WCSS_CLK_CTL_NOC_CFG_RCGR_OFFSET			0x1D1034
-#define WCSS_CLK_CTL_NOC_CFG_RCGR_SRC_SEL			GENMASK(10, 8)
-
-#define WCSS_CLK_CTL_REF_CMD_RCGR_OFFSET			0x1D602C
-#define WCSS_CLK_CTL_REF_CMD_RCGR_UPDATE			BIT(0)
-
-#define WCSS_CLK_CTL_REF_CFG_RCGR_OFFSET			0x1D6030
-#define WCSS_CLK_CTL_REF_CFG_RCGR_SRC_SEL			GENMASK(10, 8)
-
-/*
- * Registers: WCSS_HM_A_WIFI_APB_3_A_WCMN_MAC_WCMN_REG
- * Base Address: 0x18AF0000
- */
-#define WCMN_PMM_WLAN1_CFG_REG1_OFFSET				0x2F0804
-#define WCMN_PMM_WLAN1_CFG_REG1_RFIF_ADC_PORDN_N		BIT(9)
-#define WCMN_PMM_WLAN1_CFG_REG1_ADC_DIGITAL_CLAMP		BIT(10)
-
-/*
- * Registers: WCSS_HM_A_PMM_PMM
- * Base Address: 0x18880000
- */
-#define WCSS_HM_A_PMM_ROOT_CLK_ENABLE				0x80010
-#define PMM_TCXO_CLK_ENABLE					BIT(13)
-
-#define PMM_COMMON_IDLEREQ_CSR_OFFSET				0x80120
-#define PMM_COMMON_IDLEREQ_CSR_SW_WNOC_IDLEREQ_SET		BIT(16)
-#define PMM_COMMON_IDLEREQ_CSR_WNOC_IDLEACK			BIT(26)
-#define PMM_COMMON_IDLEREQ_CSR_WNOC_IDLE			BIT(27)
-
-#define PMM_RFACTRL_IDLEREQ_CSR_OFFSET				0x80164
-#define PMM_RFACTRL_IDLEREQ_CSR_SW_RFACTRL_IDLEREQ_SET		BIT(16)
-#define PMM_RFACTRL_IDLEREQ_CSR_RFACTRL_IDLETACK		BIT(26)
-
-#define PMM_WSI_CMD_OFFSET					0x800E0
-#define PMM_WSI_CMD_USE_WLAN1_WSI				BIT(0)
-#define PMM_WSI_CMD_SW_USE_PMM_WSI				BIT(2)
-#define PMM_WSI_CMD_SW_BUS_SYNC					BIT(3)
-#define PMM_WSI_CMD_SW_RF_RESET					BIT(4)
-#define PMM_WSI_CMD_SW_REG_READ					BIT(5)
-#define PMM_WSI_CMD_SW_XO_DIS					BIT(8)
-#define PMM_WSI_CMD_SW_FORCE_IDLE				BIT(9)
-#define PMM_WSI_CMD_PMM_WSI_SM					GENMASK(24, 16)
-#define PMM_WSI_CMD_RF_CMD_IP					BIT(31)
-
-#define PMM_REG_RW_ADDR_OFFSET					0x800F0
-#define PMM_REG_RW_ADDR_SW_REG_RW_ADDR				GENMASK(15, 0)
-
-#define PMM_REG_READ_DATA_OFFSET				0x800F8
-
-#define PMM_RF_VAULT_REG_ADDR_OFFSET				0x800FC
-#define PMM_RF_VAULT_REG_ADDR_RF_VAULT_REG_ADDR			GENMASK(15, 0)
-
-#define PMM_RF_VAULT_REG_DATA_OFFSET				0x80100
-#define PMM_RF_VAULT_REG_DATA_RF_VAULT_REG_DATA			GENMASK(31, 0)
-
-#define PMM_XO_DIS_ADDR_OFFSET					0x800E8
-#define PMM_XO_DIS_ADDR_XO_DIS_ADDR				GENMASK(15, 0)
-
-#define PMM_XO_DIS_DATA_OFFSET					0x800EC
-#define PMM_XO_DIS_DATA_XO_DIS_DATA				GENMASK(31, 0)
-
-#define PMM_RF_RESET_ADDR_OFFSET				0x80104
-#define PMM_RF_RESET_ADDR_RF_RESET_ADDR				GENMASK(15, 0)
-
-#define PMM_RF_RESET_DATA_OFFSET				0x80108
-#define PMM_RF_RESET_DATA_RF_RESET_DATA				GENMASK(31, 0)
-
-#define ICNSS_HW_REG_RETRY					10
-
-#define WCSS_HM_A_PMM_HW_VERSION_V10				0x40000000
-#define WCSS_HM_A_PMM_HW_VERSION_V20				0x40010000
-#define WCSS_HM_A_PMM_HW_VERSION_Q10				0x40010001
-
 #define ICNSS_SERVICE_LOCATION_CLIENT_NAME			"ICNSS-WLAN"
 #define ICNSS_WLAN_SERVICE_NAME					"wlan/fw"
 
@@ -326,38 +206,6 @@ struct ce_irq_list {
 	irqreturn_t (*handler)(int, void *);
 };
 
-struct icnss_vreg_info {
-	struct regulator *reg;
-	const char *name;
-	u32 min_v;
-	u32 max_v;
-	u32 load_ua;
-	unsigned long settle_delay;
-	bool required;
-};
-
-struct icnss_clk_info {
-	struct clk *handle;
-	const char *name;
-	u32 freq;
-	bool required;
-};
-
-static struct icnss_vreg_info icnss_vreg_info[] = {
-	{NULL, "vdd-0.8-cx-mx", 800000, 800000, 0, 0, true},
-	{NULL, "vdd-1.8-xo", 1800000, 1800000, 0, 0, false},
-	{NULL, "vdd-1.3-rfa", 1304000, 1304000, 0, 0, false},
-	{NULL, "vdd-3.3-ch0", 3312000, 3312000, 0, 0, false},
-};
-
-#define ICNSS_VREG_INFO_SIZE		ARRAY_SIZE(icnss_vreg_info)
-
-static struct icnss_clk_info icnss_clk_info[] = {
-	{NULL, "cxo_ref_clk_pin", 0, false},
-};
-
-#define ICNSS_CLK_INFO_SIZE		ARRAY_SIZE(icnss_clk_info)
-
 struct icnss_stats {
 	struct {
 		uint32_t posted;
@@ -421,13 +269,9 @@ static struct icnss_priv {
 	struct platform_device *pdev;
 	struct icnss_driver_ops *ops;
 	struct ce_irq_list ce_irq_list[ICNSS_MAX_IRQ_REGISTRATIONS];
-	struct icnss_vreg_info vreg_info[ICNSS_VREG_INFO_SIZE];
-	struct icnss_clk_info clk_info[ICNSS_CLK_INFO_SIZE];
 	u32 ce_irqs[ICNSS_MAX_IRQ_REGISTRATIONS];
 	phys_addr_t mem_base_pa;
 	void __iomem *mem_base_va;
-	phys_addr_t mpm_config_pa;
-	void __iomem *mpm_config_va;
 	struct dma_iommu_mapping *smmu_mapping;
 	dma_addr_t smmu_iova_start;
 	size_t smmu_iova_len;
@@ -477,71 +321,6 @@ static struct icnss_priv {
 	struct icnss_wlan_mac_addr wlan_mac_addr;
 } *penv;
 
-static void icnss_hw_write_reg(void *base, u32 offset, u32 val)
-{
-	writel_relaxed(val, base + offset);
-	wmb(); /* Ensure data is written to hardware register */
-}
-
-static u32 icnss_hw_read_reg(void *base, u32 offset)
-{
-	u32 rdata = readl_relaxed(base + offset);
-
-	icnss_reg_dbg(" READ: offset: 0x%06x 0x%08x\n", offset, rdata);
-
-	return rdata;
-}
-
-static void icnss_hw_write_reg_field(void *base, u32 offset, u32 mask, u32 val)
-{
-	u32 shift = find_first_bit((void *)&mask, 32);
-	u32 rdata = readl_relaxed(base + offset);
-
-	val = (rdata & ~mask) | (val << shift);
-
-	icnss_reg_dbg("WRITE: offset: 0x%06x 0x%08x -> 0x%08x\n",
-		     offset, rdata, val);
-
-	icnss_hw_write_reg(base, offset, val);
-}
-
-static int icnss_hw_poll_reg_field(void *base, u32 offset, u32 mask, u32 val,
-				    unsigned long usecs, int retry)
-{
-	u32 shift;
-	u32 rdata;
-	int r = 0;
-
-	shift = find_first_bit((void *)&mask, 32);
-
-	val = val << shift;
-
-	rdata  = readl_relaxed(base + offset);
-
-	icnss_reg_dbg(" POLL: offset: 0x%06x 0x%08x == 0x%08x & 0x%08x\n",
-		     offset, val, rdata, mask);
-
-	while ((rdata & mask) != val) {
-		if (retry != 0 && r >= retry) {
-			icnss_pr_err("POLL FAILED: offset: 0x%06x 0x%08x == 0x%08x & 0x%08x\n",
-				     offset, val, rdata, mask);
-
-			return -EIO;
-		}
-
-		r++;
-		udelay(usecs);
-		rdata = readl_relaxed(base + offset);
-
-		if (retry)
-			icnss_reg_dbg(" POLL: offset: 0x%06x 0x%08x == 0x%08x & 0x%08x\n",
-					 offset, val, rdata, mask);
-
-	}
-
-	return 0;
-}
-
 static void icnss_pm_stay_awake(struct icnss_priv *priv)
 {
 	if (atomic_inc_return(&priv->pm_count) != 1)
@@ -886,683 +665,6 @@ out:
 	return ret;
 }
 
-static int icnss_vreg_on(struct icnss_priv *priv)
-{
-	int ret = 0;
-	struct icnss_vreg_info *vreg_info;
-	int i;
-
-	for (i = 0; i < ICNSS_VREG_INFO_SIZE; i++) {
-		vreg_info = &priv->vreg_info[i];
-
-		if (!vreg_info->reg)
-			continue;
-
-		icnss_pr_dbg("Regulator %s being enabled\n", vreg_info->name);
-
-		ret = regulator_set_voltage(vreg_info->reg, vreg_info->min_v,
-					    vreg_info->max_v);
-
-		if (ret) {
-			icnss_pr_err("Regulator %s, can't set voltage: min_v: %u, max_v: %u, ret: %d\n",
-				     vreg_info->name, vreg_info->min_v,
-				     vreg_info->max_v, ret);
-			break;
-		}
-
-		if (vreg_info->load_ua) {
-			ret = regulator_set_load(vreg_info->reg,
-						 vreg_info->load_ua);
-
-			if (ret < 0) {
-				icnss_pr_err("Regulator %s, can't set load: %u, ret: %d\n",
-					     vreg_info->name,
-					     vreg_info->load_ua, ret);
-				break;
-			}
-		}
-
-		ret = regulator_enable(vreg_info->reg);
-		if (ret) {
-			icnss_pr_err("Regulator %s, can't enable: %d\n",
-				     vreg_info->name, ret);
-			break;
-		}
-
-		if (vreg_info->settle_delay)
-			udelay(vreg_info->settle_delay);
-	}
-
-	if (!ret)
-		return 0;
-
-	for (; i >= 0; i--) {
-		vreg_info = &priv->vreg_info[i];
-
-		if (!vreg_info->reg)
-			continue;
-
-		regulator_disable(vreg_info->reg);
-
-		regulator_set_load(vreg_info->reg, 0);
-
-		regulator_set_voltage(vreg_info->reg, 0, vreg_info->max_v);
-	}
-
-	return ret;
-}
-
-static int icnss_vreg_off(struct icnss_priv *priv)
-{
-	int ret = 0;
-	struct icnss_vreg_info *vreg_info;
-	int i;
-
-	for (i = ICNSS_VREG_INFO_SIZE - 1; i >= 0; i--) {
-		vreg_info = &priv->vreg_info[i];
-
-		if (!vreg_info->reg)
-			continue;
-
-		icnss_pr_dbg("Regulator %s being disabled\n", vreg_info->name);
-
-		ret = regulator_disable(vreg_info->reg);
-		if (ret)
-			icnss_pr_err("Regulator %s, can't disable: %d\n",
-				     vreg_info->name, ret);
-
-		ret = regulator_set_load(vreg_info->reg, 0);
-		if (ret < 0)
-			icnss_pr_err("Regulator %s, can't set load: %d\n",
-				     vreg_info->name, ret);
-
-		ret = regulator_set_voltage(vreg_info->reg, 0,
-					    vreg_info->max_v);
-
-		if (ret)
-			icnss_pr_err("Regulator %s, can't set voltage: %d\n",
-				     vreg_info->name, ret);
-	}
-
-	return ret;
-}
-
-static int icnss_clk_init(struct icnss_priv *priv)
-{
-	struct icnss_clk_info *clk_info;
-	int i;
-	int ret = 0;
-
-	for (i = 0; i < ICNSS_CLK_INFO_SIZE; i++) {
-		clk_info = &priv->clk_info[i];
-
-		if (!clk_info->handle)
-			continue;
-
-		icnss_pr_dbg("Clock %s being enabled\n", clk_info->name);
-
-		if (clk_info->freq) {
-			ret = clk_set_rate(clk_info->handle, clk_info->freq);
-
-			if (ret) {
-				icnss_pr_err("Clock %s, can't set frequency: %u, ret: %d\n",
-					     clk_info->name, clk_info->freq,
-					     ret);
-				break;
-			}
-		}
-
-		ret = clk_prepare_enable(clk_info->handle);
-
-		if (ret) {
-			icnss_pr_err("Clock %s, can't enable: %d\n",
-				     clk_info->name, ret);
-			break;
-		}
-	}
-
-	if (ret == 0)
-		return 0;
-
-	for (; i >= 0; i--) {
-		clk_info = &priv->clk_info[i];
-
-		if (!clk_info->handle)
-			continue;
-
-		clk_disable_unprepare(clk_info->handle);
-	}
-
-	return ret;
-}
-
-static int icnss_clk_deinit(struct icnss_priv *priv)
-{
-	struct icnss_clk_info *clk_info;
-	int i;
-
-	for (i = 0; i < ICNSS_CLK_INFO_SIZE; i++) {
-		clk_info = &priv->clk_info[i];
-
-		if (!clk_info->handle)
-			continue;
-
-		icnss_pr_dbg("Clock %s being disabled\n", clk_info->name);
-
-		clk_disable_unprepare(clk_info->handle);
-	}
-
-	return 0;
-}
-
-static void icnss_hw_top_level_release_reset(struct icnss_priv *priv)
-{
-	icnss_pr_dbg("RESET: HW Release reset: state: 0x%lx\n", priv->state);
-
-	icnss_hw_write_reg_field(priv->mpm_config_va, MPM_WCSSAON_CONFIG_OFFSET,
-				 MPM_WCSSAON_CONFIG_ARES_N, 1);
-
-	icnss_hw_write_reg_field(priv->mpm_config_va, MPM_WCSSAON_CONFIG_OFFSET,
-				 MPM_WCSSAON_CONFIG_WLAN_DISABLE, 0x0);
-
-	icnss_hw_poll_reg_field(priv->mpm_config_va,
-				MPM_WCSSAON_CONFIG_OFFSET,
-				MPM_WCSSAON_CONFIG_ARES_N, 1, 10,
-				ICNSS_HW_REG_RETRY);
-}
-
-static void icnss_hw_top_level_reset(struct icnss_priv *priv)
-{
-	icnss_pr_dbg("RESET: HW top level reset: state: 0x%lx\n", priv->state);
-
-	icnss_hw_write_reg_field(priv->mpm_config_va,
-				 MPM_WCSSAON_CONFIG_OFFSET,
-				 MPM_WCSSAON_CONFIG_ARES_N, 0);
-
-	icnss_hw_poll_reg_field(priv->mpm_config_va,
-				MPM_WCSSAON_CONFIG_OFFSET,
-				MPM_WCSSAON_CONFIG_ARES_N, 0, 10,
-				ICNSS_HW_REG_RETRY);
-}
-
-static void icnss_hw_io_reset(struct icnss_priv *priv, bool on)
-{
-	u32 hw_version = priv->soc_info.soc_id;
-
-	if (on && !test_bit(ICNSS_FW_READY, &priv->state))
-		return;
-
-	icnss_pr_dbg("HW io reset: %s, SoC: 0x%x, state: 0x%lx\n",
-		     on ? "ON" : "OFF", priv->soc_info.soc_id, priv->state);
-
-	if (hw_version == WCSS_HM_A_PMM_HW_VERSION_V10 ||
-	    hw_version == WCSS_HM_A_PMM_HW_VERSION_V20) {
-		icnss_hw_write_reg_field(priv->mpm_config_va,
-				MPM_WCSSAON_CONFIG_OFFSET,
-				MPM_WCSSAON_CONFIG_MSM_CLAMP_EN_OVRD_VAL, 0);
-		icnss_hw_write_reg_field(priv->mpm_config_va,
-				MPM_WCSSAON_CONFIG_OFFSET,
-				MPM_WCSSAON_CONFIG_MSM_CLAMP_EN_OVRD, on);
-	} else if (hw_version == WCSS_HM_A_PMM_HW_VERSION_Q10) {
-		icnss_hw_write_reg_field(priv->mpm_config_va,
-				MPM_WCSSAON_CONFIG_OFFSET,
-				MPM_WCSSAON_CONFIG_M2W_CLAMP_EN,
-				on);
-	}
-}
-
-static int icnss_hw_reset_wlan_ss_power_down(struct icnss_priv *priv)
-{
-	u32 rdata;
-
-	icnss_pr_dbg("RESET: WLAN SS power down, state: 0x%lx\n", priv->state);
-
-	rdata = icnss_hw_read_reg(priv->mem_base_va, WCSS_WLAN1_GDSCR_OFFSET);
-
-	if ((rdata & WCSS_WLAN1_GDSCR_PWR_ON) == 0)
-		return 0;
-
-	icnss_hw_write_reg_field(priv->mem_base_va, WCSS_WLAN1_GDSCR_OFFSET,
-				 WCSS_WLAN1_GDSCR_HW_CONTROL, 0);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, WCSS_WLAN1_GDSCR_OFFSET,
-				 WCSS_WLAN1_GDSCR_SW_COLLAPSE, 1);
-
-	icnss_hw_poll_reg_field(priv->mem_base_va, WCSS_WLAN1_GDSCR_OFFSET,
-				WCSS_WLAN1_GDSCR_PWR_ON, 0, 10,
-				ICNSS_HW_REG_RETRY);
-
-	icnss_hw_write_reg_field(priv->mem_base_va,
-				 WCMN_PMM_WLAN1_CFG_REG1_OFFSET,
-				 WCMN_PMM_WLAN1_CFG_REG1_ADC_DIGITAL_CLAMP, 1);
-
-	icnss_hw_write_reg_field(priv->mem_base_va,
-				 WCMN_PMM_WLAN1_CFG_REG1_OFFSET,
-				 WCMN_PMM_WLAN1_CFG_REG1_RFIF_ADC_PORDN_N, 0);
-
-	return 0;
-}
-
-static int icnss_hw_reset_common_ss_power_down(struct icnss_priv *priv)
-{
-	u32 rdata;
-
-	icnss_pr_dbg("RESET: Common SS power down, state: 0x%lx\n",
-		     priv->state);
-
-	rdata = icnss_hw_read_reg(priv->mem_base_va,
-				  WCSS_CLK_CTL_WCSS_CSS_GDSCR_OFFSET);
-
-	if ((rdata & WCSS_CLK_CTL_WCSS_CSS_GDSCR_PWR_ON) == 0)
-		return 0;
-
-	icnss_hw_write_reg_field(priv->mem_base_va,
-				 PMM_COMMON_IDLEREQ_CSR_OFFSET,
-				 PMM_COMMON_IDLEREQ_CSR_SW_WNOC_IDLEREQ_SET,
-				 1);
-
-	icnss_hw_poll_reg_field(priv->mem_base_va,
-				PMM_COMMON_IDLEREQ_CSR_OFFSET,
-				PMM_COMMON_IDLEREQ_CSR_WNOC_IDLEACK,
-				1, 20, ICNSS_HW_REG_RETRY);
-
-	icnss_hw_poll_reg_field(priv->mem_base_va,
-				PMM_COMMON_IDLEREQ_CSR_OFFSET,
-				PMM_COMMON_IDLEREQ_CSR_WNOC_IDLE,
-				1, 10, ICNSS_HW_REG_RETRY);
-
-	icnss_hw_write_reg_field(priv->mem_base_va,
-				 WCSS_CLK_CTL_WCSS_CSS_GDSCR_OFFSET,
-				 WCSS_CLK_CTL_WCSS_CSS_GDSCR_HW_CONTROL, 0);
-
-	icnss_hw_write_reg_field(priv->mem_base_va,
-				 WCSS_CLK_CTL_WCSS_CSS_GDSCR_OFFSET,
-				 WCSS_CLK_CTL_WCSS_CSS_GDSCR_SW_COLLAPSE, 1);
-
-	icnss_hw_poll_reg_field(priv->mem_base_va,
-				WCSS_CLK_CTL_WCSS_CSS_GDSCR_OFFSET,
-				WCSS_CLK_CTL_WCSS_CSS_GDSCR_PWR_ON, 0, 10,
-				ICNSS_HW_REG_RETRY);
-
-	return 0;
-
-}
-
-static int icnss_hw_reset_wlan_rfactrl_power_down(struct icnss_priv *priv)
-{
-	u32 rdata;
-
-	icnss_pr_dbg("RESET: RFACTRL power down, state: 0x%lx\n", priv->state);
-
-	rdata = icnss_hw_read_reg(priv->mem_base_va, WCSS_RFACTRL_GDSCR_OFFSET);
-
-	if ((rdata & WCSS_RFACTRL_GDSCR_PWR_ON) == 0)
-		return 0;
-
-	icnss_hw_write_reg_field(priv->mem_base_va,
-				 PMM_RFACTRL_IDLEREQ_CSR_OFFSET,
-				 PMM_RFACTRL_IDLEREQ_CSR_SW_RFACTRL_IDLEREQ_SET,
-				 1);
-
-	icnss_hw_poll_reg_field(priv->mem_base_va,
-				PMM_RFACTRL_IDLEREQ_CSR_OFFSET,
-				PMM_RFACTRL_IDLEREQ_CSR_RFACTRL_IDLETACK,
-				1, 10, ICNSS_HW_REG_RETRY);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, WCSS_RFACTRL_GDSCR_OFFSET,
-				 WCSS_RFACTRL_GDSCR_HW_CONTROL, 0);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, WCSS_RFACTRL_GDSCR_OFFSET,
-				 WCSS_RFACTRL_GDSCR_SW_COLLAPSE, 1);
-
-	return 0;
-}
-
-static void icnss_hw_wsi_cmd_error_recovery(struct icnss_priv *priv)
-{
-	icnss_pr_dbg("RESET: WSI CMD Error recovery, state: 0x%lx\n",
-		     priv->state);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				 PMM_WSI_CMD_SW_FORCE_IDLE, 1);
-
-	icnss_hw_poll_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				PMM_WSI_CMD_PMM_WSI_SM, 1, 100, 0);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				 PMM_WSI_CMD_SW_FORCE_IDLE, 0);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				 PMM_WSI_CMD_SW_BUS_SYNC, 1);
-
-	icnss_hw_poll_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				PMM_WSI_CMD_RF_CMD_IP, 0, 100, 0);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				 PMM_WSI_CMD_SW_BUS_SYNC, 0);
-}
-
-static u32 icnss_hw_rf_register_read_command(struct icnss_priv *priv, u32 addr)
-{
-	u32 rdata = 0;
-	int ret;
-	int i;
-
-	icnss_pr_dbg("RF register read command, addr: 0x%04x, state: 0x%lx\n",
-		     addr, priv->state);
-
-	for (i = 0; i < ICNSS_HW_REG_RETRY; i++) {
-		icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-					 PMM_WSI_CMD_USE_WLAN1_WSI, 1);
-
-		icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-					 PMM_WSI_CMD_SW_USE_PMM_WSI, 1);
-
-		icnss_hw_write_reg_field(priv->mem_base_va,
-					 PMM_REG_RW_ADDR_OFFSET,
-					 PMM_REG_RW_ADDR_SW_REG_RW_ADDR,
-					 addr & 0xFFFF);
-
-		icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-					 PMM_WSI_CMD_SW_REG_READ, 1);
-
-		ret = icnss_hw_poll_reg_field(priv->mem_base_va,
-					      PMM_WSI_CMD_OFFSET,
-					      PMM_WSI_CMD_RF_CMD_IP, 0, 10,
-					      ICNSS_HW_REG_RETRY);
-		if (ret == 0)
-			break;
-
-		icnss_hw_wsi_cmd_error_recovery(priv);
-	}
-
-
-	rdata = icnss_hw_read_reg(priv->mem_base_va, PMM_REG_READ_DATA_OFFSET);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				 PMM_WSI_CMD_SW_USE_PMM_WSI, 0);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				 PMM_WSI_CMD_SW_REG_READ, 0);
-
-	icnss_pr_dbg("RF register read command, data: 0x%08x, state: 0x%lx\n",
-		     rdata, priv->state);
-
-	return rdata;
-}
-
-static int icnss_hw_reset_rf_reset_cmd(struct icnss_priv *priv)
-{
-	u32 rdata;
-	int ret;
-
-	icnss_pr_dbg("RESET: RF reset command, state: 0x%lx\n", priv->state);
-
-	rdata = icnss_hw_rf_register_read_command(priv, 0x5080);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				 PMM_WSI_CMD_USE_WLAN1_WSI, 1);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				 PMM_WSI_CMD_SW_USE_PMM_WSI, 1);
-
-	icnss_hw_write_reg_field(priv->mem_base_va,
-				 PMM_RF_VAULT_REG_ADDR_OFFSET,
-				 PMM_RF_VAULT_REG_ADDR_RF_VAULT_REG_ADDR,
-				 0x5082);
-
-	icnss_hw_write_reg_field(priv->mem_base_va,
-				 PMM_RF_VAULT_REG_DATA_OFFSET,
-				 PMM_RF_VAULT_REG_DATA_RF_VAULT_REG_DATA,
-				 0x12AB8FAD);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_RF_RESET_ADDR_OFFSET,
-				 PMM_RF_RESET_ADDR_RF_RESET_ADDR, 0x5080);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_RF_RESET_DATA_OFFSET,
-				 PMM_RF_RESET_DATA_RF_RESET_DATA,
-				 rdata & 0xBFFF);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				 PMM_WSI_CMD_SW_RF_RESET, 1);
-
-	ret = icnss_hw_poll_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				      PMM_WSI_CMD_RF_CMD_IP, 0, 10,
-				      ICNSS_HW_REG_RETRY);
-
-	if (ret) {
-		icnss_pr_err("RESET: RF reset command failed, state: 0x%lx\n",
-			     priv->state);
-		return ret;
-	}
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				 PMM_WSI_CMD_SW_USE_PMM_WSI, 0);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				 PMM_WSI_CMD_SW_RF_RESET, 0);
-
-	return 0;
-}
-
-static int icnss_hw_reset_switch_to_cxo(struct icnss_priv *priv)
-{
-	u32 rdata;
-
-	icnss_pr_dbg("RESET: Switch to CXO, state: 0x%lx\n", priv->state);
-
-	rdata = icnss_hw_read_reg(priv->mem_base_va,
-				  WCSS_HM_A_PMM_ROOT_CLK_ENABLE);
-
-	icnss_pr_dbg("RESET: PMM_TCXO_CLK_ENABLE : 0x%05lx\n",
-		     rdata & PMM_TCXO_CLK_ENABLE);
-
-	if ((rdata & PMM_TCXO_CLK_ENABLE) == 0) {
-		icnss_pr_dbg("RESET: Set PMM_TCXO_CLK_ENABLE to 1\n");
-
-		icnss_hw_write_reg_field(priv->mem_base_va,
-					 WCSS_HM_A_PMM_ROOT_CLK_ENABLE,
-					 PMM_TCXO_CLK_ENABLE, 1);
-		icnss_hw_poll_reg_field(priv->mem_base_va,
-					WCSS_HM_A_PMM_ROOT_CLK_ENABLE,
-					PMM_TCXO_CLK_ENABLE, 1, 10,
-					ICNSS_HW_REG_RETRY);
-	}
-
-	icnss_hw_write_reg_field(priv->mem_base_va,
-				 WCSS_CLK_CTL_NOC_CFG_RCGR_OFFSET,
-				 WCSS_CLK_CTL_NOC_CFG_RCGR_SRC_SEL, 0);
-
-	icnss_hw_write_reg_field(priv->mem_base_va,
-				 WCSS_CLK_CTL_NOC_CMD_RCGR_OFFSET,
-				 WCSS_CLK_CTL_NOC_CMD_RCGR_UPDATE, 1);
-
-	icnss_hw_write_reg_field(priv->mem_base_va,
-				 WCSS_CLK_CTL_REF_CFG_RCGR_OFFSET,
-				 WCSS_CLK_CTL_REF_CFG_RCGR_SRC_SEL, 0);
-
-	icnss_hw_write_reg_field(priv->mem_base_va,
-				 WCSS_CLK_CTL_REF_CMD_RCGR_OFFSET,
-				 WCSS_CLK_CTL_REF_CMD_RCGR_UPDATE, 1);
-
-	return 0;
-}
-
-static int icnss_hw_reset_xo_disable_cmd(struct icnss_priv *priv)
-{
-	int ret;
-
-	icnss_pr_dbg("RESET: XO disable command, state: 0x%lx\n", priv->state);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				 PMM_WSI_CMD_USE_WLAN1_WSI, 1);
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				 PMM_WSI_CMD_SW_USE_PMM_WSI, 1);
-
-	icnss_hw_write_reg_field(priv->mem_base_va,
-				 PMM_RF_VAULT_REG_ADDR_OFFSET,
-				 PMM_RF_VAULT_REG_ADDR_RF_VAULT_REG_ADDR,
-				 0x5082);
-
-	icnss_hw_write_reg_field(priv->mem_base_va,
-				 PMM_RF_VAULT_REG_DATA_OFFSET,
-				 PMM_RF_VAULT_REG_DATA_RF_VAULT_REG_DATA,
-				 0x12AB8FAD);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_XO_DIS_ADDR_OFFSET,
-				 PMM_XO_DIS_ADDR_XO_DIS_ADDR, 0x5081);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_XO_DIS_DATA_OFFSET,
-				 PMM_XO_DIS_DATA_XO_DIS_DATA, 1);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				 PMM_WSI_CMD_SW_XO_DIS, 1);
-
-	ret = icnss_hw_poll_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				      PMM_WSI_CMD_RF_CMD_IP, 0, 10,
-				      ICNSS_HW_REG_RETRY);
-	if (ret) {
-		icnss_pr_err("RESET: XO disable command failed, state: 0x%lx\n",
-			     priv->state);
-		return ret;
-	}
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				 PMM_WSI_CMD_SW_USE_PMM_WSI, 0);
-
-	icnss_hw_write_reg_field(priv->mem_base_va, PMM_WSI_CMD_OFFSET,
-				 PMM_WSI_CMD_SW_XO_DIS, 0);
-
-	return 0;
-}
-
-static int icnss_hw_reset(struct icnss_priv *priv)
-{
-	u32 rdata;
-	u32 rdata1;
-	int i;
-	int ret = 0;
-
-	if (test_bit(HW_ONLY_TOP_LEVEL_RESET, &quirks))
-		goto top_level_reset;
-
-	icnss_pr_dbg("RESET: START, state: 0x%lx\n", priv->state);
-
-	icnss_hw_write_reg_field(priv->mpm_config_va, MPM_WCSSAON_CONFIG_OFFSET,
-				 MPM_WCSSAON_CONFIG_FORCE_ACTIVE, 1);
-
-	icnss_hw_poll_reg_field(priv->mem_base_va, SR_WCSSAON_SR_LSB_OFFSET,
-				SR_WCSSAON_SR_LSB_RETENTION_STATUS, 1, 200,
-				ICNSS_HW_REG_RETRY);
-
-	for (i = 0; i < ICNSS_HW_REG_RETRY; i++) {
-		rdata = icnss_hw_read_reg(priv->mem_base_va, SR_PMM_SR_MSB);
-		udelay(10);
-		rdata1 = icnss_hw_read_reg(priv->mem_base_va, SR_PMM_SR_MSB);
-
-		icnss_pr_dbg("RESET: XO: 0x%05lx/0x%05lx, AHB: 0x%05lx/0x%05lx\n",
-			     rdata & SR_PMM_SR_MSB_XO_CLOCK_MASK,
-			     rdata1 & SR_PMM_SR_MSB_XO_CLOCK_MASK,
-			     rdata & SR_PMM_SR_MSB_AHB_CLOCK_MASK,
-			     rdata1 & SR_PMM_SR_MSB_AHB_CLOCK_MASK);
-
-		if ((rdata & SR_PMM_SR_MSB_AHB_CLOCK_MASK) !=
-		    (rdata1 & SR_PMM_SR_MSB_AHB_CLOCK_MASK) &&
-		    (rdata & SR_PMM_SR_MSB_XO_CLOCK_MASK) !=
-		    (rdata1 & SR_PMM_SR_MSB_XO_CLOCK_MASK))
-			break;
-
-		icnss_hw_write_reg_field(priv->mpm_config_va,
-					 MPM_WCSSAON_CONFIG_OFFSET,
-					 MPM_WCSSAON_CONFIG_FORCE_XO_ENABLE,
-					 0x1);
-		usleep_range(2000, 3000);
-	}
-
-	if (i >= ICNSS_HW_REG_RETRY)
-		goto top_level_reset;
-
-	icnss_hw_write_reg_field(priv->mpm_config_va, MPM_WCSSAON_CONFIG_OFFSET,
-				 MPM_WCSSAON_CONFIG_DISCONNECT_CLR, 0x1);
-
-	usleep_range(200, 300);
-
-	icnss_hw_reset_wlan_ss_power_down(priv);
-
-	icnss_hw_reset_common_ss_power_down(priv);
-
-	icnss_hw_reset_wlan_rfactrl_power_down(priv);
-
-	ret = icnss_hw_reset_rf_reset_cmd(priv);
-	if (ret) {
-		icnss_hw_write_reg_field(priv->mpm_config_va,
-					 MPM_WCSSAON_CONFIG_OFFSET,
-					 MPM_WCSSAON_CONFIG_FORCE_ACTIVE, 0);
-		icnss_hw_write_reg_field(priv->mpm_config_va,
-					 MPM_WCSSAON_CONFIG_OFFSET,
-					 MPM_WCSSAON_CONFIG_DISCONNECT_CLR, 0);
-		icnss_hw_write_reg_field(priv->mpm_config_va,
-					 MPM_WCSSAON_CONFIG_OFFSET,
-					 MPM_WCSSAON_CONFIG_WLAN_DISABLE, 1);
-		goto top_level_reset;
-	}
-
-	icnss_hw_reset_switch_to_cxo(priv);
-
-	for (i = 0; i < ICNSS_HW_REG_RETRY; i++) {
-		rdata = icnss_hw_read_reg(priv->mem_base_va, SR_PMM_SR_MSB);
-		usleep_range(5, 10);
-		rdata1 = icnss_hw_read_reg(priv->mem_base_va, SR_PMM_SR_MSB);
-
-		icnss_pr_dbg("RESET: SR_PMM_SR_MSB: 0x%08x/0x%08x, XO: 0x%05lx/0x%05lx, AHB: 0x%05lx/0x%05lx\n",
-			     rdata, rdata1,
-			     rdata & SR_PMM_SR_MSB_XO_CLOCK_MASK,
-			     rdata1 & SR_PMM_SR_MSB_XO_CLOCK_MASK,
-			     rdata & SR_PMM_SR_MSB_AHB_CLOCK_MASK,
-			     rdata1 & SR_PMM_SR_MSB_AHB_CLOCK_MASK);
-
-		if ((rdata & SR_PMM_SR_MSB_AHB_CLOCK_MASK) !=
-		    (rdata1 & SR_PMM_SR_MSB_AHB_CLOCK_MASK) &&
-		    (rdata & SR_PMM_SR_MSB_XO_CLOCK_MASK) !=
-		    (rdata1 & SR_PMM_SR_MSB_XO_CLOCK_MASK))
-			break;
-		usleep_range(5, 10);
-	}
-
-	ret = icnss_hw_reset_xo_disable_cmd(priv);
-	if (ret) {
-		icnss_hw_write_reg_field(priv->mpm_config_va,
-					 MPM_WCSSAON_CONFIG_OFFSET,
-					 MPM_WCSSAON_CONFIG_FORCE_ACTIVE, 0);
-		icnss_hw_write_reg_field(priv->mpm_config_va,
-					 MPM_WCSSAON_CONFIG_OFFSET,
-					 MPM_WCSSAON_CONFIG_DISCONNECT_CLR, 0);
-		icnss_hw_write_reg_field(priv->mpm_config_va,
-					 MPM_WCSSAON_CONFIG_OFFSET,
-					 MPM_WCSSAON_CONFIG_WLAN_DISABLE, 1);
-		goto top_level_reset;
-	}
-
-	icnss_hw_write_reg_field(priv->mpm_config_va, MPM_WCSSAON_CONFIG_OFFSET,
-				 MPM_WCSSAON_CONFIG_FORCE_ACTIVE, 0);
-
-	icnss_hw_write_reg_field(priv->mpm_config_va, MPM_WCSSAON_CONFIG_OFFSET,
-				 MPM_WCSSAON_CONFIG_DISCONNECT_CLR, 0);
-
-	icnss_hw_write_reg_field(priv->mpm_config_va, MPM_WCSSAON_CONFIG_OFFSET,
-				 MPM_WCSSAON_CONFIG_WLAN_DISABLE, 1);
-
-	icnss_hw_poll_reg_field(priv->mem_base_va, SR_WCSSAON_SR_LSB_OFFSET,
-				BIT(26), 1, 200, ICNSS_HW_REG_RETRY);
-
-top_level_reset:
-	icnss_hw_top_level_reset(priv);
-
-	icnss_pr_dbg("RESET: DONE, state: 0x%lx\n", priv->state);
-
-	return 0;
-}
-
 static int icnss_hw_power_on(struct icnss_priv *priv)
 {
 	int ret = 0;
@@ -1578,21 +680,6 @@ static int icnss_hw_power_on(struct icnss_priv *priv)
 	set_bit(ICNSS_POWER_ON, &priv->state);
 	spin_unlock_irqrestore(&priv->on_off_lock, flags);
 
-	ret = icnss_vreg_on(priv);
-	if (ret)
-		goto out;
-
-	ret = icnss_clk_init(priv);
-	if (ret)
-		goto out;
-
-	icnss_hw_top_level_release_reset(priv);
-
-	icnss_hw_io_reset(penv, 1);
-
-	return ret;
-out:
-	clear_bit(ICNSS_POWER_ON, &priv->state);
 	return ret;
 }
 
@@ -1614,19 +701,6 @@ static int icnss_hw_power_off(struct icnss_priv *priv)
 	clear_bit(ICNSS_POWER_ON, &priv->state);
 	spin_unlock_irqrestore(&priv->on_off_lock, flags);
 
-	icnss_hw_io_reset(penv, 0);
-
-	icnss_hw_reset(priv);
-
-	icnss_clk_deinit(priv);
-
-	ret = icnss_vreg_off(priv);
-	if (ret)
-		goto out;
-
-	return ret;
-out:
-	set_bit(ICNSS_POWER_ON, &priv->state);
 	return ret;
 }
 
@@ -3693,117 +2767,6 @@ static void icnss_smmu_deinit(struct icnss_priv *priv)
 	priv->smmu_mapping = NULL;
 }
 
-static int icnss_get_vreg_info(struct device *dev,
-			       struct icnss_vreg_info *vreg_info)
-{
-	int ret = 0;
-	char prop_name[MAX_PROP_SIZE];
-	struct regulator *reg;
-	const __be32 *prop;
-	int len = 0;
-	int i;
-
-	reg = devm_regulator_get_optional(dev, vreg_info->name);
-
-	if (PTR_ERR(reg) == -EPROBE_DEFER) {
-		icnss_pr_err("EPROBE_DEFER for regulator: %s\n",
-			     vreg_info->name);
-		ret = PTR_ERR(reg);
-		goto out;
-	}
-
-	if (IS_ERR(reg)) {
-		ret = PTR_ERR(reg);
-
-		if (vreg_info->required) {
-
-			icnss_pr_err("Regulator %s doesn't exist: %d\n",
-				     vreg_info->name, ret);
-			goto out;
-		} else {
-			icnss_pr_dbg("Optional regulator %s doesn't exist: %d\n",
-				     vreg_info->name, ret);
-			goto done;
-		}
-	}
-
-	vreg_info->reg = reg;
-
-	snprintf(prop_name, MAX_PROP_SIZE,
-		 "qcom,%s-config", vreg_info->name);
-
-	prop = of_get_property(dev->of_node, prop_name, &len);
-
-	icnss_pr_dbg("Got regulator config, prop: %s, len: %d\n",
-		     prop_name, len);
-
-	if (!prop || len < (2 * sizeof(__be32))) {
-		icnss_pr_dbg("Property %s %s\n", prop_name,
-			     prop ? "invalid format" : "doesn't exist");
-		goto done;
-	}
-
-	for (i = 0; (i * sizeof(__be32)) < len; i++) {
-		switch (i) {
-		case 0:
-			vreg_info->min_v = be32_to_cpup(&prop[0]);
-			break;
-		case 1:
-			vreg_info->max_v = be32_to_cpup(&prop[1]);
-			break;
-		case 2:
-			vreg_info->load_ua = be32_to_cpup(&prop[2]);
-			break;
-		case 3:
-			vreg_info->settle_delay = be32_to_cpup(&prop[3]);
-			break;
-		default:
-			icnss_pr_dbg("Property %s, ignoring value at %d\n",
-				     prop_name, i);
-			break;
-		}
-	}
-
-done:
-	icnss_pr_dbg("Regulator: %s, min_v: %u, max_v: %u, load: %u, delay: %lu\n",
-		     vreg_info->name, vreg_info->min_v, vreg_info->max_v,
-		     vreg_info->load_ua, vreg_info->settle_delay);
-
-	return 0;
-
-out:
-	return ret;
-}
-
-static int icnss_get_clk_info(struct device *dev,
-			      struct icnss_clk_info *clk_info)
-{
-	struct clk *handle;
-	int ret = 0;
-
-	handle = devm_clk_get(dev, clk_info->name);
-
-	if (IS_ERR(handle)) {
-		ret = PTR_ERR(handle);
-		if (clk_info->required) {
-			icnss_pr_err("Clock %s isn't available: %d\n",
-				     clk_info->name, ret);
-			goto out;
-		} else {
-			icnss_pr_dbg("Ignoring clock %s: %d\n", clk_info->name,
-				     ret);
-			ret = 0;
-			goto out;
-		}
-	}
-
-	icnss_pr_dbg("Clock: %s, freq: %u\n", clk_info->name, clk_info->freq);
-
-	clk_info->handle = handle;
-out:
-	return ret;
-}
-
 static int icnss_test_mode_show(struct seq_file *s, void *data)
 {
 	struct icnss_priv *priv = s->private;
@@ -4476,21 +3439,6 @@ static int icnss_probe(struct platform_device *pdev)
 	if (ret == -EPROBE_DEFER)
 		goto out;
 
-	memcpy(priv->vreg_info, icnss_vreg_info, sizeof(icnss_vreg_info));
-	for (i = 0; i < ICNSS_VREG_INFO_SIZE; i++) {
-		ret = icnss_get_vreg_info(dev, &priv->vreg_info[i]);
-
-		if (ret)
-			goto out;
-	}
-
-	memcpy(priv->clk_info, icnss_clk_info, sizeof(icnss_clk_info));
-	for (i = 0; i < ICNSS_CLK_INFO_SIZE; i++) {
-		ret = icnss_get_clk_info(dev, &priv->clk_info[i]);
-		if (ret)
-			goto out;
-	}
-
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "membase");
 	if (!res) {
 		icnss_pr_err("Memory base not found in DT\n");
@@ -4510,26 +3458,6 @@ static int icnss_probe(struct platform_device *pdev)
 	icnss_pr_dbg("MEM_BASE pa: %pa, va: 0x%p\n", &priv->mem_base_pa,
 		     priv->mem_base_va);
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-					   "mpm_config");
-	if (!res) {
-		icnss_pr_err("MPM Config not found\n");
-		ret = -EINVAL;
-		goto out;
-	}
-	priv->mpm_config_pa = res->start;
-	priv->mpm_config_va = devm_ioremap(dev, priv->mpm_config_pa,
-					   resource_size(res));
-	if (!priv->mpm_config_va) {
-		icnss_pr_err("MPM Config ioremap failed, phy addr: %pa\n",
-			     &priv->mpm_config_pa);
-		ret = -EINVAL;
-		goto out;
-	}
-
-	icnss_pr_dbg("MPM_CONFIG pa: %pa, va: 0x%p\n", &priv->mpm_config_pa,
-		     priv->mpm_config_va);
-
 	for (i = 0; i < ICNSS_MAX_IRQ_REGISTRATIONS; i++) {
 		res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i);
 		if (!res) {