msm: kgsl: Preemption cleanups

Remove some unused gpudev hooks and further segment the A4XX and
A5XX specific code into their respective areas.  Remove some bits
that are only applicable to 4XX from the 5XX side.

CRs-Fixed: 1009124
Change-Id: Ic0dedbadc324b979583d7a3998195bf15ac537f6
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>

4 files changed, 39 insertions, 84 deletions

diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index 22827e7ca284..31be91bf4c39 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -711,17 +711,12 @@ struct adreno_gpudev {
 	void (*pwrlevel_change_settings)(struct adreno_device *,
 				unsigned int prelevel, unsigned int postlevel,
 				bool post);
-	int (*preemption_pre_ibsubmit)(struct adreno_device *,
-				struct adreno_ringbuffer *, unsigned int *,
-				struct kgsl_context *, uint64_t cond_addr,
-				struct kgsl_memobj_node *);
+	unsigned int (*preemption_pre_ibsubmit)(struct adreno_device *,
+				struct adreno_ringbuffer *rb,
+				unsigned int *, struct kgsl_context *);
 	int (*preemption_yield_enable)(unsigned int *);
-	int (*preemption_post_ibsubmit)(struct adreno_device *,
-				struct adreno_ringbuffer *, unsigned int *,
-				struct kgsl_context *);
-	int (*preemption_token)(struct adreno_device *,
-				struct adreno_ringbuffer *, unsigned int *,
-				uint64_t gpuaddr);
+	unsigned int (*preemption_post_ibsubmit)(struct adreno_device *,
+				unsigned int *);
 	int (*preemption_init)(struct adreno_device *);
 	void (*preemption_schedule)(struct adreno_device *);
 	void (*enable_64bit)(struct adreno_device *);
diff --git a/drivers/gpu/msm/adreno_a4xx.c b/drivers/gpu/msm/adreno_a4xx.c
index c9c969e0b14e..deadb483d60b 100644
--- a/drivers/gpu/msm/adreno_a4xx.c
+++ b/drivers/gpu/msm/adreno_a4xx.c
@@ -226,9 +226,8 @@ static void a4xx_preemption_save(struct adreno_device *adreno_dev,
 	kgsl_regread(device, A4XX_CP_SCRATCH_REG23, &rb->gpr11);
 }
 
-static int a4xx_preemption_token(struct adreno_device *adreno_dev,
-			struct adreno_ringbuffer *rb, unsigned int *cmds,
-			uint64_t gpuaddr)
+static unsigned int a4xx_preemption_token(struct adreno_device *adreno_dev,
+			unsigned int *cmds, uint64_t gpuaddr)
 {
 	unsigned int *cmds_orig = cmds;
 
@@ -240,36 +239,28 @@ static int a4xx_preemption_token(struct adreno_device *adreno_dev,
 	/* generate interrupt on preemption completion */
 	*cmds++ = 1 << CP_PREEMPT_ORDINAL_INTERRUPT;
 
-	return cmds - cmds_orig;
-
+	return (unsigned int) (cmds - cmds_orig);
 }
 
-static int a4xx_preemption_pre_ibsubmit(
+static unsigned int a4xx_preemption_pre_ibsubmit(
 			struct adreno_device *adreno_dev,
-			struct adreno_ringbuffer *rb, unsigned int *cmds,
-			struct kgsl_context *context, uint64_t cond_addr,
-			struct kgsl_memobj_node *ib)
+			struct adreno_ringbuffer *rb,
+			unsigned int *cmds,
+			struct kgsl_context *context)
 {
 	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
 	unsigned int *cmds_orig = cmds;
-	int exec_ib = 0;
-
-	cmds += a4xx_preemption_token(adreno_dev, rb, cmds,
-			MEMSTORE_ID_GPU_ADDR(device, context->id, preempted));
+	unsigned int cond_addr =
+		MEMSTORE_ID_GPU_ADDR(device, context->id, preempted);
 
-	if (ib)
-		exec_ib = 1;
+	cmds += a4xx_preemption_token(adreno_dev, cmds, cond_addr);
 
 	*cmds++ = cp_type3_packet(CP_COND_EXEC, 4);
 	*cmds++ = cond_addr;
 	*cmds++ = cond_addr;
 	*cmds++ = 1;
-	*cmds++ = 7 + exec_ib * 3;
-	if (exec_ib) {
-		*cmds++ = cp_type3_packet(CP_INDIRECT_BUFFER_PFE, 2);
-		*cmds++ = ib->gpuaddr;
-		*cmds++ = (unsigned int) ib->size >> 2;
-	}
+	*cmds++ = 7;
+
 	/* clear preemption flag */
 	*cmds++ = cp_type3_packet(CP_MEM_WRITE, 2);
 	*cmds++ = cond_addr;
@@ -279,7 +270,7 @@ static int a4xx_preemption_pre_ibsubmit(
 	*cmds++ = cp_type3_packet(CP_WAIT_FOR_ME, 1);
 	*cmds++ = 0;
 
-	return cmds - cmds_orig;
+	return (unsigned int) (cmds - cmds_orig);
 }
 
 /*
@@ -1848,7 +1839,6 @@ static int a4xx_submit_preempt_token(struct adreno_ringbuffer *rb,
 	struct adreno_device *adreno_dev = ADRENO_RB_DEVICE(rb);
 	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
 	unsigned int *ringcmds, *start;
-	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
 	int ptname;
 	struct kgsl_pagetable *pt;
 	int pt_switch_sizedwords = 0, total_sizedwords = 20;
@@ -1902,7 +1892,7 @@ static int a4xx_submit_preempt_token(struct adreno_ringbuffer *rb,
 	*ringcmds++ = cp_packet(adreno_dev, CP_SET_PROTECTED_MODE, 1);
 	*ringcmds++ = 1;
 
-	ringcmds += gpudev->preemption_token(adreno_dev, rb, ringcmds,
+	ringcmds += a4xx_preemption_token(adreno_dev, ringcmds,
 				device->memstore.gpuaddr +
 				MEMSTORE_RB_OFFSET(rb, preempted));
 
@@ -2276,6 +2266,5 @@ struct adreno_gpudev adreno_a4xx_gpudev = {
 	.regulator_enable = a4xx_regulator_enable,
 	.regulator_disable = a4xx_regulator_disable,
 	.preemption_pre_ibsubmit = a4xx_preemption_pre_ibsubmit,
-	.preemption_token = a4xx_preemption_token,
 	.preemption_schedule = a4xx_preemption_schedule,
 };
diff --git a/drivers/gpu/msm/adreno_a5xx.c b/drivers/gpu/msm/adreno_a5xx.c
index d82d426a78dc..cee6c8dbb60e 100644
--- a/drivers/gpu/msm/adreno_a5xx.c
+++ b/drivers/gpu/msm/adreno_a5xx.c
@@ -309,31 +309,29 @@ static int a5xx_preemption_init(struct adreno_device *adreno_dev)
  * PM4 commands for preempt token on a5xx. These commands are
  * submitted to ringbuffer to trigger preemption.
  */
-static int a5xx_preemption_token(struct adreno_device *adreno_dev,
-			struct adreno_ringbuffer *rb, unsigned int *cmds,
-			uint64_t gpuaddr)
+static unsigned int a5xx_preemption_token(struct adreno_device *adreno_dev,
+			unsigned int *cmds)
 {
 	unsigned int *cmds_orig = cmds;
 
 	*cmds++ = cp_type7_packet(CP_CONTEXT_SWITCH_YIELD, 4);
-	cmds += cp_gpuaddr(adreno_dev, cmds, gpuaddr);
+	/* Write NULL to the address to skip the data write */
+	cmds += cp_gpuaddr(adreno_dev, cmds, 0x0);
 	*cmds++ = 1;
 	/* generate interrupt on preemption completion */
 	*cmds++ = 1;
 
-	return cmds - cmds_orig;
-
+	return (unsigned int) (cmds - cmds_orig);
 }
 
 /*
  * a5xx_preemption_pre_ibsubmit() - Below PM4 commands are
  * added at the beginning of every cmdbatch submission.
  */
-static int a5xx_preemption_pre_ibsubmit(
+static unsigned int a5xx_preemption_pre_ibsubmit(
 			struct adreno_device *adreno_dev,
-			struct adreno_ringbuffer *rb, unsigned int *cmds,
-			struct kgsl_context *context, uint64_t cond_addr,
-			struct kgsl_memobj_node *ib)
+			struct adreno_ringbuffer *rb,
+			unsigned int *cmds, struct kgsl_context *context)
 {
 	unsigned int *cmds_orig = cmds;
 	uint64_t gpuaddr = rb->preemption_desc.gpuaddr;
@@ -401,7 +399,7 @@ static int a5xx_preemption_pre_ibsubmit(
 	*cmds++ = cp_type7_packet(CP_YIELD_ENABLE, 1);
 	*cmds++ = 2;
 
-	return cmds - cmds_orig;
+	return (unsigned int) (cmds - cmds_orig);
 }
 
 /*
@@ -434,15 +432,12 @@ static int a5xx_preemption_yield_enable(unsigned int *cmds)
  * a5xx_preemption_post_ibsubmit() - Below PM4 commands are
  * added after every cmdbatch submission.
  */
-static int a5xx_preemption_post_ibsubmit(struct adreno_device *adreno_dev,
-			struct adreno_ringbuffer *rb, unsigned int *cmds,
-			struct kgsl_context *context)
-{
-	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
-	unsigned int ctx_id = context ? context->id : 0;
+static unsigned int a5xx_preemption_post_ibsubmit(
+			struct adreno_device *adreno_dev,
+			unsigned int *cmds)
 
-	return a5xx_preemption_token(adreno_dev, rb, cmds,
-			MEMSTORE_ID_GPU_ADDR(device, ctx_id, preempted));
+{
+	return a5xx_preemption_token(adreno_dev, cmds);
 }
 
 static void a5xx_platform_setup(struct adreno_device *adreno_dev)
@@ -2220,11 +2215,8 @@ static int _preemption_init(
 			struct adreno_ringbuffer *rb, unsigned int *cmds,
 			struct kgsl_context *context)
 {
-	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
 	unsigned int *cmds_orig = cmds;
 	uint64_t gpuaddr = rb->preemption_desc.gpuaddr;
-	uint64_t gpuaddr_token = MEMSTORE_ID_GPU_ADDR(device,
-			KGSL_MEMSTORE_GLOBAL, preempted);
 
 	/* Turn CP protection OFF */
 	*cmds++ = cp_type7_packet(CP_SET_PROTECTED_MODE, 1);
@@ -2253,8 +2245,8 @@ static int _preemption_init(
 	*cmds++ = 1;
 
 	*cmds++ = cp_type7_packet(CP_CONTEXT_SWITCH_YIELD, 4);
-	cmds += cp_gpuaddr(adreno_dev, cmds, gpuaddr_token);
-	*cmds++ = 1;
+	cmds += cp_gpuaddr(adreno_dev, cmds, 0x0);
+	*cmds++ = 0;
 	/* generate interrupt on preemption completion */
 	*cmds++ = 1;
 
@@ -3867,7 +3859,6 @@ static void a5xx_preempt_clear_state(
 	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
 	struct adreno_ringbuffer *highest_busy_rb;
 	int switch_low_to_high;
-	int ret;
 
 	/* Device not awake means there is nothing to do */
 	if (!kgsl_state_is_awake(device))
@@ -3897,21 +3888,6 @@ static void a5xx_preempt_clear_state(
 		 */
 		if (!adreno_rb_empty(adreno_dev->cur_rb))
 			return;
-		/*
-		 * switch to default context because when we switch back
-		 * to higher context then its not known which pt will
-		 * be current, so by making it default here the next
-		 * commands submitted will set the right pt
-		 */
-		ret = adreno_drawctxt_switch(adreno_dev,
-				adreno_dev->cur_rb,
-				NULL, 0);
-		/*
-		 * lower priority RB has to wait until space opens up in
-		 * higher RB
-		 */
-		if (ret)
-			return;
 	}
 
 	/*
@@ -4105,7 +4081,6 @@ struct adreno_gpudev adreno_a5xx_gpudev = {
 				a5xx_preemption_yield_enable,
 	.preemption_post_ibsubmit =
 			a5xx_preemption_post_ibsubmit,
-	.preemption_token = a5xx_preemption_token,
 	.preemption_init = a5xx_preemption_init,
 	.preemption_schedule = a5xx_preemption_schedule,
 	.enable_64bit = a5xx_enable_64bit,
diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index 1921bf69495d..383acb71a571 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -451,7 +451,6 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb,
 	struct adreno_context *drawctxt = rb->drawctxt_active;
 	struct kgsl_context *context = NULL;
 	bool secured_ctxt = false;
-	uint64_t cond_addr;
 	static unsigned int _seq_cnt;
 
 	if (drawctxt != NULL && kgsl_context_detached(&drawctxt->base) &&
@@ -564,12 +563,9 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb,
 	*ringcmds++ = KGSL_CMD_IDENTIFIER;
 
 	if (adreno_is_preemption_enabled(adreno_dev) &&
-				gpudev->preemption_pre_ibsubmit) {
-		cond_addr = MEMSTORE_ID_GPU_ADDR(device, context_id, preempted);
+				gpudev->preemption_pre_ibsubmit)
 		ringcmds += gpudev->preemption_pre_ibsubmit(
-					adreno_dev, rb, ringcmds, context,
-					cond_addr, NULL);
-	}
+					adreno_dev, rb, ringcmds, context);
 
 	if (flags & KGSL_CMD_FLAGS_INTERNAL_ISSUE) {
 		*ringcmds++ = cp_packet(adreno_dev, CP_NOP, 1);
@@ -704,8 +700,8 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb,
 
 	if (gpudev->preemption_post_ibsubmit &&
 				adreno_is_preemption_enabled(adreno_dev))
-		ringcmds += gpudev->preemption_post_ibsubmit(adreno_dev, rb,
-					ringcmds, &drawctxt->base);
+		ringcmds += gpudev->preemption_post_ibsubmit(adreno_dev,
+			ringcmds);
 
 	/*
 	 * If we have more ringbuffer commands than space reserved