diff options
| author | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-06-14 17:23:53 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2017-03-30 22:42:34 -0700 |
| commit | 0c370689489d94e58b03b61f61cd09c7fc43eba3 (patch) | |
| tree | 060d950f9513b2266aaee519c184160bfdd2e4a7 | |
| parent | a674e321fb7ec4c5be90ef45708ff61ce8aa41b7 (diff) | |
ARM: dts: msm: Update clock frequencies for msm8996AU
Add the CPU and GPU clock frequency tables in device tree
to support MSM8996 auto. These overrides apply for both
v3 and pro based msm8996AU.
CRs-Fixed: 1039602
Change-Id: I092c0767570cf500886b75823f24346097676473
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8996v3-auto.dtsi | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/msm8996v3-auto.dtsi b/arch/arm/boot/dts/qcom/msm8996v3-auto.dtsi index 2e884b5915f1..32adb9a36dd4 100644 --- a/arch/arm/boot/dts/qcom/msm8996v3-auto.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996v3-auto.dtsi @@ -94,3 +94,76 @@ }; }; }; + +&clock_cpu { + qcom,pwrcl-speedbin0-v0 = + < 0 0 >, + < 768000000 7 >, + < 844800000 8 >, + < 902400000 9 >, + < 979200000 10 >, + < 1056000000 11 >, + < 1132800000 12 >, + < 1209600000 13 >, + < 1286400000 14 >, + < 1363200000 15 >, + < 1440000000 16 >, + < 1516800000 17 >, + < 1593600000 18 >; + + qcom,perfcl-speedbin0-v0 = + < 0 0 >, + < 825600000 8 >, + < 902400000 9 >, + < 979200000 10 >, + < 1056000000 11 >, + < 1132800000 12 >, + < 1209600000 13 >, + < 1286400000 14 >, + < 1363200000 15 >, + < 1440000000 16 >, + < 1516800000 17 >, + < 1593600000 18 >, + < 1670400000 19 >, + < 1747200000 20 >, + < 1824000000 21 >, + < 1900800000 22 >, + < 1977600000 23 >, + < 2054400000 24 >; + + qcom,cbf-speedbin0-v0 = + < 0 0 >, + < 537600000 5 >, + < 614400000 6 >, + < 691200000 7 >, + < 768000000 8 >, + < 844800000 9 >, + < 902400000 10 >, + < 979200000 11 >, + < 1056000000 12 >, + < 1132800000 13 >, + < 1190400000 14 >, + < 1286400000 15 >, + < 1363200000 16 >, + < 1440000000 17 >, + < 1516800000 18 >, + < 1593600000 19 >; +}; + +&clock_gpu { + qcom,gfxfreq-speedbin0 = + < 0 0 0 >, + < 315000000 4 4 >, + < 401800000 5 5 >, + < 510000000 6 5 >, + < 560000000 7 7 >, + < 624000000 8 7 >; + + qcom,gfxfreq-mx-speedbin0 = + < 0 0 >, + < 315000000 4 >, + < 401800000 5 >, + < 510000000 5 >, + < 560000000 7 >, + < 624000000 7 >; +}; |