diff options
| author | Shashank Mittal <mittals@codeaurora.org> | 2016-05-02 16:14:22 -0700 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-05-19 16:07:56 -0700 |
| commit | 06761098a186c4b64d33d2ed3949408965db3687 (patch) | |
| tree | d49684f38e0d98b30d53143185d996089adc24ca | |
| parent | 74c123fd3ff8882638bfb61761b7115ece9413ef (diff) | |
ARM: dts: msm: add HW event device for msmcobalt
Add device node for HW event driver. HW event driver can be used to
configure HW events on msmcobalt device.
Change-Id: I5e633e798a0655d783554538b83b4642ec428c8c
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt-coresight.dtsi | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-coresight.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-coresight.dtsi index 8f29567e1d27..c6367c05775c 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-coresight.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-coresight.dtsi @@ -1364,4 +1364,36 @@ }; }; }; + + hwevent: hwevent@158000 { + compatible = "qcom,coresight-hwevent"; + reg = <0x158000 0x80>, + <0x17091000 0x80>, + <0x1730200c 0x4>, + <0xc90137c 0x4>, + <0xc828018 0x80>, + <0x1c00058 0x80>, + <0x5e02038 0x4>, + <0x5e02028 0x10>, + <0x1fcb360 0x80>, + <0x1fcb760 0x80>, + <0x1fcbf60 0x80>, + <0xa8f8860 0x4>, + <0x500c260 0x4>, + <0x500d040 0x4>, + <0x1da6400 0x80>; + reg-names = "gcc-ctrl", "lpass-stm", "lpass-qdsp", "mdss-mdp", + "mdss-misc", "pcie0-hwev", "ssc-en", "ssc-hwev", + "tcsr-qdss", "tcsr-mss0", "tcsr-mss1", "usb-ctrl", + "vbif-stm", "vbif-stm-en", "ufs-mux"; + + coresight-name = "coresight-hwevent"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>, + <&clock_mmss clk_mmss_misc_ahb_clk>; + clock-names = "core_clk", "core_a_clk", "core_mmss_clk"; + + qcom,hwevent-clks = "core_mmss_clk"; + }; }; |