diff options
| author | Sunil Khatri <sunilkh@codeaurora.org> | 2016-10-04 18:53:22 +0530 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-10-05 23:43:18 -0700 |
| commit | 050ce1a558f617d4e3eb9af2af543adee2ab0967 (patch) | |
| tree | 9f212129784546a7d53ab10091cb9ca14f57cdc4 | |
| parent | 057bdafd976ca7609ed223dbd4473d535bcb6459 (diff) | |
msm: kgsl: Disable UCHE global filter
Disable UCHE global filter for invalidate/flush,
SP will handle the invalidate/flush for each SP
independently on A5XX GPUs.
CRs-Fixed: 1073853
Change-Id: I3daf3722cfbdfff080161f9a0248fd8096550328
Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
| -rw-r--r-- | drivers/gpu/msm/a5xx_reg.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/msm/adreno_a5xx.c | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/msm/a5xx_reg.h b/drivers/gpu/msm/a5xx_reg.h index 3b29452ce8bd..f3b4e6622043 100644 --- a/drivers/gpu/msm/a5xx_reg.h +++ b/drivers/gpu/msm/a5xx_reg.h @@ -640,6 +640,7 @@ /* UCHE registers */ #define A5XX_UCHE_ADDR_MODE_CNTL 0xE80 +#define A5XX_UCHE_MODE_CNTL 0xE81 #define A5XX_UCHE_WRITE_THRU_BASE_LO 0xE87 #define A5XX_UCHE_WRITE_THRU_BASE_HI 0xE88 #define A5XX_UCHE_TRAP_BASE_LO 0xE89 diff --git a/drivers/gpu/msm/adreno_a5xx.c b/drivers/gpu/msm/adreno_a5xx.c index 1782d1d54946..2ee8287b4459 100644 --- a/drivers/gpu/msm/adreno_a5xx.c +++ b/drivers/gpu/msm/adreno_a5xx.c @@ -1875,6 +1875,11 @@ static void a5xx_start(struct adreno_device *adreno_dev) */ kgsl_regrmw(device, A5XX_RB_DBG_ECO_CNT, 0, (1 << 9)); } + /* + * Disable UCHE global filter as SP can invalidate/flush + * independently + */ + kgsl_regwrite(device, A5XX_UCHE_MODE_CNTL, BIT(29)); /* Set the USE_RETENTION_FLOPS chicken bit */ kgsl_regwrite(device, A5XX_CP_CHICKEN_DBG, 0x02000000); |