diff options
| author | Shubhraprakash Das <sadas@codeaurora.org> | 2017-03-02 19:38:31 -0800 |
|---|---|---|
| committer | Shubhraprakash Das <sadas@codeaurora.org> | 2017-03-14 20:20:24 -0700 |
| commit | 02f717ea101357c435a55d6bf72a4556543049cd (patch) | |
| tree | c4f3cdbf7431d42c70c8e887594a11eb473b8758 | |
| parent | 89bfd053bfb4afb40d86f58de52cb7b1433dccba (diff) | |
ARM: dts: msm: Set the rate for camss vfe clock on msm8998
Under ispif node set clock rate for camss vfe clock since
after xo shutdown this clock cannot be enabled without
setting rate first. Also, enable vfe clk src before
camss clock.
CRs-Fixed: 2013802
Change-Id: Ic735b405348e7f54c02fe222c87b6ceb862a9096
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-camera.dtsi | 42 |
1 files changed, 22 insertions, 20 deletions
diff --git a/arch/arm/boot/dts/qcom/msm8998-camera.dtsi b/arch/arm/boot/dts/qcom/msm8998-camera.dtsi index e0ba982d7932..f87444465a68 100644 --- a/arch/arm/boot/dts/qcom/msm8998-camera.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-camera.dtsi @@ -493,11 +493,11 @@ <&clock_mmss clk_mmss_camss_csi1_clk>, <&clock_mmss clk_mmss_camss_csi2_clk>, <&clock_mmss clk_mmss_camss_csi3_clk>, - <&clock_mmss clk_mmss_camss_vfe0_clk>, <&clock_mmss clk_vfe0_clk_src>, + <&clock_mmss clk_mmss_camss_vfe0_clk>, <&clock_mmss clk_mmss_camss_csi_vfe0_clk>, - <&clock_mmss clk_mmss_camss_vfe1_clk>, <&clock_mmss clk_vfe1_clk_src>, + <&clock_mmss clk_mmss_camss_vfe1_clk>, <&clock_mmss clk_mmss_camss_csi_vfe1_clk>; clock-names = "mmssnoc_axi", "mnoc_ahb_clk", "camss_ahb_clk", @@ -510,10 +510,12 @@ "csi2_pix_clk", "csi3_pix_clk", "camss_csi0_clk", "camss_csi1_clk", "camss_csi2_clk", "camss_csi3_clk", + "vfe0_clk_src", "camss_vfe_vfe0_clk", - "vfe0_clk_src", "camss_csi_vfe0_clk", + "camss_csi_vfe0_clk", + "vfe1_clk_src", "camss_vfe_vfe1_clk", - "vfe1_clk_src", "camss_csi_vfe1_clk"; + "camss_csi_vfe1_clk"; qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 0 0 @@ -532,10 +534,10 @@ "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", - "NO_SET_RATE", - "INIT_RATE", "NO_SET_RATE", - "NO_SET_RATE", - "INIT_RATE", "NO_SET_RATE"; + "INIT_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "INIT_RATE", + "NO_SET_RATE", "NO_SET_RATE"; status = "ok"; }; @@ -557,23 +559,23 @@ <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, <&clock_mmss clk_mmss_camss_ahb_clk>, <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_vfe0_clk_src>, <&clock_mmss clk_mmss_camss_vfe0_clk>, <&clock_mmss clk_mmss_camss_vfe0_stream_clk>, <&clock_mmss clk_mmss_camss_vfe0_ahb_clk>, <&clock_mmss clk_mmss_camss_vfe_vbif_ahb_clk>, <&clock_mmss clk_mmss_camss_vfe_vbif_axi_clk>, - <&clock_mmss clk_vfe0_clk_src>, <&clock_mmss clk_mmss_camss_csi_vfe0_clk>; clock-names = "mmssnoc_axi", "mnoc_ahb_clk", "bimc_smmu_ahb_clk", "bimc_smmu_axi_clk", - "camss_ahb_clk", "camss_top_ahb_clk", + "camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src", "camss_vfe_clk", "camss_vfe_stream_clk", "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", - "camss_vfe_vbif_axi_clk", "vfe_clk_src", + "camss_vfe_vbif_axi_clk", "camss_csi_vfe_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 480000000 0 - 0 0 0 0 0 0 0 0 0 0 0 576000000 0 - 0 0 0 0 0 0 0 0 0 0 0 600000000 0>; + qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0 0 0 0 0 + 0 0 0 0 0 0 576000000 0 0 0 0 0 0 + 0 0 0 0 0 0 600000000 0 0 0 0 0 0>; status = "ok"; qos-entries = <8>; qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 @@ -637,23 +639,23 @@ <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, <&clock_mmss clk_mmss_camss_ahb_clk>, <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_vfe1_clk_src>, <&clock_mmss clk_mmss_camss_vfe1_clk>, <&clock_mmss clk_mmss_camss_vfe1_stream_clk>, <&clock_mmss clk_mmss_camss_vfe1_ahb_clk>, <&clock_mmss clk_mmss_camss_vfe_vbif_ahb_clk>, <&clock_mmss clk_mmss_camss_vfe_vbif_axi_clk>, - <&clock_mmss clk_vfe1_clk_src>, <&clock_mmss clk_mmss_camss_csi_vfe1_clk>; clock-names = "mmssnoc_axi", "mnoc_ahb_clk", "bimc_smmu_ahb_clk", "bimc_smmu_axi_clk", - "camss_ahb_clk", "camss_top_ahb_clk", + "camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src", "camss_vfe_clk", "camss_vfe_stream_clk", "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", - "camss_vfe_vbif_axi_clk", "vfe_clk_src", + "camss_vfe_vbif_axi_clk", "camss_csi_vfe_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 480000000 0 - 0 0 0 0 0 0 0 0 0 0 0 576000000 0 - 0 0 0 0 0 0 0 0 0 0 0 600000000 0>; + qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0 0 0 0 0 + 0 0 0 0 0 0 576000000 0 0 0 0 0 0 + 0 0 0 0 0 0 600000000 0 0 0 0 0 0>; status = "ok"; qos-entries = <8>; qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 |