ARM: dts: msm: update clock regulator nodes for msm8998 interposer

The clock nodes require the regulator nodes to be updated for interposer,
so add the same. Also update the gfx rail regulator phandle.

Change-Id: I08580f4eb04660cd1d123065976ba9bfec61b7d8
Signed-off-by: Taniya Das <tdas@codeaurora.org>

3 files changed, 119 insertions, 3 deletions

diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi
index 66c53649ad71..e83191ebfbc0 100644
--- a/arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi
@@ -199,9 +199,7 @@
 };
 
 &gfx_cpr {
-	reg =	<0x05061000 0x4000>,
-		    <0x00784000 0x1000>;
-	reg-names = "cpr_ctrl", "fuse_base";
+	status = "disabled";
 
 	/* disable aging and closed-loop */
 	/delete-property/vdd-supply;
@@ -212,6 +210,8 @@
 };
 
 &gfx_vreg {
+	status = "disabled";
+
 	/delete-property/qcom,cpr-aging-max-voltage-adjustment;
 	/delete-property/qcom,cpr-aging-ref-corner;
 	/delete-property/qcom,cpr-aging-ro-scaling-factor;
diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts
index 03e6a7e17215..528e48df1268 100644
--- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts
+++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts
@@ -27,3 +27,61 @@
 &pmfalcon_charger {
 	qcom,batteryless-platform;
 };
+
+&clock_gcc {
+	vdd_dig-supply = <&pm2falcon_s3_level>;
+	vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>;
+};
+
+&clock_mmss {
+	vdd_dig-supply = <&pm2falcon_s3_level>;
+	vdd_mmsscc_mx-supply = <&pm2falcon_s5_level>;
+};
+
+&clock_gpu {
+	vdd_dig-supply = <&pm2falcon_s3_level>;
+};
+
+&clock_gfx {
+	/* GFX Rail = CX */
+	vdd_gpucc-supply = <&pm2falcon_s3_level>;
+	vdd_mx-supply = <&pm2falcon_s5_level>;
+	vdd_gpu_mx-supply = <&pm2falcon_s5_level>;
+	qcom,gfxfreq-speedbin0 =
+		<         0 0                           0 >,
+		< 180000000 RPM_SMD_REGULATOR_LEVEL_MIN_SVS
+					RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 257000000 RPM_SMD_REGULATOR_LEVEL_LOW_SVS
+					RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 342000000 RPM_SMD_REGULATOR_LEVEL_SVS
+					RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 414000000 RPM_SMD_REGULATOR_LEVEL_SVS_PLUS
+					RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 515000000 RPM_SMD_REGULATOR_LEVEL_NOM
+					RPM_SMD_REGULATOR_LEVEL_NOM >,
+		< 596000000 RPM_SMD_REGULATOR_LEVEL_NOM_PLUS
+					RPM_SMD_REGULATOR_LEVEL_NOM >,
+		< 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO
+					RPM_SMD_REGULATOR_LEVEL_TURBO >,
+		< 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO
+					RPM_SMD_REGULATOR_LEVEL_TURBO >;
+	qcom,gfxfreq-mx-speedbin0 =
+		<         0                           0 >,
+		< 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 257000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 342000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >,
+		< 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >,
+		< 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >,
+		< 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >;
+};
+
+&gdsc_gpu_gx {
+	clock-names = "core_root_clk";
+	clocks = <&clock_gfx clk_gfx3d_clk_src>;
+	qcom,force-enable-root-clk;
+	/* GFX Rail = CX */
+	parent-supply = <&pm2falcon_s3_level>;
+	status = "ok";
+};
diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts
index b66e4bbe236f..0f0a88b33402 100644
--- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts
+++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts
@@ -27,3 +27,61 @@
 &pmfalcon_fg {
 	qcom,battery-data = <&mtp_batterydata>;
 };
+
+&clock_gcc {
+	vdd_dig-supply = <&pm2falcon_s3_level>;
+	vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>;
+};
+
+&clock_mmss {
+	vdd_dig-supply = <&pm2falcon_s3_level>;
+	vdd_mmsscc_mx-supply = <&pm2falcon_s5_level>;
+};
+
+&clock_gpu {
+	vdd_dig-supply = <&pm2falcon_s3_level>;
+};
+
+&clock_gfx {
+	/* GFX Rail = CX */
+	vdd_gpucc-supply = <&pm2falcon_s3_level>;
+	vdd_mx-supply = <&pm2falcon_s5_level>;
+	vdd_gpu_mx-supply = <&pm2falcon_s5_level>;
+	qcom,gfxfreq-speedbin0 =
+		<         0 0                           0 >,
+		< 180000000 RPM_SMD_REGULATOR_LEVEL_MIN_SVS
+					RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 257000000 RPM_SMD_REGULATOR_LEVEL_LOW_SVS
+					RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 342000000 RPM_SMD_REGULATOR_LEVEL_SVS
+					RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 414000000 RPM_SMD_REGULATOR_LEVEL_SVS_PLUS
+					RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 515000000 RPM_SMD_REGULATOR_LEVEL_NOM
+					RPM_SMD_REGULATOR_LEVEL_NOM >,
+		< 596000000 RPM_SMD_REGULATOR_LEVEL_NOM_PLUS
+					RPM_SMD_REGULATOR_LEVEL_NOM >,
+		< 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO
+					RPM_SMD_REGULATOR_LEVEL_TURBO >,
+		< 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO
+					RPM_SMD_REGULATOR_LEVEL_TURBO >;
+	qcom,gfxfreq-mx-speedbin0 =
+		<         0                           0 >,
+		< 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 257000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 342000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >,
+		< 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >,
+		< 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >,
+		< 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >;
+};
+
+&gdsc_gpu_gx {
+	clock-names = "core_root_clk";
+	clocks = <&clock_gfx clk_gfx3d_clk_src>;
+	qcom,force-enable-root-clk;
+	/* GFX Rail = CX */
+	parent-supply = <&pm2falcon_s3_level>;
+	status = "ok";
+};