diff options
| author | Subhash Jadavani <subhashj@codeaurora.org> | 2016-11-10 12:09:18 -0800 |
|---|---|---|
| committer | Subhash Jadavani <subhashj@codeaurora.org> | 2016-11-24 07:59:56 -0800 |
| commit | 00e8c4542a6fbbdfad334ce8a032cc40c5c0d302 (patch) | |
| tree | 90f133fa84f0baea9be24793cf50b59f8af9fa9e | |
| parent | 0c82737188e2d63a08196e078e411032dbbc3b89 (diff) | |
ARM: dts: msm: add UFS_RESET pin ctrl data for msm8998
This change adds the UFS_RESET pin ctrl data for UFS controller node.
This will enable UFS driver to issue reset to UFS device.
Change-Id: I61561fb7e395671d2bc52c6a9c0c71e0351114ea
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi | 46 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998.dtsi | 4 |
2 files changed, 50 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi b/arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi index 1f5facd5cde5..5685e9041fe4 100644 --- a/arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi @@ -1624,6 +1624,52 @@ }; }; + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + sdc2_clk_on: sdc2_clk_on { config { pins = "sdc2_clk"; diff --git a/arch/arm/boot/dts/qcom/msm8998.dtsi b/arch/arm/boot/dts/qcom/msm8998.dtsi index 7f7f2f65deee..e95bc8597043 100644 --- a/arch/arm/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998.dtsi @@ -1660,6 +1660,10 @@ qcom,pm-qos-cpu-group-latency-us = <70 70>; qcom,pm-qos-default-cpu = <0>; + pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; + pinctrl-0 = <&ufs_dev_reset_assert>; + pinctrl-1 = <&ufs_dev_reset_deassert>; + resets = <&clock_gcc UFS_BCR>; reset-names = "core_reset"; |