diff options
Diffstat (limited to 'include/linux/mfd')
| -rw-r--r-- | include/linux/mfd/msm-cdc-pinctrl.h | 41 | ||||
| -rw-r--r-- | include/linux/mfd/msm-cdc-supply.h | 48 | ||||
| -rwxr-xr-x | include/linux/mfd/wcd9335/registers.h | 1348 | ||||
| -rw-r--r-- | include/linux/mfd/wcd934x/registers.h | 1848 | ||||
| -rwxr-xr-x | include/linux/mfd/wcd9xxx/Kbuild | 2 | ||||
| -rw-r--r-- | include/linux/mfd/wcd9xxx/core.h | 437 | ||||
| -rwxr-xr-x | include/linux/mfd/wcd9xxx/pdata.h | 197 | ||||
| -rwxr-xr-x | include/linux/mfd/wcd9xxx/wcd9310_registers.h | 1106 | ||||
| -rwxr-xr-x | include/linux/mfd/wcd9xxx/wcd9330_registers.h | 1626 | ||||
| -rw-r--r-- | include/linux/mfd/wcd9xxx/wcd9xxx-irq.h | 32 | ||||
| -rwxr-xr-x | include/linux/mfd/wcd9xxx/wcd9xxx-slimslave.h | 119 | ||||
| -rw-r--r-- | include/linux/mfd/wcd9xxx/wcd9xxx-utils.h | 141 |
12 files changed, 6945 insertions, 0 deletions
diff --git a/include/linux/mfd/msm-cdc-pinctrl.h b/include/linux/mfd/msm-cdc-pinctrl.h new file mode 100644 index 000000000000..951b8d4d1ed9 --- /dev/null +++ b/include/linux/mfd/msm-cdc-pinctrl.h @@ -0,0 +1,41 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MFD_CDC_PINCTRL_H_ +#define __MFD_CDC_PINCTRL_H_ + +#include <linux/types.h> +#include <linux/of.h> + +#ifdef CONFIG_MSM_CDC_PINCTRL +extern int msm_cdc_pinctrl_select_sleep_state(struct device_node *); +extern int msm_cdc_pinctrl_select_active_state(struct device_node *); +extern bool msm_cdc_pinctrl_get_state(struct device_node *); +extern int msm_cdc_get_gpio_state(struct device_node *); + +#else +int msm_cdc_pinctrl_select_sleep_state(struct device_node *np) +{ + return 0; +} +int msm_cdc_pinctrl_select_active_state(struct device_node *np) +{ + return 0; +} +int msm_cdc_get_gpio_state(struct device_node *np) +{ + return 0; +} +# +#endif + +#endif diff --git a/include/linux/mfd/msm-cdc-supply.h b/include/linux/mfd/msm-cdc-supply.h new file mode 100644 index 000000000000..b40f44b1f12f --- /dev/null +++ b/include/linux/mfd/msm-cdc-supply.h @@ -0,0 +1,48 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CODEC_POWER_SUPPLY_H__ +#define __CODEC_POWER_SUPPLY_H__ + +#include <linux/kernel.h> +#include <linux/slab.h> +#include <linux/regulator/consumer.h> + +struct cdc_regulator { + const char *name; + int min_uV; + int max_uV; + int optimum_uA; + bool ondemand; + struct regulator *regulator; +}; + +extern int msm_cdc_get_power_supplies(struct device *dev, + struct cdc_regulator **cdc_vreg, + int *total_num_supplies); +extern int msm_cdc_disable_static_supplies(struct device *dev, + struct regulator_bulk_data *supplies, + struct cdc_regulator *cdc_vreg, + int num_supplies); +extern int msm_cdc_release_supplies(struct device *dev, + struct regulator_bulk_data *supplies, + struct cdc_regulator *cdc_vreg, + int num_supplies); +extern int msm_cdc_enable_static_supplies(struct device *dev, + struct regulator_bulk_data *supplies, + struct cdc_regulator *cdc_vreg, + int num_supplies); +extern int msm_cdc_init_supplies(struct device *dev, + struct regulator_bulk_data **supplies, + struct cdc_regulator *cdc_vreg, + int num_supplies); +#endif diff --git a/include/linux/mfd/wcd9335/registers.h b/include/linux/mfd/wcd9335/registers.h new file mode 100755 index 000000000000..c50430d4278f --- /dev/null +++ b/include/linux/mfd/wcd9335/registers.h @@ -0,0 +1,1348 @@ +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _WCD9335_REGISTERS_H +#define _WCD9335_REGISTERS_H + +#define WCD9335_PAGE_SIZE 256 +#define WCD9335_NUM_PAGES 256 + +extern const u8 *wcd9335_reg[WCD9335_NUM_PAGES]; + +enum { + PAGE_0 = 0, + PAGE_1, + PAGE_2, + PAGE_6 = 6, + PAGE_10 = 0xA, + PAGE_11, + PAGE_12, + PAGE_13, + PAGE_0X80, +}; + +/* Page-0 Registers */ +#define WCD9335_PAGE0_PAGE_REGISTER 0x0000 +#define WCD9335_CODEC_RPM_CLK_BYPASS 0x0001 +#define WCD9335_CODEC_RPM_CLK_GATE 0x0002 +#define WCD9335_CODEC_RPM_CLK_MCLK_CFG 0x0003 +#define WCD9335_CODEC_RPM_RST_CTL 0x0009 +#define WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL 0x0011 +#define WCD9335_CODEC_RPM_PWR_CPE_DEEPSLP_1 0x0012 +#define WCD9335_CODEC_RPM_PWR_CPE_DEEPSLP_2 0x0013 +#define WCD9335_CODEC_RPM_PWR_CPE_DEEPSLP_3 0x0014 +#define WCD9335_CODEC_RPM_PWR_CPE_IRAM_SHUTDOWN 0x0015 +#define WCD9335_CODEC_RPM_PWR_CPE_DRAM1_SHUTDOWN 0x0016 +#define WCD9335_CODEC_RPM_PWR_CPE_DRAM0_SHUTDOWN_1 0x0017 +#define WCD9335_CODEC_RPM_PWR_CPE_DRAM0_SHUTDOWN_2 0x0018 +#define WCD9335_CODEC_RPM_INT_MASK 0x001d +#define WCD9335_CODEC_RPM_INT_STATUS 0x001e +#define WCD9335_CODEC_RPM_INT_CLEAR 0x001f +#define WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0 0x0021 +#define WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE1 0x0022 +#define WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE2 0x0023 +#define WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE3 0x0024 +#define WCD9335_CHIP_TIER_CTRL_EFUSE_CTL 0x0025 +#define WCD9335_CHIP_TIER_CTRL_EFUSE_TEST0 0x0026 +#define WCD9335_CHIP_TIER_CTRL_EFUSE_TEST1 0x0027 +#define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0 0x0029 +#define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 0x002a +#define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 0x002b +#define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT3 0x002c +#define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT4 0x002d +#define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT5 0x002e +#define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT6 0x002f +#define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT7 0x0030 +#define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT8 0x0031 +#define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT9 0x0032 +#define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT10 0x0033 +#define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT11 0x0034 +#define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT12 0x0035 +#define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT13 0x0036 +#define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT14 0x0037 +#define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT15 0x0038 +#define WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS 0x0039 +#define WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_NONNEGO 0x003a +#define WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_1 0x003b +#define WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_2 0x003c +#define WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_3 0x003d +#define WCD9335_CHIP_TIER_CTRL_ANA_WAIT_STATE_CTL 0x003e +#define WCD9335_CHIP_TIER_CTRL_I2C_ACTIVE 0x003f +#define WCD9335_CHIP_TIER_CTRL_PROC1_MON_CTL 0x0041 +#define WCD9335_CHIP_TIER_CTRL_PROC1_MON_STATUS 0x0042 +#define WCD9335_CHIP_TIER_CTRL_PROC1_MON_CNT_MSB 0x0043 +#define WCD9335_CHIP_TIER_CTRL_PROC1_MON_CNT_LSB 0x0044 +#define WCD9335_CHIP_TIER_CTRL_PROC2_MON_CTL 0x0045 +#define WCD9335_CHIP_TIER_CTRL_PROC2_MON_STATUS 0x0046 +#define WCD9335_CHIP_TIER_CTRL_PROC2_MON_CNT_MSB 0x0047 +#define WCD9335_CHIP_TIER_CTRL_PROC2_MON_CNT_LSB 0x0048 +#define WCD9335_CHIP_TIER_CTRL_PROC3_MON_CTL 0x0049 +#define WCD9335_CHIP_TIER_CTRL_PROC3_MON_STATUS 0x004a +#define WCD9335_CHIP_TIER_CTRL_PROC3_MON_CNT_MSB 0x004b +#define WCD9335_CHIP_TIER_CTRL_PROC3_MON_CNT_LSB 0x004c +#define WCD9335_DATA_HUB_DATA_HUB_RX_I2S_CTL 0x0051 +#define WCD9335_DATA_HUB_DATA_HUB_TX_I2S_CTL 0x0052 +#define WCD9335_DATA_HUB_DATA_HUB_I2S_CLK 0x0053 +#define WCD9335_DATA_HUB_DATA_HUB_RX0_INP_CFG 0x0054 +#define WCD9335_DATA_HUB_DATA_HUB_RX1_INP_CFG 0x0055 +#define WCD9335_DATA_HUB_DATA_HUB_RX2_INP_CFG 0x0056 +#define WCD9335_DATA_HUB_DATA_HUB_RX3_INP_CFG 0x0057 +#define WCD9335_DATA_HUB_DATA_HUB_RX4_INP_CFG 0x0058 +#define WCD9335_DATA_HUB_DATA_HUB_RX5_INP_CFG 0x0059 +#define WCD9335_DATA_HUB_DATA_HUB_RX6_INP_CFG 0x005a +#define WCD9335_DATA_HUB_DATA_HUB_RX7_INP_CFG 0x005b +#define WCD9335_DATA_HUB_DATA_HUB_SB_TX0_INP_CFG 0x0061 +#define WCD9335_DATA_HUB_DATA_HUB_SB_TX1_INP_CFG 0x0062 +#define WCD9335_DATA_HUB_DATA_HUB_SB_TX2_INP_CFG 0x0063 +#define WCD9335_DATA_HUB_DATA_HUB_SB_TX3_INP_CFG 0x0064 +#define WCD9335_DATA_HUB_DATA_HUB_SB_TX4_INP_CFG 0x0065 +#define WCD9335_DATA_HUB_DATA_HUB_SB_TX5_INP_CFG 0x0066 +#define WCD9335_DATA_HUB_DATA_HUB_SB_TX6_INP_CFG 0x0067 +#define WCD9335_DATA_HUB_DATA_HUB_SB_TX7_INP_CFG 0x0068 +#define WCD9335_DATA_HUB_DATA_HUB_SB_TX8_INP_CFG 0x0069 +#define WCD9335_DATA_HUB_DATA_HUB_SB_TX9_INP_CFG 0x006a +#define WCD9335_DATA_HUB_DATA_HUB_SB_TX10_INP_CFG 0x006b +#define WCD9335_DATA_HUB_DATA_HUB_SB_TX11_INP_CFG 0x006c +#define WCD9335_DATA_HUB_DATA_HUB_SB_TX13_INP_CFG 0x006e +#define WCD9335_DATA_HUB_DATA_HUB_SB_TX14_INP_CFG 0x006f +#define WCD9335_DATA_HUB_DATA_HUB_SB_TX15_INP_CFG 0x0070 +#define WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD0_L_CFG 0x0071 +#define WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD0_R_CFG 0x0072 +#define WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_L_CFG 0x0073 +#define WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_R_CFG 0x0074 +#define WCD9335_DATA_HUB_NATIVE_FIFO_SYNC 0x0075 +#define WCD9335_DATA_HUB_NATIVE_FIFO_STATUS 0x007D +#define WCD9335_INTR_CFG 0x0081 +#define WCD9335_INTR_CLR_COMMIT 0x0082 +#define WCD9335_INTR_PIN1_MASK0 0x0089 +#define WCD9335_INTR_PIN1_MASK1 0x008a +#define WCD9335_INTR_PIN1_MASK2 0x008b +#define WCD9335_INTR_PIN1_MASK3 0x008c +#define WCD9335_INTR_PIN1_STATUS0 0x0091 +#define WCD9335_INTR_PIN1_STATUS1 0x0092 +#define WCD9335_INTR_PIN1_STATUS2 0x0093 +#define WCD9335_INTR_PIN1_STATUS3 0x0094 +#define WCD9335_INTR_PIN1_CLEAR0 0x0099 +#define WCD9335_INTR_PIN1_CLEAR1 0x009a +#define WCD9335_INTR_PIN1_CLEAR2 0x009b +#define WCD9335_INTR_PIN1_CLEAR3 0x009c +#define WCD9335_INTR_PIN2_MASK0 0x00a1 +#define WCD9335_INTR_PIN2_MASK1 0x00a2 +#define WCD9335_INTR_PIN2_MASK2 0x00a3 +#define WCD9335_INTR_PIN2_MASK3 0x00a4 +#define WCD9335_INTR_PIN2_STATUS0 0x00a9 +#define WCD9335_INTR_PIN2_STATUS1 0x00aa +#define WCD9335_INTR_PIN2_STATUS2 0x00ab +#define WCD9335_INTR_PIN2_STATUS3 0x00ac +#define WCD9335_INTR_PIN2_CLEAR0 0x00b1 +#define WCD9335_INTR_PIN2_CLEAR1 0x00b2 +#define WCD9335_INTR_PIN2_CLEAR2 0x00b3 +#define WCD9335_INTR_PIN2_CLEAR3 0x00b4 +#define WCD9335_INTR_LEVEL0 0x00e1 +#define WCD9335_INTR_LEVEL1 0x00e2 +#define WCD9335_INTR_LEVEL2 0x00e3 +#define WCD9335_INTR_LEVEL3 0x00e4 +#define WCD9335_INTR_BYPASS0 0x00e9 +#define WCD9335_INTR_BYPASS1 0x00ea +#define WCD9335_INTR_BYPASS2 0x00eb +#define WCD9335_INTR_BYPASS3 0x00ec +#define WCD9335_INTR_SET0 0x00f1 +#define WCD9335_INTR_SET1 0x00f2 +#define WCD9335_INTR_SET2 0x00f3 +#define WCD9335_INTR_SET3 0x00f4 + +/* Page-1 Registers */ +#define WCD9335_PAGE1_PAGE_REGISTER 0x0100 +#define WCD9335_CPE_FLL_USER_CTL_0 0x0101 +#define WCD9335_CPE_FLL_USER_CTL_1 0x0102 +#define WCD9335_CPE_FLL_USER_CTL_2 0x0103 +#define WCD9335_CPE_FLL_USER_CTL_3 0x0104 +#define WCD9335_CPE_FLL_USER_CTL_4 0x0105 +#define WCD9335_CPE_FLL_USER_CTL_5 0x0106 +#define WCD9335_CPE_FLL_USER_CTL_6 0x0107 +#define WCD9335_CPE_FLL_USER_CTL_7 0x0108 +#define WCD9335_CPE_FLL_USER_CTL_8 0x0109 +#define WCD9335_CPE_FLL_USER_CTL_9 0x010a +#define WCD9335_CPE_FLL_L_VAL_CTL_0 0x010b +#define WCD9335_CPE_FLL_L_VAL_CTL_1 0x010c +#define WCD9335_CPE_FLL_DSM_FRAC_CTL_0 0x010d +#define WCD9335_CPE_FLL_DSM_FRAC_CTL_1 0x010e +#define WCD9335_CPE_FLL_CONFIG_CTL_0 0x010f +#define WCD9335_CPE_FLL_CONFIG_CTL_1 0x0110 +#define WCD9335_CPE_FLL_CONFIG_CTL_2 0x0111 +#define WCD9335_CPE_FLL_CONFIG_CTL_3 0x0112 +#define WCD9335_CPE_FLL_CONFIG_CTL_4 0x0113 +#define WCD9335_CPE_FLL_TEST_CTL_0 0x0114 +#define WCD9335_CPE_FLL_TEST_CTL_1 0x0115 +#define WCD9335_CPE_FLL_TEST_CTL_2 0x0116 +#define WCD9335_CPE_FLL_TEST_CTL_3 0x0117 +#define WCD9335_CPE_FLL_TEST_CTL_4 0x0118 +#define WCD9335_CPE_FLL_TEST_CTL_5 0x0119 +#define WCD9335_CPE_FLL_TEST_CTL_6 0x011a +#define WCD9335_CPE_FLL_TEST_CTL_7 0x011b +#define WCD9335_CPE_FLL_FREQ_CTL_0 0x011c +#define WCD9335_CPE_FLL_FREQ_CTL_1 0x011d +#define WCD9335_CPE_FLL_FREQ_CTL_2 0x011e +#define WCD9335_CPE_FLL_FREQ_CTL_3 0x011f +#define WCD9335_CPE_FLL_SSC_CTL_0 0x0120 +#define WCD9335_CPE_FLL_SSC_CTL_1 0x0121 +#define WCD9335_CPE_FLL_SSC_CTL_2 0x0122 +#define WCD9335_CPE_FLL_SSC_CTL_3 0x0123 +#define WCD9335_CPE_FLL_FLL_MODE 0x0124 +#define WCD9335_CPE_FLL_STATUS_0 0x0125 +#define WCD9335_CPE_FLL_STATUS_1 0x0126 +#define WCD9335_CPE_FLL_STATUS_2 0x0127 +#define WCD9335_CPE_FLL_STATUS_3 0x0128 +#define WCD9335_I2S_FLL_USER_CTL_0 0x0141 +#define WCD9335_I2S_FLL_USER_CTL_1 0x0142 +#define WCD9335_I2S_FLL_USER_CTL_2 0x0143 +#define WCD9335_I2S_FLL_USER_CTL_3 0x0144 +#define WCD9335_I2S_FLL_USER_CTL_4 0x0145 +#define WCD9335_I2S_FLL_USER_CTL_5 0x0146 +#define WCD9335_I2S_FLL_USER_CTL_6 0x0147 +#define WCD9335_I2S_FLL_USER_CTL_7 0x0148 +#define WCD9335_I2S_FLL_USER_CTL_8 0x0149 +#define WCD9335_I2S_FLL_USER_CTL_9 0x014a +#define WCD9335_I2S_FLL_L_VAL_CTL_0 0x014b +#define WCD9335_I2S_FLL_L_VAL_CTL_1 0x014c +#define WCD9335_I2S_FLL_DSM_FRAC_CTL_0 0x014d +#define WCD9335_I2S_FLL_DSM_FRAC_CTL_1 0x014e +#define WCD9335_I2S_FLL_CONFIG_CTL_0 0x014f +#define WCD9335_I2S_FLL_CONFIG_CTL_1 0x0150 +#define WCD9335_I2S_FLL_CONFIG_CTL_2 0x0151 +#define WCD9335_I2S_FLL_CONFIG_CTL_3 0x0152 +#define WCD9335_I2S_FLL_CONFIG_CTL_4 0x0153 +#define WCD9335_I2S_FLL_TEST_CTL_0 0x0154 +#define WCD9335_I2S_FLL_TEST_CTL_1 0x0155 +#define WCD9335_I2S_FLL_TEST_CTL_2 0x0156 +#define WCD9335_I2S_FLL_TEST_CTL_3 0x0157 +#define WCD9335_I2S_FLL_TEST_CTL_4 0x0158 +#define WCD9335_I2S_FLL_TEST_CTL_5 0x0159 +#define WCD9335_I2S_FLL_TEST_CTL_6 0x015a +#define WCD9335_I2S_FLL_TEST_CTL_7 0x015b +#define WCD9335_I2S_FLL_FREQ_CTL_0 0x015c +#define WCD9335_I2S_FLL_FREQ_CTL_1 0x015d +#define WCD9335_I2S_FLL_FREQ_CTL_2 0x015e +#define WCD9335_I2S_FLL_FREQ_CTL_3 0x015f +#define WCD9335_I2S_FLL_SSC_CTL_0 0x0160 +#define WCD9335_I2S_FLL_SSC_CTL_1 0x0161 +#define WCD9335_I2S_FLL_SSC_CTL_2 0x0162 +#define WCD9335_I2S_FLL_SSC_CTL_3 0x0163 +#define WCD9335_I2S_FLL_FLL_MODE 0x0164 +#define WCD9335_I2S_FLL_STATUS_0 0x0165 +#define WCD9335_I2S_FLL_STATUS_1 0x0166 +#define WCD9335_I2S_FLL_STATUS_2 0x0167 +#define WCD9335_I2S_FLL_STATUS_3 0x0168 +#define WCD9335_SB_FLL_USER_CTL_0 0x0181 +#define WCD9335_SB_FLL_USER_CTL_1 0x0182 +#define WCD9335_SB_FLL_USER_CTL_2 0x0183 +#define WCD9335_SB_FLL_USER_CTL_3 0x0184 +#define WCD9335_SB_FLL_USER_CTL_4 0x0185 +#define WCD9335_SB_FLL_USER_CTL_5 0x0186 +#define WCD9335_SB_FLL_USER_CTL_6 0x0187 +#define WCD9335_SB_FLL_USER_CTL_7 0x0188 +#define WCD9335_SB_FLL_USER_CTL_8 0x0189 +#define WCD9335_SB_FLL_USER_CTL_9 0x018a +#define WCD9335_SB_FLL_L_VAL_CTL_0 0x018b +#define WCD9335_SB_FLL_L_VAL_CTL_1 0x018c +#define WCD9335_SB_FLL_DSM_FRAC_CTL_0 0x018d +#define WCD9335_SB_FLL_DSM_FRAC_CTL_1 0x018e +#define WCD9335_SB_FLL_CONFIG_CTL_0 0x018f +#define WCD9335_SB_FLL_CONFIG_CTL_1 0x0190 +#define WCD9335_SB_FLL_CONFIG_CTL_2 0x0191 +#define WCD9335_SB_FLL_CONFIG_CTL_3 0x0192 +#define WCD9335_SB_FLL_CONFIG_CTL_4 0x0193 +#define WCD9335_SB_FLL_TEST_CTL_0 0x0194 +#define WCD9335_SB_FLL_TEST_CTL_1 0x0195 +#define WCD9335_SB_FLL_TEST_CTL_2 0x0196 +#define WCD9335_SB_FLL_TEST_CTL_3 0x0197 +#define WCD9335_SB_FLL_TEST_CTL_4 0x0198 +#define WCD9335_SB_FLL_TEST_CTL_5 0x0199 +#define WCD9335_SB_FLL_TEST_CTL_6 0x019a +#define WCD9335_SB_FLL_TEST_CTL_7 0x019b +#define WCD9335_SB_FLL_FREQ_CTL_0 0x019c +#define WCD9335_SB_FLL_FREQ_CTL_1 0x019d +#define WCD9335_SB_FLL_FREQ_CTL_2 0x019e +#define WCD9335_SB_FLL_FREQ_CTL_3 0x019f +#define WCD9335_SB_FLL_SSC_CTL_0 0x01a0 +#define WCD9335_SB_FLL_SSC_CTL_1 0x01a1 +#define WCD9335_SB_FLL_SSC_CTL_2 0x01a2 +#define WCD9335_SB_FLL_SSC_CTL_3 0x01a3 +#define WCD9335_SB_FLL_FLL_MODE 0x01a4 +#define WCD9335_SB_FLL_STATUS_0 0x01a5 +#define WCD9335_SB_FLL_STATUS_1 0x01a6 +#define WCD9335_SB_FLL_STATUS_2 0x01a7 +#define WCD9335_SB_FLL_STATUS_3 0x01a8 + +/* Page-2 Registers */ +#define WCD9335_PAGE2_PAGE_REGISTER 0x0200 +#define WCD9335_CPE_SS_MEM_PTR_0 0x0201 +#define WCD9335_CPE_SS_MEM_PTR_1 0x0202 +#define WCD9335_CPE_SS_MEM_PTR_2 0x0203 +#define WCD9335_CPE_SS_MEM_CTRL 0x0205 +#define WCD9335_CPE_SS_MEM_BANK_0 0x0206 +#define WCD9335_CPE_SS_MEM_BANK_1 0x0207 +#define WCD9335_CPE_SS_MEM_BANK_2 0x0208 +#define WCD9335_CPE_SS_MEM_BANK_3 0x0209 +#define WCD9335_CPE_SS_MEM_BANK_4 0x020a +#define WCD9335_CPE_SS_MEM_BANK_5 0x020b +#define WCD9335_CPE_SS_MEM_BANK_6 0x020c +#define WCD9335_CPE_SS_MEM_BANK_7 0x020d +#define WCD9335_CPE_SS_MEM_BANK_8 0x020e +#define WCD9335_CPE_SS_MEM_BANK_9 0x020f +#define WCD9335_CPE_SS_MEM_BANK_10 0x0210 +#define WCD9335_CPE_SS_MEM_BANK_11 0x0211 +#define WCD9335_CPE_SS_MEM_BANK_12 0x0212 +#define WCD9335_CPE_SS_MEM_BANK_13 0x0213 +#define WCD9335_CPE_SS_MEM_BANK_14 0x0214 +#define WCD9335_CPE_SS_MEM_BANK_15 0x0215 +#define WCD9335_CPE_SS_INBOX1_TRG 0x0216 +#define WCD9335_CPE_SS_INBOX2_TRG 0x0217 +#define WCD9335_CPE_SS_INBOX1_0 0x0218 +#define WCD9335_CPE_SS_INBOX1_1 0x0219 +#define WCD9335_CPE_SS_INBOX1_2 0x021a +#define WCD9335_CPE_SS_INBOX1_3 0x021b +#define WCD9335_CPE_SS_INBOX1_4 0x021c +#define WCD9335_CPE_SS_INBOX1_5 0x021d +#define WCD9335_CPE_SS_INBOX1_6 0x021e +#define WCD9335_CPE_SS_INBOX1_7 0x021f +#define WCD9335_CPE_SS_INBOX1_8 0x0220 +#define WCD9335_CPE_SS_INBOX1_9 0x0221 +#define WCD9335_CPE_SS_INBOX1_10 0x0222 +#define WCD9335_CPE_SS_INBOX1_11 0x0223 +#define WCD9335_CPE_SS_INBOX1_12 0x0224 +#define WCD9335_CPE_SS_INBOX1_13 0x0225 +#define WCD9335_CPE_SS_INBOX1_14 0x0226 +#define WCD9335_CPE_SS_INBOX1_15 0x0227 +#define WCD9335_CPE_SS_OUTBOX1_0 0x0228 +#define WCD9335_CPE_SS_OUTBOX1_1 0x0229 +#define WCD9335_CPE_SS_OUTBOX1_2 0x022a +#define WCD9335_CPE_SS_OUTBOX1_3 0x022b +#define WCD9335_CPE_SS_OUTBOX1_4 0x022c +#define WCD9335_CPE_SS_OUTBOX1_5 0x022d +#define WCD9335_CPE_SS_OUTBOX1_6 0x022e +#define WCD9335_CPE_SS_OUTBOX1_7 0x022f +#define WCD9335_CPE_SS_OUTBOX1_8 0x0230 +#define WCD9335_CPE_SS_OUTBOX1_9 0x0231 +#define WCD9335_CPE_SS_OUTBOX1_10 0x0232 +#define WCD9335_CPE_SS_OUTBOX1_11 0x0233 +#define WCD9335_CPE_SS_OUTBOX1_12 0x0234 +#define WCD9335_CPE_SS_OUTBOX1_13 0x0235 +#define WCD9335_CPE_SS_OUTBOX1_14 0x0236 +#define WCD9335_CPE_SS_OUTBOX1_15 0x0237 +#define WCD9335_CPE_SS_INBOX2_0 0x0238 +#define WCD9335_CPE_SS_INBOX2_1 0x0239 +#define WCD9335_CPE_SS_INBOX2_2 0x023a +#define WCD9335_CPE_SS_INBOX2_3 0x023b +#define WCD9335_CPE_SS_INBOX2_4 0x023c +#define WCD9335_CPE_SS_INBOX2_5 0x023d +#define WCD9335_CPE_SS_INBOX2_6 0x023e +#define WCD9335_CPE_SS_INBOX2_7 0x023f +#define WCD9335_CPE_SS_INBOX2_8 0x0240 +#define WCD9335_CPE_SS_INBOX2_9 0x0241 +#define WCD9335_CPE_SS_INBOX2_10 0x0242 +#define WCD9335_CPE_SS_INBOX2_11 0x0243 +#define WCD9335_CPE_SS_INBOX2_12 0x0244 +#define WCD9335_CPE_SS_INBOX2_13 0x0245 +#define WCD9335_CPE_SS_INBOX2_14 0x0246 +#define WCD9335_CPE_SS_INBOX2_15 0x0247 +#define WCD9335_CPE_SS_OUTBOX2_0 0x0248 +#define WCD9335_CPE_SS_OUTBOX2_1 0x0249 +#define WCD9335_CPE_SS_OUTBOX2_2 0x024a +#define WCD9335_CPE_SS_OUTBOX2_3 0x024b +#define WCD9335_CPE_SS_OUTBOX2_4 0x024c +#define WCD9335_CPE_SS_OUTBOX2_5 0x024d +#define WCD9335_CPE_SS_OUTBOX2_6 0x024e +#define WCD9335_CPE_SS_OUTBOX2_7 0x024f +#define WCD9335_CPE_SS_OUTBOX2_8 0x0250 +#define WCD9335_CPE_SS_OUTBOX2_9 0x0251 +#define WCD9335_CPE_SS_OUTBOX2_10 0x0252 +#define WCD9335_CPE_SS_OUTBOX2_11 0x0253 +#define WCD9335_CPE_SS_OUTBOX2_12 0x0254 +#define WCD9335_CPE_SS_OUTBOX2_13 0x0255 +#define WCD9335_CPE_SS_OUTBOX2_14 0x0256 +#define WCD9335_CPE_SS_OUTBOX2_15 0x0257 +#define WCD9335_CPE_SS_OUTBOX1_ACK 0x0258 +#define WCD9335_CPE_SS_OUTBOX2_ACK 0x0259 +#define WCD9335_CPE_SS_EC_BUF_INT_PERIOD 0x025a +#define WCD9335_CPE_SS_US_BUF_INT_PERIOD 0x025b +#define WCD9335_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD 0x025c +#define WCD9335_CPE_SS_CFG 0x025d +#define WCD9335_CPE_SS_US_EC_MUX_CFG 0x025e +#define WCD9335_CPE_SS_MAD_CTL 0x025f +#define WCD9335_CPE_SS_CPAR_CTL 0x0260 +#define WCD9335_CPE_SS_TX_PP_BUF_INT_PERIOD 0x0261 +#define WCD9335_CPE_SS_TX_PP_CFG 0x0262 +#define WCD9335_CPE_SS_DMIC0_CTL 0x0263 +#define WCD9335_CPE_SS_DMIC1_CTL 0x0264 +#define WCD9335_CPE_SS_DMIC2_CTL 0x0265 +#define WCD9335_CPE_SS_DMIC_CFG 0x0266 +#define WCD9335_CPE_SS_SVA_CFG 0x0267 +#define WCD9335_CPE_SS_CPAR_CFG 0x0271 +#define WCD9335_CPE_SS_WDOG_CFG 0x0272 +#define WCD9335_CPE_SS_BACKUP_INT 0x0273 +#define WCD9335_CPE_SS_STATUS 0x0274 +#define WCD9335_CPE_SS_CPE_OCD_CFG 0x0275 +#define WCD9335_CPE_SS_SS_ERROR_INT_MASK 0x0276 +#define WCD9335_CPE_SS_SS_ERROR_INT_STATUS 0x0277 +#define WCD9335_CPE_SS_SS_ERROR_INT_CLEAR 0x0278 +#define WCD9335_SOC_MAD_MAIN_CTL_1 0x0281 +#define WCD9335_SOC_MAD_MAIN_CTL_2 0x0282 +#define WCD9335_SOC_MAD_AUDIO_CTL_1 0x0283 +#define WCD9335_SOC_MAD_AUDIO_CTL_2 0x0284 +#define WCD9335_SOC_MAD_AUDIO_CTL_3 0x0285 +#define WCD9335_SOC_MAD_AUDIO_CTL_4 0x0286 +#define WCD9335_SOC_MAD_AUDIO_CTL_5 0x0287 +#define WCD9335_SOC_MAD_AUDIO_CTL_6 0x0288 +#define WCD9335_SOC_MAD_AUDIO_CTL_7 0x0289 +#define WCD9335_SOC_MAD_AUDIO_CTL_8 0x028a +#define WCD9335_SOC_MAD_AUDIO_IIR_CTL_PTR 0x028b +#define WCD9335_SOC_MAD_AUDIO_IIR_CTL_VAL 0x028c +#define WCD9335_SOC_MAD_ULTR_CTL_1 0x028d +#define WCD9335_SOC_MAD_ULTR_CTL_2 0x028e +#define WCD9335_SOC_MAD_ULTR_CTL_3 0x028f +#define WCD9335_SOC_MAD_ULTR_CTL_4 0x0290 +#define WCD9335_SOC_MAD_ULTR_CTL_5 0x0291 +#define WCD9335_SOC_MAD_ULTR_CTL_6 0x0292 +#define WCD9335_SOC_MAD_ULTR_CTL_7 0x0293 +#define WCD9335_SOC_MAD_BEACON_CTL_1 0x0294 +#define WCD9335_SOC_MAD_BEACON_CTL_2 0x0295 +#define WCD9335_SOC_MAD_BEACON_CTL_3 0x0296 +#define WCD9335_SOC_MAD_BEACON_CTL_4 0x0297 +#define WCD9335_SOC_MAD_BEACON_CTL_5 0x0298 +#define WCD9335_SOC_MAD_BEACON_CTL_6 0x0299 +#define WCD9335_SOC_MAD_BEACON_CTL_7 0x029a +#define WCD9335_SOC_MAD_BEACON_CTL_8 0x029b +#define WCD9335_SOC_MAD_BEACON_IIR_CTL_PTR 0x029c +#define WCD9335_SOC_MAD_BEACON_IIR_CTL_VAL 0x029d +#define WCD9335_SOC_MAD_INP_SEL 0x029e + +/* Page-6 Registers */ +#define WCD9335_PAGE6_PAGE_REGISTER 0x0600 +#define WCD9335_ANA_BIAS 0x0601 +#define WCD9335_ANA_CLK_TOP 0x0602 +#define WCD9335_ANA_RCO 0x0603 +#define WCD9335_ANA_BUCK_VOUT_A 0x0604 +#define WCD9335_ANA_BUCK_VOUT_D 0x0605 +#define WCD9335_ANA_BUCK_CTL 0x0606 +#define WCD9335_ANA_BUCK_STATUS 0x0607 +#define WCD9335_ANA_RX_SUPPLIES 0x0608 +#define WCD9335_ANA_HPH 0x0609 +#define WCD9335_ANA_EAR 0x060a +#define WCD9335_ANA_LO_1_2 0x060b +#define WCD9335_ANA_LO_3_4 0x060c +#define WCD9335_ANA_MAD_SETUP 0x060d +#define WCD9335_ANA_AMIC1 0x060e +#define WCD9335_ANA_AMIC2 0x060f +#define WCD9335_ANA_AMIC3 0x0610 +#define WCD9335_ANA_AMIC4 0x0611 +#define WCD9335_ANA_AMIC5 0x0612 +#define WCD9335_ANA_AMIC6 0x0613 +#define WCD9335_ANA_MBHC_MECH 0x0614 +#define WCD9335_ANA_MBHC_ELECT 0x0615 +#define WCD9335_ANA_MBHC_ZDET 0x0616 +#define WCD9335_ANA_MBHC_RESULT_1 0x0617 +#define WCD9335_ANA_MBHC_RESULT_2 0x0618 +#define WCD9335_ANA_MBHC_RESULT_3 0x0619 +#define WCD9335_ANA_MBHC_BTN0 0x061a +#define WCD9335_ANA_MBHC_BTN1 0x061b +#define WCD9335_ANA_MBHC_BTN2 0x061c +#define WCD9335_ANA_MBHC_BTN3 0x061d +#define WCD9335_ANA_MBHC_BTN4 0x061e +#define WCD9335_ANA_MBHC_BTN5 0x061f +#define WCD9335_ANA_MBHC_BTN6 0x0620 +#define WCD9335_ANA_MBHC_BTN7 0x0621 +#define WCD9335_ANA_MICB1 0x0622 +#define WCD9335_ANA_MICB2 0x0623 +#define WCD9335_ANA_MICB2_RAMP 0x0624 +#define WCD9335_ANA_MICB3 0x0625 +#define WCD9335_ANA_MICB4 0x0626 +#define WCD9335_ANA_VBADC 0x0627 +#define WCD9335_BIAS_CTL 0x0628 +#define WCD9335_BIAS_VBG_FINE_ADJ 0x0629 +#define WCD9335_CLOCK_TEST_CTL 0x062d +#define WCD9335_RCO_CTRL_1 0x062e +#define WCD9335_RCO_CTRL_2 0x062f +#define WCD9335_RCO_CAL 0x0630 +#define WCD9335_RCO_CAL_1 0x0631 +#define WCD9335_RCO_CAL_2 0x0632 +#define WCD9335_RCO_TEST_CTRL 0x0633 +#define WCD9335_RCO_CAL_OUT_1 0x0634 +#define WCD9335_RCO_CAL_OUT_2 0x0635 +#define WCD9335_RCO_CAL_OUT_3 0x0636 +#define WCD9335_RCO_CAL_OUT_4 0x0637 +#define WCD9335_RCO_CAL_OUT_5 0x0638 +#define WCD9335_SIDO_SIDO_MODE_1 0x063a +#define WCD9335_SIDO_SIDO_MODE_2 0x063b +#define WCD9335_SIDO_SIDO_MODE_3 0x063c +#define WCD9335_SIDO_SIDO_MODE_4 0x063d +#define WCD9335_SIDO_SIDO_VCL_1 0x063e +#define WCD9335_SIDO_SIDO_VCL_2 0x063f +#define WCD9335_SIDO_SIDO_VCL_3 0x0640 +#define WCD9335_SIDO_SIDO_CCL_1 0x0641 +#define WCD9335_SIDO_SIDO_CCL_2 0x0642 +#define WCD9335_SIDO_SIDO_CCL_3 0x0643 +#define WCD9335_SIDO_SIDO_CCL_4 0x0644 +#define WCD9335_SIDO_SIDO_CCL_5 0x0645 +#define WCD9335_SIDO_SIDO_CCL_6 0x0646 +#define WCD9335_SIDO_SIDO_CCL_7 0x0647 +#define WCD9335_SIDO_SIDO_CCL_8 0x0648 +#define WCD9335_SIDO_SIDO_CCL_9 0x0649 +#define WCD9335_SIDO_SIDO_CCL_10 0x064a +#define WCD9335_SIDO_SIDO_FILTER_1 0x064b +#define WCD9335_SIDO_SIDO_FILTER_2 0x064c +#define WCD9335_SIDO_SIDO_DRIVER_1 0x064d +#define WCD9335_SIDO_SIDO_DRIVER_2 0x064e +#define WCD9335_SIDO_SIDO_DRIVER_3 0x064f +#define WCD9335_SIDO_SIDO_CAL_CODE_EXT_1 0x0650 +#define WCD9335_SIDO_SIDO_CAL_CODE_EXT_2 0x0651 +#define WCD9335_SIDO_SIDO_CAL_CODE_OUT_1 0x0652 +#define WCD9335_SIDO_SIDO_CAL_CODE_OUT_2 0x0653 +#define WCD9335_SIDO_SIDO_TEST_1 0x0654 +#define WCD9335_SIDO_SIDO_TEST_2 0x0655 +#define WCD9335_MBHC_CTL_1 0x0656 +#define WCD9335_MBHC_CTL_2 0x0657 +#define WCD9335_MBHC_PLUG_DETECT_CTL 0x0658 +#define WCD9335_MBHC_ZDET_ANA_CTL 0x0659 +#define WCD9335_MBHC_ZDET_RAMP_CTL 0x065a +#define WCD9335_MBHC_FSM_DEBUG 0x065b /* v1.x */ +#define WCD9335_MBHC_FSM_STATUS 0x065b /* v2.0 */ +#define WCD9335_MBHC_TEST_CTL 0x065c +#define WCD9335_VBADC_SUBBLOCK_EN 0x065d +#define WCD9335_VBADC_IBIAS_FE 0x065e +#define WCD9335_VBADC_BIAS_ADC 0x065f +#define WCD9335_VBADC_FE_CTRL 0x0660 +#define WCD9335_VBADC_ADC_REF 0x0661 +#define WCD9335_VBADC_ADC_IO 0x0662 +#define WCD9335_VBADC_ADC_SAR 0x0663 +#define WCD9335_VBADC_DEBUG 0x0664 +#define WCD9335_VBADC_ADC_DOUTMSB 0x0665 +#define WCD9335_VBADC_ADC_DOUTLSB 0x0666 +#define WCD9335_LDOH_MODE 0x0667 +#define WCD9335_LDOH_BIAS 0x0668 +#define WCD9335_LDOH_STB_LOADS 0x0669 +#define WCD9335_LDOH_SLOWRAMP 0x066a +#define WCD9335_MICB1_TEST_CTL_1 0x066b +#define WCD9335_MICB1_TEST_CTL_2 0x066c +#define WCD9335_MICB1_TEST_CTL_3 0x066d +#define WCD9335_MICB2_TEST_CTL_1 0x066e +#define WCD9335_MICB2_TEST_CTL_2 0x066f +#define WCD9335_MICB2_TEST_CTL_3 0x0670 +#define WCD9335_MICB3_TEST_CTL_1 0x0671 +#define WCD9335_MICB3_TEST_CTL_2 0x0672 +#define WCD9335_MICB3_TEST_CTL_3 0x0673 +#define WCD9335_MICB4_TEST_CTL_1 0x0674 +#define WCD9335_MICB4_TEST_CTL_2 0x0675 +#define WCD9335_MICB4_TEST_CTL_3 0x0676 +#define WCD9335_TX_COM_ADC_VCM 0x0677 +#define WCD9335_TX_COM_BIAS_ATEST 0x0678 +#define WCD9335_TX_COM_ADC_INT1_IB 0x0679 +#define WCD9335_TX_COM_ADC_INT2_IB 0x067a +#define WCD9335_TX_COM_TXFE_DIV_CTL 0x067b +#define WCD9335_TX_COM_TXFE_DIV_START 0x067c +#define WCD9335_TX_COM_TXFE_DIV_STOP_9P6M 0x067d +#define WCD9335_TX_COM_TXFE_DIV_STOP_12P288M 0x067e +#define WCD9335_TX_1_2_TEST_EN 0x067f +#define WCD9335_TX_1_2_ADC_IB 0x0680 +#define WCD9335_TX_1_2_ATEST_REFCTL 0x0681 +#define WCD9335_TX_1_2_TEST_CTL 0x0682 +#define WCD9335_TX_1_2_TEST_BLK_EN 0x0683 +#define WCD9335_TX_1_2_TXFE_CLKDIV 0x0684 +#define WCD9335_TX_1_2_SAR1_ERR 0x0685 +#define WCD9335_TX_1_2_SAR2_ERR 0x0686 +#define WCD9335_TX_3_4_TEST_EN 0x0687 +#define WCD9335_TX_3_4_ADC_IB 0x0688 +#define WCD9335_TX_3_4_ATEST_REFCTL 0x0689 +#define WCD9335_TX_3_4_TEST_CTL 0x068a +#define WCD9335_TX_3_4_TEST_BLK_EN 0x068b +#define WCD9335_TX_3_4_TXFE_CLKDIV 0x068c +#define WCD9335_TX_3_4_SAR1_ERR 0x068d +#define WCD9335_TX_3_4_SAR2_ERR 0x068e +#define WCD9335_TX_5_6_TEST_EN 0x068f +#define WCD9335_TX_5_6_ADC_IB 0x0690 +#define WCD9335_TX_5_6_ATEST_REFCTL 0x0691 +#define WCD9335_TX_5_6_TEST_CTL 0x0692 +#define WCD9335_TX_5_6_TEST_BLK_EN 0x0693 +#define WCD9335_TX_5_6_TXFE_CLKDIV 0x0694 +#define WCD9335_TX_5_6_SAR1_ERR 0x0695 +#define WCD9335_TX_5_6_SAR2_ERR 0x0696 +#define WCD9335_CLASSH_MODE_1 0x0697 +#define WCD9335_CLASSH_MODE_2 0x0698 +#define WCD9335_CLASSH_MODE_3 0x0699 +#define WCD9335_CLASSH_CTRL_VCL_1 0x069a +#define WCD9335_CLASSH_CTRL_VCL_2 0x069b +#define WCD9335_CLASSH_CTRL_CCL_1 0x069c +#define WCD9335_CLASSH_CTRL_CCL_2 0x069d +#define WCD9335_CLASSH_CTRL_CCL_3 0x069e +#define WCD9335_CLASSH_CTRL_CCL_4 0x069f +#define WCD9335_CLASSH_CTRL_CCL_5 0x06a0 +#define WCD9335_CLASSH_BUCK_TMUX_A_D 0x06a1 +#define WCD9335_CLASSH_BUCK_SW_DRV_CNTL 0x06a2 +#define WCD9335_CLASSH_SPARE 0x06a3 +#define WCD9335_FLYBACK_EN 0x06a4 +#define WCD9335_FLYBACK_VNEG_CTRL_1 0x06a5 +#define WCD9335_FLYBACK_VNEG_CTRL_2 0x06a6 +#define WCD9335_FLYBACK_VNEG_CTRL_3 0x06a7 +#define WCD9335_FLYBACK_VNEG_CTRL_4 0x06a8 +#define WCD9335_FLYBACK_VNEG_CTRL_5 0x06a9 +#define WCD9335_FLYBACK_VNEG_CTRL_6 0x06aa +#define WCD9335_FLYBACK_VNEG_CTRL_7 0x06ab +#define WCD9335_FLYBACK_VNEG_CTRL_8 0x06ac +#define WCD9335_FLYBACK_VNEG_CTRL_9 0x06ad +#define WCD9335_FLYBACK_VNEG_DAC_CTRL_1 0x06ae +#define WCD9335_FLYBACK_VNEG_DAC_CTRL_2 0x06af +#define WCD9335_FLYBACK_VNEG_DAC_CTRL_3 0x06b0 +#define WCD9335_FLYBACK_VNEG_DAC_CTRL_4 0x06b1 /* v1.x */ +#define WCD9335_FLYBACK_CTRL_1 0x06b1 /* v2.0 */ +#define WCD9335_FLYBACK_TEST_CTL 0x06b2 +#define WCD9335_RX_AUX_SW_CTL 0x06b3 +#define WCD9335_RX_PA_AUX_IN_CONN 0x06b4 +#define WCD9335_RX_TIMER_DIV 0x06b5 +#define WCD9335_RX_OCP_CTL 0x06b6 +#define WCD9335_RX_OCP_COUNT 0x06b7 +#define WCD9335_RX_BIAS_EAR_DAC 0x06b8 +#define WCD9335_RX_BIAS_EAR_AMP 0x06b9 +#define WCD9335_RX_BIAS_HPH_LDO 0x06ba +#define WCD9335_RX_BIAS_HPH_PA 0x06bb +#define WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2 0x06bc +#define WCD9335_RX_BIAS_HPH_RDAC_LDO 0x06bd +#define WCD9335_RX_BIAS_HPH_CNP1 0x06be +#define WCD9335_RX_BIAS_HPH_LOWPOWER 0x06bf +#define WCD9335_RX_BIAS_DIFFLO_PA 0x06c0 +#define WCD9335_RX_BIAS_DIFFLO_REF 0x06c1 +#define WCD9335_RX_BIAS_DIFFLO_LDO 0x06c2 +#define WCD9335_RX_BIAS_SELO_DAC_PA 0x06c3 +#define WCD9335_RX_BIAS_BUCK_RST 0x06c4 +#define WCD9335_RX_BIAS_BUCK_VREF_ERRAMP 0x06c5 +#define WCD9335_RX_BIAS_FLYB_ERRAMP 0x06c6 +#define WCD9335_RX_BIAS_FLYB_BUFF 0x06c7 +#define WCD9335_RX_BIAS_FLYB_MID_RST 0x06c8 +#define WCD9335_HPH_L_STATUS 0x06c9 +#define WCD9335_HPH_R_STATUS 0x06ca +#define WCD9335_HPH_CNP_EN 0x06cb +#define WCD9335_HPH_CNP_WG_CTL 0x06cc +#define WCD9335_HPH_CNP_WG_TIME 0x06cd +#define WCD9335_HPH_OCP_CTL 0x06ce +#define WCD9335_HPH_AUTO_CHOP 0x06cf +#define WCD9335_HPH_CHOP_CTL 0x06d0 +#define WCD9335_HPH_PA_CTL1 0x06d1 +#define WCD9335_HPH_PA_CTL2 0x06d2 +#define WCD9335_HPH_L_EN 0x06d3 +#define WCD9335_HPH_L_TEST 0x06d4 +#define WCD9335_HPH_L_ATEST 0x06d5 +#define WCD9335_HPH_R_EN 0x06d6 +#define WCD9335_HPH_R_TEST 0x06d7 +#define WCD9335_HPH_R_ATEST 0x06d8 +#define WCD9335_HPH_RDAC_CLK_CTL1 0x06d9 +#define WCD9335_HPH_RDAC_CLK_CTL2 0x06da +#define WCD9335_HPH_RDAC_LDO_CTL 0x06db +#define WCD9335_HPH_RDAC_CHOP_CLK_LP_CTL 0x06dc +#define WCD9335_HPH_REFBUFF_UHQA_CTL 0x06dd +#define WCD9335_HPH_REFBUFF_LP_CTL 0x06de +#define WCD9335_HPH_L_DAC_CTL 0x06df +#define WCD9335_HPH_R_DAC_CTL 0x06e0 +#define WCD9335_EAR_EN_REG 0x06e1 +#define WCD9335_EAR_CMBUFF 0x06e2 +#define WCD9335_EAR_ICTL 0x06e3 +#define WCD9335_EAR_EN_DBG_CTL 0x06e4 +#define WCD9335_EAR_CNP 0x06e5 +#define WCD9335_EAR_DAC_CTL_ATEST 0x06e6 +#define WCD9335_EAR_STATUS_REG 0x06e7 +#define WCD9335_EAR_OUT_SHORT 0x06e8 +#define WCD9335_DIFF_LO_MISC 0x06e9 +#define WCD9335_DIFF_LO_LO2_COMPANDER 0x06ea +#define WCD9335_DIFF_LO_LO1_COMPANDER 0x06eb +#define WCD9335_DIFF_LO_COMMON 0x06ec +#define WCD9335_DIFF_LO_BYPASS_EN 0x06ed +#define WCD9335_DIFF_LO_CNP 0x06ee +#define WCD9335_DIFF_LO_CORE_OUT_PROG 0x06ef +#define WCD9335_DIFF_LO_LDO_OUT_PROG 0x06f0 +#define WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ 0x06f1 +#define WCD9335_DIFF_LO_COM_PA_FREQ 0x06f2 +#define WCD9335_DIFF_LO_RESERVED_REG 0x06f3 +#define WCD9335_DIFF_LO_LO1_STATUS_1 0x06f4 +#define WCD9335_DIFF_LO_LO1_STATUS_2 0x06f5 +#define WCD9335_SE_LO_COM1 0x06f6 +#define WCD9335_SE_LO_COM2 0x06f7 +#define WCD9335_SE_LO_LO3_GAIN 0x06f8 +#define WCD9335_SE_LO_LO3_CTRL 0x06f9 +#define WCD9335_SE_LO_LO4_GAIN 0x06fa +#define WCD9335_SE_LO_LO4_CTRL 0x06fb +#define WCD9335_SE_LO_LO3_STATUS 0x06fe +#define WCD9335_SE_LO_LO4_STATUS 0x06ff + +/* Page-10 Registers */ +#define WCD9335_PAGE10_PAGE_REGISTER 0x0a00 +#define WCD9335_CDC_ANC0_CLK_RESET_CTL 0x0a01 +#define WCD9335_CDC_ANC0_MODE_1_CTL 0x0a02 +#define WCD9335_CDC_ANC0_MODE_2_CTL 0x0a03 +#define WCD9335_CDC_ANC0_FF_SHIFT 0x0a04 +#define WCD9335_CDC_ANC0_FB_SHIFT 0x0a05 +#define WCD9335_CDC_ANC0_LPF_FF_A_CTL 0x0a06 +#define WCD9335_CDC_ANC0_LPF_FF_B_CTL 0x0a07 +#define WCD9335_CDC_ANC0_LPF_FB_CTL 0x0a08 +#define WCD9335_CDC_ANC0_SMLPF_CTL 0x0a09 +#define WCD9335_CDC_ANC0_DCFLT_SHIFT_CTL 0x0a0a +#define WCD9335_CDC_ANC0_IIR_ADAPT_CTL 0x0a0b +#define WCD9335_CDC_ANC0_IIR_COEFF_1_CTL 0x0a0c +#define WCD9335_CDC_ANC0_IIR_COEFF_2_CTL 0x0a0d +#define WCD9335_CDC_ANC0_FF_A_GAIN_CTL 0x0a0e +#define WCD9335_CDC_ANC0_FF_B_GAIN_CTL 0x0a0f +#define WCD9335_CDC_ANC0_FB_GAIN_CTL 0x0a10 +#define WCD9335_CDC_ANC1_CLK_RESET_CTL 0x0a19 +#define WCD9335_CDC_ANC1_MODE_1_CTL 0x0a1a +#define WCD9335_CDC_ANC1_MODE_2_CTL 0x0a1b +#define WCD9335_CDC_ANC1_FF_SHIFT 0x0a1c +#define WCD9335_CDC_ANC1_FB_SHIFT 0x0a1d +#define WCD9335_CDC_ANC1_LPF_FF_A_CTL 0x0a1e +#define WCD9335_CDC_ANC1_LPF_FF_B_CTL 0x0a1f +#define WCD9335_CDC_ANC1_LPF_FB_CTL 0x0a20 +#define WCD9335_CDC_ANC1_SMLPF_CTL 0x0a21 +#define WCD9335_CDC_ANC1_DCFLT_SHIFT_CTL 0x0a22 +#define WCD9335_CDC_ANC1_IIR_ADAPT_CTL 0x0a23 +#define WCD9335_CDC_ANC1_IIR_COEFF_1_CTL 0x0a24 +#define WCD9335_CDC_ANC1_IIR_COEFF_2_CTL 0x0a25 +#define WCD9335_CDC_ANC1_FF_A_GAIN_CTL 0x0a26 +#define WCD9335_CDC_ANC1_FF_B_GAIN_CTL 0x0a27 +#define WCD9335_CDC_ANC1_FB_GAIN_CTL 0x0a28 +#define WCD9335_CDC_TX0_TX_PATH_CTL 0x0a31 +#define WCD9335_CDC_TX0_TX_PATH_CFG0 0x0a32 +#define WCD9335_CDC_TX0_TX_PATH_CFG1 0x0a33 +#define WCD9335_CDC_TX0_TX_VOL_CTL 0x0a34 +#define WCD9335_CDC_TX0_TX_PATH_192_CTL 0x0a35 +#define WCD9335_CDC_TX0_TX_PATH_192_CFG 0x0a36 +#define WCD9335_CDC_TX0_TX_PATH_SEC0 0x0a37 +#define WCD9335_CDC_TX0_TX_PATH_SEC1 0x0a38 +#define WCD9335_CDC_TX0_TX_PATH_SEC2 0x0a39 +#define WCD9335_CDC_TX0_TX_PATH_SEC3 0x0a3a +#define WCD9335_CDC_TX0_TX_PATH_SEC4 0x0a3b +#define WCD9335_CDC_TX0_TX_PATH_SEC5 0x0a3c +#define WCD9335_CDC_TX0_TX_PATH_SEC6 0x0a3d +#define WCD9335_CDC_TX0_TX_PATH_SEC7 0x0a3e +#define WCD9335_CDC_TX1_TX_PATH_CTL 0x0a41 +#define WCD9335_CDC_TX1_TX_PATH_CFG0 0x0a42 +#define WCD9335_CDC_TX1_TX_PATH_CFG1 0x0a43 +#define WCD9335_CDC_TX1_TX_VOL_CTL 0x0a44 +#define WCD9335_CDC_TX1_TX_PATH_192_CTL 0x0a45 +#define WCD9335_CDC_TX1_TX_PATH_192_CFG 0x0a46 +#define WCD9335_CDC_TX1_TX_PATH_SEC0 0x0a47 +#define WCD9335_CDC_TX1_TX_PATH_SEC1 0x0a48 +#define WCD9335_CDC_TX1_TX_PATH_SEC2 0x0a49 +#define WCD9335_CDC_TX1_TX_PATH_SEC3 0x0a4a +#define WCD9335_CDC_TX1_TX_PATH_SEC4 0x0a4b +#define WCD9335_CDC_TX1_TX_PATH_SEC5 0x0a4c +#define WCD9335_CDC_TX1_TX_PATH_SEC6 0x0a4d +#define WCD9335_CDC_TX2_TX_PATH_CTL 0x0a51 +#define WCD9335_CDC_TX2_TX_PATH_CFG0 0x0a52 +#define WCD9335_CDC_TX2_TX_PATH_CFG1 0x0a53 +#define WCD9335_CDC_TX2_TX_VOL_CTL 0x0a54 +#define WCD9335_CDC_TX2_TX_PATH_192_CTL 0x0a55 +#define WCD9335_CDC_TX2_TX_PATH_192_CFG 0x0a56 +#define WCD9335_CDC_TX2_TX_PATH_SEC0 0x0a57 +#define WCD9335_CDC_TX2_TX_PATH_SEC1 0x0a58 +#define WCD9335_CDC_TX2_TX_PATH_SEC2 0x0a59 +#define WCD9335_CDC_TX2_TX_PATH_SEC3 0x0a5a +#define WCD9335_CDC_TX2_TX_PATH_SEC4 0x0a5b +#define WCD9335_CDC_TX2_TX_PATH_SEC5 0x0a5c +#define WCD9335_CDC_TX2_TX_PATH_SEC6 0x0a5d +#define WCD9335_CDC_TX3_TX_PATH_CTL 0x0a61 +#define WCD9335_CDC_TX3_TX_PATH_CFG0 0x0a62 +#define WCD9335_CDC_TX3_TX_PATH_CFG1 0x0a63 +#define WCD9335_CDC_TX3_TX_VOL_CTL 0x0a64 +#define WCD9335_CDC_TX3_TX_PATH_192_CTL 0x0a65 +#define WCD9335_CDC_TX3_TX_PATH_192_CFG 0x0a66 +#define WCD9335_CDC_TX3_TX_PATH_SEC0 0x0a67 +#define WCD9335_CDC_TX3_TX_PATH_SEC1 0x0a68 +#define WCD9335_CDC_TX3_TX_PATH_SEC2 0x0a69 +#define WCD9335_CDC_TX3_TX_PATH_SEC3 0x0a6a +#define WCD9335_CDC_TX3_TX_PATH_SEC4 0x0a6b +#define WCD9335_CDC_TX3_TX_PATH_SEC5 0x0a6c +#define WCD9335_CDC_TX3_TX_PATH_SEC6 0x0a6d +#define WCD9335_CDC_TX4_TX_PATH_CTL 0x0a71 +#define WCD9335_CDC_TX4_TX_PATH_CFG0 0x0a72 +#define WCD9335_CDC_TX4_TX_PATH_CFG1 0x0a73 +#define WCD9335_CDC_TX4_TX_VOL_CTL 0x0a74 +#define WCD9335_CDC_TX4_TX_PATH_192_CTL 0x0a75 +#define WCD9335_CDC_TX4_TX_PATH_192_CFG 0x0a76 +#define WCD9335_CDC_TX4_TX_PATH_SEC0 0x0a77 +#define WCD9335_CDC_TX4_TX_PATH_SEC1 0x0a78 +#define WCD9335_CDC_TX4_TX_PATH_SEC2 0x0a79 +#define WCD9335_CDC_TX4_TX_PATH_SEC3 0x0a7a +#define WCD9335_CDC_TX4_TX_PATH_SEC4 0x0a7b +#define WCD9335_CDC_TX4_TX_PATH_SEC5 0x0a7c +#define WCD9335_CDC_TX4_TX_PATH_SEC6 0x0a7d +#define WCD9335_CDC_TX5_TX_PATH_CTL 0x0a81 +#define WCD9335_CDC_TX5_TX_PATH_CFG0 0x0a82 +#define WCD9335_CDC_TX5_TX_PATH_CFG1 0x0a83 +#define WCD9335_CDC_TX5_TX_VOL_CTL 0x0a84 +#define WCD9335_CDC_TX5_TX_PATH_192_CTL 0x0a85 +#define WCD9335_CDC_TX5_TX_PATH_192_CFG 0x0a86 +#define WCD9335_CDC_TX5_TX_PATH_SEC0 0x0a87 +#define WCD9335_CDC_TX5_TX_PATH_SEC1 0x0a88 +#define WCD9335_CDC_TX5_TX_PATH_SEC2 0x0a89 +#define WCD9335_CDC_TX5_TX_PATH_SEC3 0x0a8a +#define WCD9335_CDC_TX5_TX_PATH_SEC4 0x0a8b +#define WCD9335_CDC_TX5_TX_PATH_SEC5 0x0a8c +#define WCD9335_CDC_TX5_TX_PATH_SEC6 0x0a8d +#define WCD9335_CDC_TX6_TX_PATH_CTL 0x0a91 +#define WCD9335_CDC_TX6_TX_PATH_CFG0 0x0a92 +#define WCD9335_CDC_TX6_TX_PATH_CFG1 0x0a93 +#define WCD9335_CDC_TX6_TX_VOL_CTL 0x0a94 +#define WCD9335_CDC_TX6_TX_PATH_192_CTL 0x0a95 +#define WCD9335_CDC_TX6_TX_PATH_192_CFG 0x0a96 +#define WCD9335_CDC_TX6_TX_PATH_SEC0 0x0a97 +#define WCD9335_CDC_TX6_TX_PATH_SEC1 0x0a98 +#define WCD9335_CDC_TX6_TX_PATH_SEC2 0x0a99 +#define WCD9335_CDC_TX6_TX_PATH_SEC3 0x0a9a +#define WCD9335_CDC_TX6_TX_PATH_SEC4 0x0a9b +#define WCD9335_CDC_TX6_TX_PATH_SEC5 0x0a9c +#define WCD9335_CDC_TX6_TX_PATH_SEC6 0x0a9d +#define WCD9335_CDC_TX7_TX_PATH_CTL 0x0aa1 +#define WCD9335_CDC_TX7_TX_PATH_CFG0 0x0aa2 +#define WCD9335_CDC_TX7_TX_PATH_CFG1 0x0aa3 +#define WCD9335_CDC_TX7_TX_VOL_CTL 0x0aa4 +#define WCD9335_CDC_TX7_TX_PATH_192_CTL 0x0aa5 +#define WCD9335_CDC_TX7_TX_PATH_192_CFG 0x0aa6 +#define WCD9335_CDC_TX7_TX_PATH_SEC0 0x0aa7 +#define WCD9335_CDC_TX7_TX_PATH_SEC1 0x0aa8 +#define WCD9335_CDC_TX7_TX_PATH_SEC2 0x0aa9 +#define WCD9335_CDC_TX7_TX_PATH_SEC3 0x0aaa +#define WCD9335_CDC_TX7_TX_PATH_SEC4 0x0aab +#define WCD9335_CDC_TX7_TX_PATH_SEC5 0x0aac +#define WCD9335_CDC_TX7_TX_PATH_SEC6 0x0aad +#define WCD9335_CDC_TX8_TX_PATH_CTL 0x0ab1 +#define WCD9335_CDC_TX8_TX_PATH_CFG0 0x0ab2 +#define WCD9335_CDC_TX8_TX_PATH_CFG1 0x0ab3 +#define WCD9335_CDC_TX8_TX_VOL_CTL 0x0ab4 +#define WCD9335_CDC_TX8_TX_PATH_192_CTL 0x0ab5 +#define WCD9335_CDC_TX8_TX_PATH_192_CFG 0x0ab6 +#define WCD9335_CDC_TX8_TX_PATH_SEC0 0x0ab7 +#define WCD9335_CDC_TX8_TX_PATH_SEC1 0x0ab8 +#define WCD9335_CDC_TX8_TX_PATH_SEC2 0x0ab9 +#define WCD9335_CDC_TX8_TX_PATH_SEC3 0x0aba +#define WCD9335_CDC_TX8_TX_PATH_SEC4 0x0abb +#define WCD9335_CDC_TX8_TX_PATH_SEC5 0x0abc +#define WCD9335_CDC_TX8_TX_PATH_SEC6 0x0abd +#define WCD9335_CDC_TX9_SPKR_PROT_PATH_CTL 0x0ac2 +#define WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0 0x0ac3 +#define WCD9335_CDC_TX10_SPKR_PROT_PATH_CTL 0x0ac6 +#define WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0 0x0ac7 +#define WCD9335_CDC_TX11_SPKR_PROT_PATH_CTL 0x0aca +#define WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0 0x0acb +#define WCD9335_CDC_TX12_SPKR_PROT_PATH_CTL 0x0ace +#define WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0 0x0acf + +/* Page-11 Registers */ +#define WCD9335_PAGE11_PAGE_REGISTER 0x0b00 +#define WCD9335_CDC_COMPANDER1_CTL0 0x0b01 +#define WCD9335_CDC_COMPANDER1_CTL1 0x0b02 +#define WCD9335_CDC_COMPANDER1_CTL2 0x0b03 +#define WCD9335_CDC_COMPANDER1_CTL3 0x0b04 +#define WCD9335_CDC_COMPANDER1_CTL4 0x0b05 +#define WCD9335_CDC_COMPANDER1_CTL5 0x0b06 +#define WCD9335_CDC_COMPANDER1_CTL6 0x0b07 +#define WCD9335_CDC_COMPANDER1_CTL7 0x0b08 +#define WCD9335_CDC_COMPANDER2_CTL0 0x0b09 +#define WCD9335_CDC_COMPANDER2_CTL1 0x0b0a +#define WCD9335_CDC_COMPANDER2_CTL2 0x0b0b +#define WCD9335_CDC_COMPANDER2_CTL3 0x0b0c +#define WCD9335_CDC_COMPANDER2_CTL4 0x0b0d +#define WCD9335_CDC_COMPANDER2_CTL5 0x0b0e +#define WCD9335_CDC_COMPANDER2_CTL6 0x0b0f +#define WCD9335_CDC_COMPANDER2_CTL7 0x0b10 +#define WCD9335_CDC_COMPANDER3_CTL0 0x0b11 +#define WCD9335_CDC_COMPANDER3_CTL1 0x0b12 +#define WCD9335_CDC_COMPANDER3_CTL2 0x0b13 +#define WCD9335_CDC_COMPANDER3_CTL3 0x0b14 +#define WCD9335_CDC_COMPANDER3_CTL4 0x0b15 +#define WCD9335_CDC_COMPANDER3_CTL5 0x0b16 +#define WCD9335_CDC_COMPANDER3_CTL6 0x0b17 +#define WCD9335_CDC_COMPANDER3_CTL7 0x0b18 +#define WCD9335_CDC_COMPANDER4_CTL0 0x0b19 +#define WCD9335_CDC_COMPANDER4_CTL1 0x0b1a +#define WCD9335_CDC_COMPANDER4_CTL2 0x0b1b +#define WCD9335_CDC_COMPANDER4_CTL3 0x0b1c +#define WCD9335_CDC_COMPANDER4_CTL4 0x0b1d +#define WCD9335_CDC_COMPANDER4_CTL5 0x0b1e +#define WCD9335_CDC_COMPANDER4_CTL6 0x0b1f +#define WCD9335_CDC_COMPANDER4_CTL7 0x0b20 +#define WCD9335_CDC_COMPANDER5_CTL0 0x0b21 +#define WCD9335_CDC_COMPANDER5_CTL1 0x0b22 +#define WCD9335_CDC_COMPANDER5_CTL2 0x0b23 +#define WCD9335_CDC_COMPANDER5_CTL3 0x0b24 +#define WCD9335_CDC_COMPANDER5_CTL4 0x0b25 +#define WCD9335_CDC_COMPANDER5_CTL5 0x0b26 +#define WCD9335_CDC_COMPANDER5_CTL6 0x0b27 +#define WCD9335_CDC_COMPANDER5_CTL7 0x0b28 +#define WCD9335_CDC_COMPANDER6_CTL0 0x0b29 +#define WCD9335_CDC_COMPANDER6_CTL1 0x0b2a +#define WCD9335_CDC_COMPANDER6_CTL2 0x0b2b +#define WCD9335_CDC_COMPANDER6_CTL3 0x0b2c +#define WCD9335_CDC_COMPANDER6_CTL4 0x0b2d +#define WCD9335_CDC_COMPANDER6_CTL5 0x0b2e +#define WCD9335_CDC_COMPANDER6_CTL6 0x0b2f +#define WCD9335_CDC_COMPANDER6_CTL7 0x0b30 +#define WCD9335_CDC_COMPANDER7_CTL0 0x0b31 +#define WCD9335_CDC_COMPANDER7_CTL1 0x0b32 +#define WCD9335_CDC_COMPANDER7_CTL2 0x0b33 +#define WCD9335_CDC_COMPANDER7_CTL3 0x0b34 +#define WCD9335_CDC_COMPANDER7_CTL4 0x0b35 +#define WCD9335_CDC_COMPANDER7_CTL5 0x0b36 +#define WCD9335_CDC_COMPANDER7_CTL6 0x0b37 +#define WCD9335_CDC_COMPANDER7_CTL7 0x0b38 +#define WCD9335_CDC_COMPANDER8_CTL0 0x0b39 +#define WCD9335_CDC_COMPANDER8_CTL1 0x0b3a +#define WCD9335_CDC_COMPANDER8_CTL2 0x0b3b +#define WCD9335_CDC_COMPANDER8_CTL3 0x0b3c +#define WCD9335_CDC_COMPANDER8_CTL4 0x0b3d +#define WCD9335_CDC_COMPANDER8_CTL5 0x0b3e +#define WCD9335_CDC_COMPANDER8_CTL6 0x0b3f +#define WCD9335_CDC_COMPANDER8_CTL7 0x0b40 +#define WCD9335_CDC_RX0_RX_PATH_CTL 0x0b41 +#define WCD9335_CDC_RX0_RX_PATH_CFG0 0x0b42 +#define WCD9335_CDC_RX0_RX_PATH_CFG1 0x0b43 +#define WCD9335_CDC_RX0_RX_PATH_CFG2 0x0b44 +#define WCD9335_CDC_RX0_RX_VOL_CTL 0x0b45 +#define WCD9335_CDC_RX0_RX_PATH_MIX_CTL 0x0b46 +#define WCD9335_CDC_RX0_RX_PATH_MIX_CFG 0x0b47 +#define WCD9335_CDC_RX0_RX_VOL_MIX_CTL 0x0b48 +#define WCD9335_CDC_RX0_RX_PATH_SEC0 0x0b49 +#define WCD9335_CDC_RX0_RX_PATH_SEC1 0x0b4a +#define WCD9335_CDC_RX0_RX_PATH_SEC2 0x0b4b +#define WCD9335_CDC_RX0_RX_PATH_SEC3 0x0b4c +#define WCD9335_CDC_RX0_RX_PATH_SEC5 0x0b4e +#define WCD9335_CDC_RX0_RX_PATH_SEC6 0x0b4f +#define WCD9335_CDC_RX0_RX_PATH_SEC7 0x0b50 +#define WCD9335_CDC_RX0_RX_PATH_MIX_SEC0 0x0b51 +#define WCD9335_CDC_RX0_RX_PATH_MIX_SEC1 0x0b52 +#define WCD9335_CDC_RX1_RX_PATH_CTL 0x0b55 +#define WCD9335_CDC_RX1_RX_PATH_CFG0 0x0b56 +#define WCD9335_CDC_RX1_RX_PATH_CFG1 0x0b57 +#define WCD9335_CDC_RX1_RX_PATH_CFG2 0x0b58 +#define WCD9335_CDC_RX1_RX_VOL_CTL 0x0b59 +#define WCD9335_CDC_RX1_RX_PATH_MIX_CTL 0x0b5a +#define WCD9335_CDC_RX1_RX_PATH_MIX_CFG 0x0b5b +#define WCD9335_CDC_RX1_RX_VOL_MIX_CTL 0x0b5c +#define WCD9335_CDC_RX1_RX_PATH_SEC0 0x0b5d +#define WCD9335_CDC_RX1_RX_PATH_SEC1 0x0b5e +#define WCD9335_CDC_RX1_RX_PATH_SEC2 0x0b5f +#define WCD9335_CDC_RX1_RX_PATH_SEC3 0x0b60 +#define WCD9335_CDC_RX1_RX_PATH_SEC4 0x0b61 +#define WCD9335_CDC_RX1_RX_PATH_SEC5 0x0b62 +#define WCD9335_CDC_RX1_RX_PATH_SEC6 0x0b63 +#define WCD9335_CDC_RX1_RX_PATH_SEC7 0x0b64 +#define WCD9335_CDC_RX1_RX_PATH_MIX_SEC0 0x0b65 +#define WCD9335_CDC_RX1_RX_PATH_MIX_SEC1 0x0b66 +#define WCD9335_CDC_RX2_RX_PATH_CTL 0x0b69 +#define WCD9335_CDC_RX2_RX_PATH_CFG0 0x0b6a +#define WCD9335_CDC_RX2_RX_PATH_CFG1 0x0b6b +#define WCD9335_CDC_RX2_RX_PATH_CFG2 0x0b6c +#define WCD9335_CDC_RX2_RX_VOL_CTL 0x0b6d +#define WCD9335_CDC_RX2_RX_PATH_MIX_CTL 0x0b6e +#define WCD9335_CDC_RX2_RX_PATH_MIX_CFG 0x0b6f +#define WCD9335_CDC_RX2_RX_VOL_MIX_CTL 0x0b70 +#define WCD9335_CDC_RX2_RX_PATH_SEC0 0x0b71 +#define WCD9335_CDC_RX2_RX_PATH_SEC1 0x0b72 +#define WCD9335_CDC_RX2_RX_PATH_SEC2 0x0b73 +#define WCD9335_CDC_RX2_RX_PATH_SEC3 0x0b74 +#define WCD9335_CDC_RX2_RX_PATH_SEC4 0x0b75 +#define WCD9335_CDC_RX2_RX_PATH_SEC5 0x0b76 +#define WCD9335_CDC_RX2_RX_PATH_SEC6 0x0b77 +#define WCD9335_CDC_RX2_RX_PATH_SEC7 0x0b78 +#define WCD9335_CDC_RX2_RX_PATH_MIX_SEC0 0x0b79 +#define WCD9335_CDC_RX2_RX_PATH_MIX_SEC1 0x0b7a +#define WCD9335_CDC_RX3_RX_PATH_CTL 0x0b7d +#define WCD9335_CDC_RX3_RX_PATH_CFG0 0x0b7e +#define WCD9335_CDC_RX3_RX_PATH_CFG1 0x0b7f +#define WCD9335_CDC_RX3_RX_PATH_CFG2 0x0b80 +#define WCD9335_CDC_RX3_RX_VOL_CTL 0x0b81 +#define WCD9335_CDC_RX3_RX_PATH_MIX_CTL 0x0b82 +#define WCD9335_CDC_RX3_RX_PATH_MIX_CFG 0x0b83 +#define WCD9335_CDC_RX3_RX_VOL_MIX_CTL 0x0b84 +#define WCD9335_CDC_RX3_RX_PATH_SEC0 0x0b85 +#define WCD9335_CDC_RX3_RX_PATH_SEC1 0x0b86 +#define WCD9335_CDC_RX3_RX_PATH_SEC2 0x0b87 +#define WCD9335_CDC_RX3_RX_PATH_SEC3 0x0b88 +#define WCD9335_CDC_RX3_RX_PATH_SEC5 0x0b8a +#define WCD9335_CDC_RX3_RX_PATH_SEC6 0x0b8b +#define WCD9335_CDC_RX3_RX_PATH_SEC7 0x0b8c +#define WCD9335_CDC_RX3_RX_PATH_MIX_SEC0 0x0b8d +#define WCD9335_CDC_RX3_RX_PATH_MIX_SEC1 0x0b8e +#define WCD9335_CDC_RX4_RX_PATH_CTL 0x0b91 +#define WCD9335_CDC_RX4_RX_PATH_CFG0 0x0b92 +#define WCD9335_CDC_RX4_RX_PATH_CFG1 0x0b93 +#define WCD9335_CDC_RX4_RX_PATH_CFG2 0x0b94 +#define WCD9335_CDC_RX4_RX_VOL_CTL 0x0b95 +#define WCD9335_CDC_RX4_RX_PATH_MIX_CTL 0x0b96 +#define WCD9335_CDC_RX4_RX_PATH_MIX_CFG 0x0b97 +#define WCD9335_CDC_RX4_RX_VOL_MIX_CTL 0x0b98 +#define WCD9335_CDC_RX4_RX_PATH_SEC0 0x0b99 +#define WCD9335_CDC_RX4_RX_PATH_SEC1 0x0b9a +#define WCD9335_CDC_RX4_RX_PATH_SEC2 0x0b9b +#define WCD9335_CDC_RX4_RX_PATH_SEC3 0x0b9c +#define WCD9335_CDC_RX4_RX_PATH_SEC5 0x0b9e +#define WCD9335_CDC_RX4_RX_PATH_SEC6 0x0b9f +#define WCD9335_CDC_RX4_RX_PATH_SEC7 0x0ba0 +#define WCD9335_CDC_RX4_RX_PATH_MIX_SEC0 0x0ba1 +#define WCD9335_CDC_RX4_RX_PATH_MIX_SEC1 0x0ba2 +#define WCD9335_CDC_RX5_RX_PATH_CTL 0x0ba5 +#define WCD9335_CDC_RX5_RX_PATH_CFG0 0x0ba6 +#define WCD9335_CDC_RX5_RX_PATH_CFG1 0x0ba7 +#define WCD9335_CDC_RX5_RX_PATH_CFG2 0x0ba8 +#define WCD9335_CDC_RX5_RX_VOL_CTL 0x0ba9 +#define WCD9335_CDC_RX5_RX_PATH_MIX_CTL 0x0baa +#define WCD9335_CDC_RX5_RX_PATH_MIX_CFG 0x0bab +#define WCD9335_CDC_RX5_RX_VOL_MIX_CTL 0x0bac +#define WCD9335_CDC_RX5_RX_PATH_SEC0 0x0bad +#define WCD9335_CDC_RX5_RX_PATH_SEC1 0x0bae +#define WCD9335_CDC_RX5_RX_PATH_SEC2 0x0baf +#define WCD9335_CDC_RX5_RX_PATH_SEC3 0x0bb0 +#define WCD9335_CDC_RX5_RX_PATH_SEC5 0x0bb2 +#define WCD9335_CDC_RX5_RX_PATH_SEC6 0x0bb3 +#define WCD9335_CDC_RX5_RX_PATH_SEC7 0x0bb4 +#define WCD9335_CDC_RX5_RX_PATH_MIX_SEC0 0x0bb5 +#define WCD9335_CDC_RX5_RX_PATH_MIX_SEC1 0x0bb6 +#define WCD9335_CDC_RX6_RX_PATH_CTL 0x0bb9 +#define WCD9335_CDC_RX6_RX_PATH_CFG0 0x0bba +#define WCD9335_CDC_RX6_RX_PATH_CFG1 0x0bbb +#define WCD9335_CDC_RX6_RX_PATH_CFG2 0x0bbc +#define WCD9335_CDC_RX6_RX_VOL_CTL 0x0bbd +#define WCD9335_CDC_RX6_RX_PATH_MIX_CTL 0x0bbe +#define WCD9335_CDC_RX6_RX_PATH_MIX_CFG 0x0bbf +#define WCD9335_CDC_RX6_RX_VOL_MIX_CTL 0x0bc0 +#define WCD9335_CDC_RX6_RX_PATH_SEC0 0x0bc1 +#define WCD9335_CDC_RX6_RX_PATH_SEC1 0x0bc2 +#define WCD9335_CDC_RX6_RX_PATH_SEC2 0x0bc3 +#define WCD9335_CDC_RX6_RX_PATH_SEC3 0x0bc4 +#define WCD9335_CDC_RX6_RX_PATH_SEC5 0x0bc6 +#define WCD9335_CDC_RX6_RX_PATH_SEC6 0x0bc7 +#define WCD9335_CDC_RX6_RX_PATH_SEC7 0x0bc8 +#define WCD9335_CDC_RX6_RX_PATH_MIX_SEC0 0x0bc9 +#define WCD9335_CDC_RX6_RX_PATH_MIX_SEC1 0x0bca +#define WCD9335_CDC_RX7_RX_PATH_CTL 0x0bcd +#define WCD9335_CDC_RX7_RX_PATH_CFG0 0x0bce +#define WCD9335_CDC_RX7_RX_PATH_CFG1 0x0bcf +#define WCD9335_CDC_RX7_RX_PATH_CFG2 0x0bd0 +#define WCD9335_CDC_RX7_RX_VOL_CTL 0x0bd1 +#define WCD9335_CDC_RX7_RX_PATH_MIX_CTL 0x0bd2 +#define WCD9335_CDC_RX7_RX_PATH_MIX_CFG 0x0bd3 +#define WCD9335_CDC_RX7_RX_VOL_MIX_CTL 0x0bd4 +#define WCD9335_CDC_RX7_RX_PATH_SEC0 0x0bd5 +#define WCD9335_CDC_RX7_RX_PATH_SEC1 0x0bd6 +#define WCD9335_CDC_RX7_RX_PATH_SEC2 0x0bd7 +#define WCD9335_CDC_RX7_RX_PATH_SEC3 0x0bd8 +#define WCD9335_CDC_RX7_RX_PATH_SEC5 0x0bda +#define WCD9335_CDC_RX7_RX_PATH_SEC6 0x0bdb +#define WCD9335_CDC_RX7_RX_PATH_SEC7 0x0bdc +#define WCD9335_CDC_RX7_RX_PATH_MIX_SEC0 0x0bdd +#define WCD9335_CDC_RX7_RX_PATH_MIX_SEC1 0x0bde +#define WCD9335_CDC_RX8_RX_PATH_CTL 0x0be1 +#define WCD9335_CDC_RX8_RX_PATH_CFG0 0x0be2 +#define WCD9335_CDC_RX8_RX_PATH_CFG1 0x0be3 +#define WCD9335_CDC_RX8_RX_PATH_CFG2 0x0be4 +#define WCD9335_CDC_RX8_RX_VOL_CTL 0x0be5 +#define WCD9335_CDC_RX8_RX_PATH_MIX_CTL 0x0be6 +#define WCD9335_CDC_RX8_RX_PATH_MIX_CFG 0x0be7 +#define WCD9335_CDC_RX8_RX_VOL_MIX_CTL 0x0be8 +#define WCD9335_CDC_RX8_RX_PATH_SEC0 0x0be9 +#define WCD9335_CDC_RX8_RX_PATH_SEC1 0x0bea +#define WCD9335_CDC_RX8_RX_PATH_SEC2 0x0beb +#define WCD9335_CDC_RX8_RX_PATH_SEC3 0x0bec +#define WCD9335_CDC_RX8_RX_PATH_SEC5 0x0bee +#define WCD9335_CDC_RX8_RX_PATH_SEC6 0x0bef +#define WCD9335_CDC_RX8_RX_PATH_SEC7 0x0bf0 +#define WCD9335_CDC_RX8_RX_PATH_MIX_SEC0 0x0bf1 +#define WCD9335_CDC_RX8_RX_PATH_MIX_SEC1 0x0bf2 + +/* Page-12 Registers */ +#define WCD9335_PAGE12_PAGE_REGISTER 0x0c00 +#define WCD9335_CDC_CLSH_CRC 0x0c01 +#define WCD9335_CDC_CLSH_DLY_CTRL 0x0c02 +#define WCD9335_CDC_CLSH_DECAY_CTRL 0x0c03 +#define WCD9335_CDC_CLSH_HPH_V_PA 0x0c04 +#define WCD9335_CDC_CLSH_EAR_V_PA 0x0c05 +#define WCD9335_CDC_CLSH_HPH_V_HD 0x0c06 +#define WCD9335_CDC_CLSH_EAR_V_HD 0x0c07 +#define WCD9335_CDC_CLSH_K1_MSB 0x0c08 +#define WCD9335_CDC_CLSH_K1_LSB 0x0c09 +#define WCD9335_CDC_CLSH_K2_MSB 0x0c0a +#define WCD9335_CDC_CLSH_K2_LSB 0x0c0b +#define WCD9335_CDC_CLSH_IDLE_CTRL 0x0c0c +#define WCD9335_CDC_CLSH_IDLE_HPH 0x0c0d +#define WCD9335_CDC_CLSH_IDLE_EAR 0x0c0e +#define WCD9335_CDC_CLSH_TEST0 0x0c0f +#define WCD9335_CDC_CLSH_TEST1 0x0c10 +#define WCD9335_CDC_CLSH_OVR_VREF 0x0c11 +#define WCD9335_CDC_BOOST0_BOOST_PATH_CTL 0x0c19 +#define WCD9335_CDC_BOOST0_BOOST_CTL 0x0c1a +#define WCD9335_CDC_BOOST0_BOOST_CFG1 0x0c1b +#define WCD9335_CDC_BOOST0_BOOST_CFG2 0x0c1c +#define WCD9335_CDC_BOOST1_BOOST_PATH_CTL 0x0c21 +#define WCD9335_CDC_BOOST1_BOOST_CTL 0x0c22 +#define WCD9335_CDC_BOOST1_BOOST_CFG1 0x0c23 +#define WCD9335_CDC_BOOST1_BOOST_CFG2 0x0c24 +#define WCD9335_SWR_AHB_BRIDGE_WR_DATA_0 0x0c29 +#define WCD9335_SWR_AHB_BRIDGE_WR_DATA_1 0x0c2a +#define WCD9335_SWR_AHB_BRIDGE_WR_DATA_2 0x0c2b +#define WCD9335_SWR_AHB_BRIDGE_WR_DATA_3 0x0c2c +#define WCD9335_SWR_AHB_BRIDGE_WR_ADDR_0 0x0c2d +#define WCD9335_SWR_AHB_BRIDGE_WR_ADDR_1 0x0c2e +#define WCD9335_SWR_AHB_BRIDGE_WR_ADDR_2 0x0c2f +#define WCD9335_SWR_AHB_BRIDGE_WR_ADDR_3 0x0c30 +#define WCD9335_SWR_AHB_BRIDGE_RD_ADDR_0 0x0c31 +#define WCD9335_SWR_AHB_BRIDGE_RD_ADDR_1 0x0c32 +#define WCD9335_SWR_AHB_BRIDGE_RD_ADDR_2 0x0c33 +#define WCD9335_SWR_AHB_BRIDGE_RD_ADDR_3 0x0c34 +#define WCD9335_SWR_AHB_BRIDGE_RD_DATA_0 0x0c35 +#define WCD9335_SWR_AHB_BRIDGE_RD_DATA_1 0x0c36 +#define WCD9335_SWR_AHB_BRIDGE_RD_DATA_2 0x0c37 +#define WCD9335_SWR_AHB_BRIDGE_RD_DATA_3 0x0c38 +#define WCD9335_SWR_AHB_BRIDGE_ACCESS_CFG 0x0c39 +#define WCD9335_SWR_AHB_BRIDGE_ACCESS_STATUS 0x0c3a +#define WCD9335_CDC_VBAT_VBAT_PATH_CTL 0x0c3d +#define WCD9335_CDC_VBAT_VBAT_CFG 0x0c3e +#define WCD9335_CDC_VBAT_VBAT_ADC_CAL1 0x0c3f +#define WCD9335_CDC_VBAT_VBAT_ADC_CAL2 0x0c40 +#define WCD9335_CDC_VBAT_VBAT_ADC_CAL3 0x0c41 +#define WCD9335_CDC_VBAT_VBAT_PK_EST1 0x0c42 +#define WCD9335_CDC_VBAT_VBAT_PK_EST2 0x0c43 +#define WCD9335_CDC_VBAT_VBAT_PK_EST3 0x0c44 +#define WCD9335_CDC_VBAT_VBAT_RF_PROC1 0x0c45 +#define WCD9335_CDC_VBAT_VBAT_RF_PROC2 0x0c46 +#define WCD9335_CDC_VBAT_VBAT_TAC1 0x0c47 +#define WCD9335_CDC_VBAT_VBAT_TAC2 0x0c48 +#define WCD9335_CDC_VBAT_VBAT_TAC3 0x0c49 +#define WCD9335_CDC_VBAT_VBAT_TAC4 0x0c4a +#define WCD9335_CDC_VBAT_VBAT_GAIN_UPD1 0x0c4b +#define WCD9335_CDC_VBAT_VBAT_GAIN_UPD2 0x0c4c +#define WCD9335_CDC_VBAT_VBAT_GAIN_UPD3 0x0c4d +#define WCD9335_CDC_VBAT_VBAT_GAIN_UPD4 0x0c4e +#define WCD9335_CDC_VBAT_VBAT_DEBUG1 0x0c4f +#define WCD9335_CDC_VBAT_VBAT_GAIN_UPD_MON 0x0c50 +#define WCD9335_CDC_VBAT_VBAT_GAIN_MON_VAL 0x0c51 +#define WCD9335_SPLINE_SRC0_CLK_RST_CTL_0 0x0c55 +#define WCD9335_SPLINE_SRC0_STATUS 0x0c56 +#define WCD9335_SPLINE_SRC1_CLK_RST_CTL_0 0x0c6d +#define WCD9335_SPLINE_SRC1_STATUS 0x0c6e +#define WCD9335_SPLINE_SRC2_CLK_RST_CTL_0 0x0c85 +#define WCD9335_SPLINE_SRC2_STATUS 0x0c86 +#define WCD9335_SPLINE_SRC3_CLK_RST_CTL_0 0x0c9d +#define WCD9335_SPLINE_SRC3_STATUS 0x0c9e +#define WCD9335_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL 0x0cb5 +#define WCD9335_CDC_SIDETONE_SRC0_ST_SRC_PATH_CFG1 0x0cb6 +#define WCD9335_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL 0x0cb9 +#define WCD9335_CDC_SIDETONE_SRC1_ST_SRC_PATH_CFG1 0x0cba + +/* Page-13 Registers */ +#define WCD9335_PAGE13_PAGE_REGISTER 0x0d00 +#define WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0 0x0d01 +#define WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1 0x0d02 +#define WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0 0x0d03 +#define WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1 0x0d04 +#define WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0 0x0d05 +#define WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1 0x0d06 +#define WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0 0x0d07 +#define WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1 0x0d08 +#define WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0 0x0d09 +#define WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1 0x0d0a +#define WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0 0x0d0b +#define WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1 0x0d0c +#define WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0 0x0d0d +#define WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1 0x0d0e +#define WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0 0x0d0f +#define WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1 0x0d10 +#define WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0 0x0d11 +#define WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1 0x0d12 +#define WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG0 0x0d13 +#define WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG1 0x0d14 +#define WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG2 0x0d15 +#define WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG3 0x0d16 +#define WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG4 0x0d17 +#define WCD9335_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 0x0d18 +#define WCD9335_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1 0x0d19 +#define WCD9335_CDC_RX_INP_MUX_ANC_CFG0 0x0d1a +#define WCD9335_CDC_RX_INP_MUX_SPLINE_SRC_CFG0 0x0d1b +#define WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 0x0d1d +#define WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 0x0d1e +#define WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0 0x0d1f +#define WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1 0x0d20 +#define WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0 0x0d21 +#define WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1 0x0d22 +#define WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0 0x0d23 +#define WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1 0x0d24 +#define WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 0x0d25 +#define WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0 0x0d26 +#define WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0 0x0d27 +#define WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0 0x0d28 +#define WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0 0x0d29 +#define WCD9335_CDC_TX_INP_MUX_ADC_MUX10_CFG0 0x0d2b +#define WCD9335_CDC_TX_INP_MUX_ADC_MUX11_CFG0 0x0d2c +#define WCD9335_CDC_TX_INP_MUX_ADC_MUX12_CFG0 0x0d2d +#define WCD9335_CDC_TX_INP_MUX_ADC_MUX13_CFG0 0x0d2e +#define WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0 0x0d31 +#define WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1 0x0d32 +#define WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2 0x0d33 +#define WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3 0x0d34 +#define WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0 0x0d35 +#define WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1 0x0d36 +#define WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2 0x0d37 +#define WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3 0x0d38 +#define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0 0x0d3a +#define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1 0x0d3b +#define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2 0x0d3c +#define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3 0x0d3d +#define WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL 0x0d41 +#define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL 0x0d42 +#define WCD9335_CDC_CLK_RST_CTRL_SWR_CONTROL 0x0d43 +#define WCD9335_CDC_PROX_DETECT_PROX_CTL 0x0d49 +#define WCD9335_CDC_PROX_DETECT_PROX_POLL_PERIOD0 0x0d4a +#define WCD9335_CDC_PROX_DETECT_PROX_POLL_PERIOD1 0x0d4b +#define WCD9335_CDC_PROX_DETECT_PROX_SIG_PATTERN_LSB 0x0d4c +#define WCD9335_CDC_PROX_DETECT_PROX_SIG_PATTERN_MSB 0x0d4d +#define WCD9335_CDC_PROX_DETECT_PROX_STATUS 0x0d4e +#define WCD9335_CDC_PROX_DETECT_PROX_TEST_CTRL 0x0d4f +#define WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB 0x0d50 +#define WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB 0x0d51 +#define WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB_RD 0x0d52 +#define WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB_RD 0x0d53 +#define WCD9335_CDC_PROX_DETECT_PROX_CTL_REPEAT_PAT 0x0d54 +#define WCD9335_CDC_SIDETONE_IIR0_IIR_PATH_CTL 0x0d55 +#define WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL 0x0d56 +#define WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL 0x0d57 +#define WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL 0x0d58 +#define WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL 0x0d59 +#define WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B5_CTL 0x0d5a +#define WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B6_CTL 0x0d5b +#define WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B7_CTL 0x0d5c +#define WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B8_CTL 0x0d5d +#define WCD9335_CDC_SIDETONE_IIR0_IIR_CTL 0x0d5e +#define WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL 0x0d5f +#define WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL 0x0d60 +#define WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL 0x0d61 +#define WCD9335_CDC_SIDETONE_IIR1_IIR_PATH_CTL 0x0d65 +#define WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL 0x0d66 +#define WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL 0x0d67 +#define WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL 0x0d68 +#define WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL 0x0d69 +#define WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B5_CTL 0x0d6a +#define WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B6_CTL 0x0d6b +#define WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B7_CTL 0x0d6c +#define WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B8_CTL 0x0d6d +#define WCD9335_CDC_SIDETONE_IIR1_IIR_CTL 0x0d6e +#define WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL 0x0d6f +#define WCD9335_CDC_SIDETONE_IIR1_IIR_COEF_B1_CTL 0x0d70 +#define WCD9335_CDC_SIDETONE_IIR1_IIR_COEF_B2_CTL 0x0d71 +#define WCD9335_CDC_TOP_TOP_CFG0 0x0d81 +#define WCD9335_CDC_TOP_TOP_CFG1 0x0d82 +#define WCD9335_CDC_TOP_TOP_CFG2 0x0d83 +#define WCD9335_CDC_TOP_TOP_CFG3 0x0d84 +#define WCD9335_CDC_TOP_TOP_CFG4 0x0d85 +#define WCD9335_CDC_TOP_TOP_CFG5 0x0d86 +#define WCD9335_CDC_TOP_TOP_CFG6 0x0d87 +#define WCD9335_CDC_TOP_TOP_CFG7 0x0d88 +#define WCD9335_CDC_TOP_HPHL_COMP_WR_LSB 0x0d89 +#define WCD9335_CDC_TOP_HPHL_COMP_WR_MSB 0x0d8a +#define WCD9335_CDC_TOP_HPHL_COMP_LUT 0x0d8b +#define WCD9335_CDC_TOP_HPHL_COMP_RD_LSB 0x0d8c +#define WCD9335_CDC_TOP_HPHL_COMP_RD_MSB 0x0d8d +#define WCD9335_CDC_TOP_HPHR_COMP_WR_LSB 0x0d8e +#define WCD9335_CDC_TOP_HPHR_COMP_WR_MSB 0x0d8f +#define WCD9335_CDC_TOP_HPHR_COMP_LUT 0x0d90 +#define WCD9335_CDC_TOP_HPHR_COMP_RD_LSB 0x0d91 +#define WCD9335_CDC_TOP_HPHR_COMP_RD_MSB 0x0d92 +#define WCD9335_CDC_TOP_DIFFL_COMP_WR_LSB 0x0d93 +#define WCD9335_CDC_TOP_DIFFL_COMP_WR_MSB 0x0d94 +#define WCD9335_CDC_TOP_DIFFL_COMP_LUT 0x0d95 +#define WCD9335_CDC_TOP_DIFFL_COMP_RD_LSB 0x0d96 +#define WCD9335_CDC_TOP_DIFFL_COMP_RD_MSB 0x0d97 +#define WCD9335_CDC_TOP_DIFFR_COMP_WR_LSB 0x0d98 +#define WCD9335_CDC_TOP_DIFFR_COMP_WR_MSB 0x0d99 +#define WCD9335_CDC_TOP_DIFFR_COMP_LUT 0x0d9a +#define WCD9335_CDC_TOP_DIFFR_COMP_RD_LSB 0x0d9b +#define WCD9335_CDC_TOP_DIFFR_COMP_RD_MSB 0x0d9c + +/* Page-0x80 Registers */ +#define WCD9335_PAGE80_PAGE_REGISTER 0x8000 +#define WCD9335_TLMM_BIST_MODE_PINCFG 0x8001 +#define WCD9335_TLMM_RF_PA_ON_PINCFG 0x8002 +#define WCD9335_TLMM_INTR1_PINCFG 0x8003 +#define WCD9335_TLMM_INTR2_PINCFG 0x8004 +#define WCD9335_TLMM_SWR_DATA_PINCFG 0x8005 +#define WCD9335_TLMM_SWR_CLK_PINCFG 0x8006 +#define WCD9335_TLMM_SLIMBUS_DATA2_PINCFG 0x8007 +#define WCD9335_TLMM_I2C_CLK_PINCFG 0x8008 +#define WCD9335_TLMM_I2C_DATA_PINCFG 0x8009 +#define WCD9335_TLMM_I2S_RX_SD0_PINCFG 0x800a +#define WCD9335_TLMM_I2S_RX_SD1_PINCFG 0x800b +#define WCD9335_TLMM_I2S_RX_SCK_PINCFG 0x800c +#define WCD9335_TLMM_I2S_RX_WS_PINCFG 0x800d +#define WCD9335_TLMM_I2S_TX_SD0_PINCFG 0x800e +#define WCD9335_TLMM_I2S_TX_SD1_PINCFG 0x800f +#define WCD9335_TLMM_I2S_TX_SCK_PINCFG 0x8010 +#define WCD9335_TLMM_I2S_TX_WS_PINCFG 0x8011 +#define WCD9335_TLMM_DMIC1_CLK_PINCFG 0x8012 +#define WCD9335_TLMM_DMIC1_DATA_PINCFG 0x8013 +#define WCD9335_TLMM_DMIC2_CLK_PINCFG 0x8014 +#define WCD9335_TLMM_DMIC2_DATA_PINCFG 0x8015 +#define WCD9335_TLMM_DMIC3_CLK_PINCFG 0x8016 +#define WCD9335_TLMM_DMIC3_DATA_PINCFG 0x8017 +#define WCD9335_TLMM_JTDI_PINCFG 0x8018 +#define WCD9335_TLMM_JTDO_PINCFG 0x8019 +#define WCD9335_TLMM_JTMS_PINCFG 0x801a +#define WCD9335_TLMM_JTCK_PINCFG 0x801b +#define WCD9335_TLMM_JTRST_PINCFG 0x801c +#define WCD9335_TEST_DEBUG_PIN_CTL_OE_0 0x8031 +#define WCD9335_TEST_DEBUG_PIN_CTL_OE_1 0x8032 +#define WCD9335_TEST_DEBUG_PIN_CTL_OE_2 0x8033 +#define WCD9335_TEST_DEBUG_PIN_CTL_OE_3 0x8034 +#define WCD9335_TEST_DEBUG_PIN_CTL_DATA_0 0x8035 +#define WCD9335_TEST_DEBUG_PIN_CTL_DATA_1 0x8036 +#define WCD9335_TEST_DEBUG_PIN_CTL_DATA_2 0x8037 +#define WCD9335_TEST_DEBUG_PIN_CTL_DATA_3 0x8038 +#define WCD9335_TEST_DEBUG_PAD_DRVCTL 0x8039 +#define WCD9335_TEST_DEBUG_PIN_STATUS 0x803a +#define WCD9335_TEST_DEBUG_NPL_DLY_TEST_1 0x803b +#define WCD9335_TEST_DEBUG_NPL_DLY_TEST_2 0x803c +#define WCD9335_TEST_DEBUG_MEM_CTRL 0x803d +#define WCD9335_TEST_DEBUG_DEBUG_BUS_SEL 0x8041 +#define WCD9335_TEST_DEBUG_DEBUG_JTAG 0x8042 +#define WCD9335_TEST_DEBUG_DEBUG_EN_1 0x8043 +#define WCD9335_TEST_DEBUG_DEBUG_EN_2 0x8044 +#define WCD9335_TEST_DEBUG_DEBUG_EN_3 0x8045 +#define WCD9335_MAX_REGISTER 0x80FF + +/* SLIMBUS Slave Registers */ +#define TASHA_SLIM_PGD_PORT_INT_EN0 (0x30) +#define TASHA_SLIM_PGD_PORT_INT_STATUS_RX_0 (0x34) +#define TASHA_SLIM_PGD_PORT_INT_STATUS_RX_1 (0x35) +#define TASHA_SLIM_PGD_PORT_INT_STATUS_TX_0 (0x36) +#define TASHA_SLIM_PGD_PORT_INT_STATUS_TX_1 (0x37) +#define TASHA_SLIM_PGD_PORT_INT_CLR_RX_0 (0x38) +#define TASHA_SLIM_PGD_PORT_INT_CLR_RX_1 (0x39) +#define TASHA_SLIM_PGD_PORT_INT_CLR_TX_0 (0x3A) +#define TASHA_SLIM_PGD_PORT_INT_CLR_TX_1 (0x3B) +#define TASHA_SLIM_PGD_PORT_INT_RX_SOURCE0 (0x60) +#define TASHA_SLIM_PGD_PORT_INT_TX_SOURCE0 (0x70) + +/* Macros for Packing Register Writes into a U32 */ +#define TASHA_PACKED_REG_SIZE sizeof(u32) + +#define TASHA_CODEC_PACK_ENTRY(reg, mask, val) ((val & 0xff)|\ + ((mask & 0xff) << 8)|((reg & 0xffff) << 16)) +#define TASHA_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \ + do { \ + ((reg) = ((packed >> 16) & (0xffff))); \ + ((mask) = ((packed >> 8) & (0xff))); \ + ((val) = ((packed) & (0xff))); \ + } while (0) +#endif diff --git a/include/linux/mfd/wcd934x/registers.h b/include/linux/mfd/wcd934x/registers.h new file mode 100644 index 000000000000..a824875096e4 --- /dev/null +++ b/include/linux/mfd/wcd934x/registers.h @@ -0,0 +1,1848 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _WCD934X_REGISTERS_H +#define _WCD934X_REGISTERS_H + +#define WCD934X_PAGE_SIZE 256 +#define WCD934X_NUM_PAGES 256 + +extern const u8 * const wcd934x_reg[WCD934X_NUM_PAGES]; + +enum { + WCD934X_PAGE_0 = 0, + WCD934X_PAGE_1, + WCD934X_PAGE_2, + WCD934X_PAGE_4 = 4, + WCD934X_PAGE_5, + WCD934X_PAGE_6, + WCD934X_PAGE_7, + WCD934X_PAGE_10 = 0xA, + WCD934X_PAGE_11, + WCD934X_PAGE_12, + WCD934X_PAGE_13, + WCD934X_PAGE_14, + WCD934X_PAGE_15, + WCD934X_PAGE_0x50, + WCD934X_PAGE_0X80, +}; + +enum { + WCD934X_WRITE = 0, + WCD934X_READ, + WCD934X_READ_WRITE, +}; + +/* Page-0 Registers */ +#define WCD934X_PAGE0_PAGE_REGISTER 0x0000 +#define WCD934X_CODEC_RPM_CLK_BYPASS 0x0001 +#define WCD934X_CODEC_RPM_CLK_GATE 0x0002 +#define WCD934X_CODEC_RPM_CLK_MCLK_CFG 0x0003 +#define WCD934X_CODEC_RPM_CLK_MCLK2_CFG 0x0004 +#define WCD934X_CODEC_RPM_I2S_DSD_CLK_SEL 0x0005 +#define WCD934X_CODEC_RPM_RST_CTL 0x0009 +#define WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL 0x0011 +#define WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0 0x0021 +#define WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE1 0x0022 +#define WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE2 0x0023 +#define WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE3 0x0024 +#define WCD934X_CHIP_TIER_CTRL_EFUSE_CTL 0x0025 +#define WCD934X_CHIP_TIER_CTRL_EFUSE_TEST0 0x0026 +#define WCD934X_CHIP_TIER_CTRL_EFUSE_TEST1 0x0027 +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT0 0x0029 +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 0x002a +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 0x002b +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT3 0x002c +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT4 0x002d +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT5 0x002e +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT6 0x002f +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT7 0x0030 +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT8 0x0031 +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT9 0x0032 +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT10 0x0033 +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT11 0x0034 +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT12 0x0035 +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT13 0x0036 +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14 0x0037 +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15 0x0038 +#define WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS 0x0039 +#define WCD934X_CHIP_TIER_CTRL_I2C_SLAVE_ID_NONNEGO 0x003a +#define WCD934X_CHIP_TIER_CTRL_I2C_SLAVE_ID_1 0x003b +#define WCD934X_CHIP_TIER_CTRL_I2C_SLAVE_ID_2 0x003c +#define WCD934X_CHIP_TIER_CTRL_I2C_SLAVE_ID_3 0x003d +#define WCD934X_CHIP_TIER_CTRL_ANA_WAIT_STATE_CTL 0x003e +#define WCD934X_CHIP_TIER_CTRL_SLNQ_WAIT_STATE_CTL 0x003f +#define WCD934X_CHIP_TIER_CTRL_I2C_ACTIVE 0x0040 +#define WCD934X_CHIP_TIER_CTRL_ALT_FUNC_EN 0x0041 +#define WCD934X_CHIP_TIER_CTRL_GPIO_CTL_OE 0x0042 +#define WCD934X_CHIP_TIER_CTRL_GPIO_CTL_DATA 0x0043 +#define WCD934X_DATA_HUB_RX0_CFG 0x0051 +#define WCD934X_DATA_HUB_RX1_CFG 0x0052 +#define WCD934X_DATA_HUB_RX2_CFG 0x0053 +#define WCD934X_DATA_HUB_RX3_CFG 0x0054 +#define WCD934X_DATA_HUB_RX4_CFG 0x0055 +#define WCD934X_DATA_HUB_RX5_CFG 0x0056 +#define WCD934X_DATA_HUB_RX6_CFG 0x0057 +#define WCD934X_DATA_HUB_RX7_CFG 0x0058 +#define WCD934X_DATA_HUB_SB_TX0_INP_CFG 0x0061 +#define WCD934X_DATA_HUB_SB_TX1_INP_CFG 0x0062 +#define WCD934X_DATA_HUB_SB_TX2_INP_CFG 0x0063 +#define WCD934X_DATA_HUB_SB_TX3_INP_CFG 0x0064 +#define WCD934X_DATA_HUB_SB_TX4_INP_CFG 0x0065 +#define WCD934X_DATA_HUB_SB_TX5_INP_CFG 0x0066 +#define WCD934X_DATA_HUB_SB_TX6_INP_CFG 0x0067 +#define WCD934X_DATA_HUB_SB_TX7_INP_CFG 0x0068 +#define WCD934X_DATA_HUB_SB_TX8_INP_CFG 0x0069 +#define WCD934X_DATA_HUB_SB_TX9_INP_CFG 0x006a +#define WCD934X_DATA_HUB_SB_TX10_INP_CFG 0x006b +#define WCD934X_DATA_HUB_SB_TX11_INP_CFG 0x006c +#define WCD934X_DATA_HUB_SB_TX13_INP_CFG 0x006e +#define WCD934X_DATA_HUB_SB_TX14_INP_CFG 0x006f +#define WCD934X_DATA_HUB_SB_TX15_INP_CFG 0x0070 +#define WCD934X_DATA_HUB_I2S_TX0_CFG 0x0071 +#define WCD934X_DATA_HUB_I2S_TX1_0_CFG 0x0073 +#define WCD934X_DATA_HUB_I2S_TX1_1_CFG 0x0074 +#define WCD934X_DATA_HUB_I2S_0_CTL 0x0081 +#define WCD934X_DATA_HUB_I2S_1_CTL 0x0082 +#define WCD934X_DATA_HUB_I2S_2_CTL 0x0083 +#define WCD934X_DATA_HUB_I2S_3_CTL 0x0084 +#define WCD934X_DATA_HUB_I2S_CLKSRC_CTL 0x0085 +#define WCD934X_DATA_HUB_I2S_COMMON_CTL 0x0086 +#define WCD934X_DATA_HUB_I2S_0_TDM_CTL 0x0087 +#define WCD934X_DATA_HUB_I2S_STATUS 0x0088 +#define WCD934X_DMA_RDMA_CTL_0 0x0091 +#define WCD934X_DMA_CH_2_3_CFG_RDMA_0 0x0092 +#define WCD934X_DMA_CH_0_1_CFG_RDMA_0 0x0093 +#define WCD934X_DMA_RDMA_CTL_1 0x0094 +#define WCD934X_DMA_CH_2_3_CFG_RDMA_1 0x0095 +#define WCD934X_DMA_CH_0_1_CFG_RDMA_1 0x0096 +#define WCD934X_DMA_RDMA_CTL_2 0x0097 +#define WCD934X_DMA_CH_2_3_CFG_RDMA_2 0x0098 +#define WCD934X_DMA_CH_0_1_CFG_RDMA_2 0x0099 +#define WCD934X_DMA_RDMA_CTL_3 0x009A +#define WCD934X_DMA_CH_2_3_CFG_RDMA_3 0x009B +#define WCD934X_DMA_CH_0_1_CFG_RDMA_3 0x009C +#define WCD934X_DMA_RDMA_CTL_4 0x009D +#define WCD934X_DMA_CH_2_3_CFG_RDMA_4 0x009E +#define WCD934X_DMA_CH_0_1_CFG_RDMA_4 0x009F +#define WCD934X_DMA_RDMA4_PRT_CFG 0x00b1 +#define WCD934X_DMA_RDMA_SBTX0_7_CFG 0x00b9 +#define WCD934X_DMA_RDMA_SBTX8_11_CFG 0x00ba +#define WCD934X_DMA_WDMA_CTL_0 0x00c1 +#define WCD934X_DMA_CH_4_5_CFG_WDMA_0 0x00c2 +#define WCD934X_DMA_CH_2_3_CFG_WDMA_0 0x00c3 +#define WCD934X_DMA_CH_0_1_CFG_WDMA_0 0x00c4 +#define WCD934X_DMA_WDMA_CTL_1 0x00C6 +#define WCD934X_DMA_CH_4_5_CFG_WDMA_1 0x00C7 +#define WCD934X_DMA_CH_2_3_CFG_WDMA_1 0x00C8 +#define WCD934X_DMA_CH_0_1_CFG_WDMA_1 0x00C9 +#define WCD934X_DMA_WDMA_CTL_2 0x00CB +#define WCD934X_DMA_CH_4_5_CFG_WDMA_2 0x00CC +#define WCD934X_DMA_CH_2_3_CFG_WDMA_2 0x00CD +#define WCD934X_DMA_CH_0_1_CFG_WDMA_2 0x00CE +#define WCD934X_DMA_WDMA_CTL_3 0x00D0 +#define WCD934X_DMA_CH_4_5_CFG_WDMA_3 0x00D1 +#define WCD934X_DMA_CH_2_3_CFG_WDMA_3 0x00D2 +#define WCD934X_DMA_CH_0_1_CFG_WDMA_3 0x00D3 +#define WCD934X_DMA_WDMA_CTL_4 0x00D5 +#define WCD934X_DMA_CH_4_5_CFG_WDMA_4 0x00D6 +#define WCD934X_DMA_CH_2_3_CFG_WDMA_4 0x00D7 +#define WCD934X_DMA_CH_0_1_CFG_WDMA_4 0x00D8 +#define WCD934X_DMA_WDMA0_PRT_CFG 0x00E1 +#define WCD934X_DMA_WDMA3_PRT_CFG 0x00E2 +#define WCD934X_DMA_WDMA4_PRT0_3_CFG 0x00E3 +#define WCD934X_DMA_WDMA4_PRT4_7_CFG 0x00E4 +#define WCD934X_PAGE1_PAGE_REGISTER 0x0100 +#define WCD934X_CPE_FLL_USER_CTL_0 0x0101 +#define WCD934X_CPE_FLL_USER_CTL_1 0x0102 +#define WCD934X_CPE_FLL_USER_CTL_2 0x0103 +#define WCD934X_CPE_FLL_USER_CTL_3 0x0104 +#define WCD934X_CPE_FLL_USER_CTL_4 0x0105 +#define WCD934X_CPE_FLL_USER_CTL_5 0x0106 +#define WCD934X_CPE_FLL_USER_CTL_6 0x0107 +#define WCD934X_CPE_FLL_USER_CTL_7 0x0108 +#define WCD934X_CPE_FLL_USER_CTL_8 0x0109 +#define WCD934X_CPE_FLL_USER_CTL_9 0x010a +#define WCD934X_CPE_FLL_L_VAL_CTL_0 0x010b +#define WCD934X_CPE_FLL_L_VAL_CTL_1 0x010c +#define WCD934X_CPE_FLL_DSM_FRAC_CTL_0 0x010d +#define WCD934X_CPE_FLL_DSM_FRAC_CTL_1 0x010e +#define WCD934X_CPE_FLL_CONFIG_CTL_0 0x010f +#define WCD934X_CPE_FLL_CONFIG_CTL_1 0x0110 +#define WCD934X_CPE_FLL_CONFIG_CTL_2 0x0111 +#define WCD934X_CPE_FLL_CONFIG_CTL_3 0x0112 +#define WCD934X_CPE_FLL_CONFIG_CTL_4 0x0113 +#define WCD934X_CPE_FLL_TEST_CTL_0 0x0114 +#define WCD934X_CPE_FLL_TEST_CTL_1 0x0115 +#define WCD934X_CPE_FLL_TEST_CTL_2 0x0116 +#define WCD934X_CPE_FLL_TEST_CTL_3 0x0117 +#define WCD934X_CPE_FLL_TEST_CTL_4 0x0118 +#define WCD934X_CPE_FLL_TEST_CTL_5 0x0119 +#define WCD934X_CPE_FLL_TEST_CTL_6 0x011a +#define WCD934X_CPE_FLL_TEST_CTL_7 0x011b +#define WCD934X_CPE_FLL_FREQ_CTL_0 0x011c +#define WCD934X_CPE_FLL_FREQ_CTL_1 0x011d +#define WCD934X_CPE_FLL_FREQ_CTL_2 0x011e +#define WCD934X_CPE_FLL_FREQ_CTL_3 0x011f +#define WCD934X_CPE_FLL_SSC_CTL_0 0x0120 +#define WCD934X_CPE_FLL_SSC_CTL_1 0x0121 +#define WCD934X_CPE_FLL_SSC_CTL_2 0x0122 +#define WCD934X_CPE_FLL_SSC_CTL_3 0x0123 +#define WCD934X_CPE_FLL_FLL_MODE 0x0124 +#define WCD934X_CPE_FLL_STATUS_0 0x0125 +#define WCD934X_CPE_FLL_STATUS_1 0x0126 +#define WCD934X_CPE_FLL_STATUS_2 0x0127 +#define WCD934X_CPE_FLL_STATUS_3 0x0128 +#define WCD934X_I2S_FLL_USER_CTL_0 0x0141 +#define WCD934X_I2S_FLL_USER_CTL_1 0x0142 +#define WCD934X_I2S_FLL_USER_CTL_2 0x0143 +#define WCD934X_I2S_FLL_USER_CTL_3 0x0144 +#define WCD934X_I2S_FLL_USER_CTL_4 0x0145 +#define WCD934X_I2S_FLL_USER_CTL_5 0x0146 +#define WCD934X_I2S_FLL_USER_CTL_6 0x0147 +#define WCD934X_I2S_FLL_USER_CTL_7 0x0148 +#define WCD934X_I2S_FLL_USER_CTL_8 0x0149 +#define WCD934X_I2S_FLL_USER_CTL_9 0x014a +#define WCD934X_I2S_FLL_L_VAL_CTL_0 0x014b +#define WCD934X_I2S_FLL_L_VAL_CTL_1 0x014c +#define WCD934X_I2S_FLL_DSM_FRAC_CTL_0 0x014d +#define WCD934X_I2S_FLL_DSM_FRAC_CTL_1 0x014e +#define WCD934X_I2S_FLL_CONFIG_CTL_0 0x014f +#define WCD934X_I2S_FLL_CONFIG_CTL_1 0x0150 +#define WCD934X_I2S_FLL_CONFIG_CTL_2 0x0151 +#define WCD934X_I2S_FLL_CONFIG_CTL_3 0x0152 +#define WCD934X_I2S_FLL_CONFIG_CTL_4 0x0153 +#define WCD934X_I2S_FLL_TEST_CTL_0 0x0154 +#define WCD934X_I2S_FLL_TEST_CTL_1 0x0155 +#define WCD934X_I2S_FLL_TEST_CTL_2 0x0156 +#define WCD934X_I2S_FLL_TEST_CTL_3 0x0157 +#define WCD934X_I2S_FLL_TEST_CTL_4 0x0158 +#define WCD934X_I2S_FLL_TEST_CTL_5 0x0159 +#define WCD934X_I2S_FLL_TEST_CTL_6 0x015a +#define WCD934X_I2S_FLL_TEST_CTL_7 0x015b +#define WCD934X_I2S_FLL_FREQ_CTL_0 0x015c +#define WCD934X_I2S_FLL_FREQ_CTL_1 0x015d +#define WCD934X_I2S_FLL_FREQ_CTL_2 0x015e +#define WCD934X_I2S_FLL_FREQ_CTL_3 0x015f +#define WCD934X_I2S_FLL_SSC_CTL_0 0x0160 +#define WCD934X_I2S_FLL_SSC_CTL_1 0x0161 +#define WCD934X_I2S_FLL_SSC_CTL_2 0x0162 +#define WCD934X_I2S_FLL_SSC_CTL_3 0x0163 +#define WCD934X_I2S_FLL_FLL_MODE 0x0164 +#define WCD934X_I2S_FLL_STATUS_0 0x0165 +#define WCD934X_I2S_FLL_STATUS_1 0x0166 +#define WCD934X_I2S_FLL_STATUS_2 0x0167 +#define WCD934X_I2S_FLL_STATUS_3 0x0168 +#define WCD934X_SB_FLL_USER_CTL_0 0x0181 +#define WCD934X_SB_FLL_USER_CTL_1 0x0182 +#define WCD934X_SB_FLL_USER_CTL_2 0x0183 +#define WCD934X_SB_FLL_USER_CTL_3 0x0184 +#define WCD934X_SB_FLL_USER_CTL_4 0x0185 +#define WCD934X_SB_FLL_USER_CTL_5 0x0186 +#define WCD934X_SB_FLL_USER_CTL_6 0x0187 +#define WCD934X_SB_FLL_USER_CTL_7 0x0188 +#define WCD934X_SB_FLL_USER_CTL_8 0x0189 +#define WCD934X_SB_FLL_USER_CTL_9 0x018a +#define WCD934X_SB_FLL_L_VAL_CTL_0 0x018b +#define WCD934X_SB_FLL_L_VAL_CTL_1 0x018c +#define WCD934X_SB_FLL_DSM_FRAC_CTL_0 0x018d +#define WCD934X_SB_FLL_DSM_FRAC_CTL_1 0x018e +#define WCD934X_SB_FLL_CONFIG_CTL_0 0x018f +#define WCD934X_SB_FLL_CONFIG_CTL_1 0x0190 +#define WCD934X_SB_FLL_CONFIG_CTL_2 0x0191 +#define WCD934X_SB_FLL_CONFIG_CTL_3 0x0192 +#define WCD934X_SB_FLL_CONFIG_CTL_4 0x0193 +#define WCD934X_SB_FLL_TEST_CTL_0 0x0194 +#define WCD934X_SB_FLL_TEST_CTL_1 0x0195 +#define WCD934X_SB_FLL_TEST_CTL_2 0x0196 +#define WCD934X_SB_FLL_TEST_CTL_3 0x0197 +#define WCD934X_SB_FLL_TEST_CTL_4 0x0198 +#define WCD934X_SB_FLL_TEST_CTL_5 0x0199 +#define WCD934X_SB_FLL_TEST_CTL_6 0x019a +#define WCD934X_SB_FLL_TEST_CTL_7 0x019b +#define WCD934X_SB_FLL_FREQ_CTL_0 0x019c +#define WCD934X_SB_FLL_FREQ_CTL_1 0x019d +#define WCD934X_SB_FLL_FREQ_CTL_2 0x019e +#define WCD934X_SB_FLL_FREQ_CTL_3 0x019f +#define WCD934X_SB_FLL_SSC_CTL_0 0x01a0 +#define WCD934X_SB_FLL_SSC_CTL_1 0x01a1 +#define WCD934X_SB_FLL_SSC_CTL_2 0x01a2 +#define WCD934X_SB_FLL_SSC_CTL_3 0x01a3 +#define WCD934X_SB_FLL_FLL_MODE 0x01a4 +#define WCD934X_SB_FLL_STATUS_0 0x01a5 +#define WCD934X_SB_FLL_STATUS_1 0x01a6 +#define WCD934X_SB_FLL_STATUS_2 0x01a7 +#define WCD934X_SB_FLL_STATUS_3 0x01a8 +#define WCD934X_PAGE2_PAGE_REGISTER 0x0200 +#define WCD934X_CPE_SS_CPE_CTL 0x0201 +#define WCD934X_CPE_SS_PWR_SYS_PSTATE_CTL_0 0x0202 +#define WCD934X_CPE_SS_PWR_SYS_PSTATE_CTL_1 0x0203 +#define WCD934X_CPE_SS_PWR_CPEFLL_CTL 0x0204 +#define WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_0 0x0205 +#define WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_1 0x0206 +#define WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_OVERRIDE 0x0207 +#define WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_0 0x0208 +#define WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_1 0x0209 +#define WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_2 0x020a +#define WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_3 0x020b +#define WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_4 0x020c +#define WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_5 0x020d +#define WCD934X_CPE_SS_PWR_CPE_DRAM1_SHUTDOWN 0x020e +#define WCD934X_CPE_SS_SOC_SW_COLLAPSE_CTL 0x020f +#define WCD934X_CPE_SS_SOC_SW_COLLAPSE_OVERRIDE_CTL 0x0210 +#define WCD934X_CPE_SS_SOC_SW_COLLAPSE_OVERRIDE_CTL1 0x0211 +#define WCD934X_CPE_SS_US_BUF_INT_PERIOD 0x0212 +#define WCD934X_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD 0x0213 +#define WCD934X_CPE_SS_SVA_CFG 0x0214 +#define WCD934X_CPE_SS_US_CFG 0x0215 +#define WCD934X_CPE_SS_MAD_CTL 0x0216 +#define WCD934X_CPE_SS_CPAR_CTL 0x0217 +#define WCD934X_CPE_SS_DMIC0_CTL 0x0218 +#define WCD934X_CPE_SS_DMIC1_CTL 0x0219 +#define WCD934X_CPE_SS_DMIC2_CTL 0x021a +#define WCD934X_CPE_SS_DMIC_CFG 0x021b +#define WCD934X_CPE_SS_CPAR_CFG 0x021c +#define WCD934X_CPE_SS_WDOG_CFG 0x021d +#define WCD934X_CPE_SS_BACKUP_INT 0x021e +#define WCD934X_CPE_SS_STATUS 0x021f +#define WCD934X_CPE_SS_CPE_OCD_CFG 0x0220 +#define WCD934X_CPE_SS_SS_ERROR_INT_MASK_0A 0x0221 +#define WCD934X_CPE_SS_SS_ERROR_INT_MASK_0B 0x0222 +#define WCD934X_CPE_SS_SS_ERROR_INT_MASK_1A 0x0223 +#define WCD934X_CPE_SS_SS_ERROR_INT_MASK_1B 0x0224 +#define WCD934X_CPE_SS_SS_ERROR_INT_STATUS_0A 0x0225 +#define WCD934X_CPE_SS_SS_ERROR_INT_STATUS_0B 0x0226 +#define WCD934X_CPE_SS_SS_ERROR_INT_STATUS_1A 0x0227 +#define WCD934X_CPE_SS_SS_ERROR_INT_STATUS_1B 0x0228 +#define WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_0A 0x0229 +#define WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_0B 0x022a +#define WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_1A 0x022b +#define WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_1B 0x022c +#define WCD934X_SOC_MAD_MAIN_CTL_1 0x0281 +#define WCD934X_SOC_MAD_MAIN_CTL_2 0x0282 +#define WCD934X_SOC_MAD_AUDIO_CTL_1 0x0283 +#define WCD934X_SOC_MAD_AUDIO_CTL_2 0x0284 +#define WCD934X_SOC_MAD_AUDIO_CTL_3 0x0285 +#define WCD934X_SOC_MAD_AUDIO_CTL_4 0x0286 +#define WCD934X_SOC_MAD_AUDIO_CTL_5 0x0287 +#define WCD934X_SOC_MAD_AUDIO_CTL_6 0x0288 +#define WCD934X_SOC_MAD_AUDIO_CTL_7 0x0289 +#define WCD934X_SOC_MAD_AUDIO_CTL_8 0x028a +#define WCD934X_SOC_MAD_AUDIO_IIR_CTL_PTR 0x028b +#define WCD934X_SOC_MAD_AUDIO_IIR_CTL_VAL 0x028c +#define WCD934X_SOC_MAD_ULTR_CTL_1 0x028d +#define WCD934X_SOC_MAD_ULTR_CTL_2 0x028e +#define WCD934X_SOC_MAD_ULTR_CTL_3 0x028f +#define WCD934X_SOC_MAD_ULTR_CTL_4 0x0290 +#define WCD934X_SOC_MAD_ULTR_CTL_5 0x0291 +#define WCD934X_SOC_MAD_ULTR_CTL_6 0x0292 +#define WCD934X_SOC_MAD_ULTR_CTL_7 0x0293 +#define WCD934X_SOC_MAD_BEACON_CTL_1 0x0294 +#define WCD934X_SOC_MAD_BEACON_CTL_2 0x0295 +#define WCD934X_SOC_MAD_BEACON_CTL_3 0x0296 +#define WCD934X_SOC_MAD_BEACON_CTL_4 0x0297 +#define WCD934X_SOC_MAD_BEACON_CTL_5 0x0298 +#define WCD934X_SOC_MAD_BEACON_CTL_6 0x0299 +#define WCD934X_SOC_MAD_BEACON_CTL_7 0x029a +#define WCD934X_SOC_MAD_BEACON_CTL_8 0x029b +#define WCD934X_SOC_MAD_BEACON_IIR_CTL_PTR 0x029c +#define WCD934X_SOC_MAD_BEACON_IIR_CTL_VAL 0x029d +#define WCD934X_SOC_MAD_INP_SEL 0x029e +#define WCD934X_PAGE4_PAGE_REGISTER 0x0400 +#define WCD934X_INTR_CFG 0x0401 +#define WCD934X_INTR_CLR_COMMIT 0x0402 +#define WCD934X_INTR_PIN1_MASK0 0x0409 +#define WCD934X_INTR_PIN1_MASK1 0x040a +#define WCD934X_INTR_PIN1_MASK2 0x040b +#define WCD934X_INTR_PIN1_MASK3 0x040c +#define WCD934X_INTR_PIN1_STATUS0 0x0411 +#define WCD934X_INTR_PIN1_STATUS1 0x0412 +#define WCD934X_INTR_PIN1_STATUS2 0x0413 +#define WCD934X_INTR_PIN1_STATUS3 0x0414 +#define WCD934X_INTR_PIN1_CLEAR0 0x0419 +#define WCD934X_INTR_PIN1_CLEAR1 0x041a +#define WCD934X_INTR_PIN1_CLEAR2 0x041b +#define WCD934X_INTR_PIN1_CLEAR3 0x041c +#define WCD934X_INTR_PIN2_MASK3 0x0424 +#define WCD934X_INTR_PIN2_STATUS3 0x042c +#define WCD934X_INTR_PIN2_CLEAR3 0x0434 +#define WCD934X_INTR_CPESS_SUMRY_MASK2 0x043b +#define WCD934X_INTR_CPESS_SUMRY_MASK3 0x043c +#define WCD934X_INTR_CPESS_SUMRY_STATUS2 0x0443 +#define WCD934X_INTR_CPESS_SUMRY_STATUS3 0x0444 +#define WCD934X_INTR_CPESS_SUMRY_CLEAR2 0x044b +#define WCD934X_INTR_CPESS_SUMRY_CLEAR3 0x044c +#define WCD934X_INTR_LEVEL0 0x0461 +#define WCD934X_INTR_LEVEL1 0x0462 +#define WCD934X_INTR_LEVEL2 0x0463 +#define WCD934X_INTR_LEVEL3 0x0464 +#define WCD934X_INTR_BYPASS0 0x0469 +#define WCD934X_INTR_BYPASS1 0x046a +#define WCD934X_INTR_BYPASS2 0x046b +#define WCD934X_INTR_BYPASS3 0x046c +#define WCD934X_INTR_SET0 0x0471 +#define WCD934X_INTR_SET1 0x0472 +#define WCD934X_INTR_SET2 0x0473 +#define WCD934X_INTR_SET3 0x0474 +#define WCD934X_INTR_CODEC_MISC_MASK 0x04b1 +#define WCD934X_INTR_CODEC_MISC_STATUS 0x04b2 +#define WCD934X_INTR_CODEC_MISC_CLEAR 0x04b3 +#define WCD934X_PAGE5_PAGE_REGISTER 0x0500 +#define WCD934X_SLNQ_DIG_DEVICE 0x0501 +#define WCD934X_SLNQ_DIG_REVISION 0x0502 +#define WCD934X_SLNQ_DIG_H_COMMAND 0x0511 +#define WCD934X_SLNQ_DIG_NUMBER_OF_BYTE_MSB 0x0512 +#define WCD934X_SLNQ_DIG_NUMBER_OF_BYTE_LSB 0x0513 +#define WCD934X_SLNQ_DIG_MASTER_ADDRESS_MSB 0x0514 +#define WCD934X_SLNQ_DIG_MASTER_ADDRESS_LSB 0x0515 +#define WCD934X_SLNQ_DIG_SLAVE_ADDRESS_MSB 0x0516 +#define WCD934X_SLNQ_DIG_SLAVE_ADDRESS_LSB 0x0517 +#define WCD934X_SLNQ_DIG_TIMER0_INTERRUPT_MSB 0x0518 +#define WCD934X_SLNQ_DIG_TIMER0_INTERRUPT_LSB 0x0519 +#define WCD934X_SLNQ_DIG_TIMER1_INTERRUPT_MSB 0x051a +#define WCD934X_SLNQ_DIG_TIMER1_INTERRUPT_LSB 0x051b +#define WCD934X_SLNQ_DIG_TIMER2_INTERRUPT_MSB 0x051c +#define WCD934X_SLNQ_DIG_TIMER2_INTERRUPT_LSB 0x051d +#define WCD934X_SLNQ_DIG_COMM_CTL 0x0520 +#define WCD934X_SLNQ_DIG_FRAME_CTRL 0x0542 +#define WCD934X_SLNQ_DIG_PDM_2ND_DATA_CH1_2 0x055c +#define WCD934X_SLNQ_DIG_PDM_2ND_DATA_CH3_4 0x055d +#define WCD934X_SLNQ_DIG_PDM_2ND_DATA_CH5 0x055e +#define WCD934X_SLNQ_DIG_SW_EVENT_RD 0x0561 +#define WCD934X_SLNQ_DIG_SW_EVENT_CTRL 0x0562 +#define WCD934X_SLNQ_DIG_PDM_SELECT_1 0x0563 +#define WCD934X_SLNQ_DIG_PDM_SELECT_2 0x0564 +#define WCD934X_SLNQ_DIG_PDM_SELECT_3 0x0565 +#define WCD934X_SLNQ_DIG_PDM_SAMPLING_FREQ 0x0566 +#define WCD934X_SLNQ_DIG_PDM_DC_CONVERSION_CTL 0x0569 +#define WCD934X_SLNQ_DIG_PDM_DC_CONVERSION_SEL 0x056a +#define WCD934X_SLNQ_DIG_PDM_DC_CONV_CHA_MSB 0x056b +#define WCD934X_SLNQ_DIG_PDM_DC_CONV_CHA_LSB 0x056c +#define WCD934X_SLNQ_DIG_PDM_DC_CONV_CHB_MSB 0x056d +#define WCD934X_SLNQ_DIG_PDM_DC_CONV_CHB_LSB 0x056e +#define WCD934X_SLNQ_DIG_RAM_CNTRL 0x0571 +#define WCD934X_SLNQ_DIG_SRAM_BANK 0x0572 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_0 0x0573 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_1 0x0574 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_2 0x0575 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_3 0x0576 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_4 0x0577 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_5 0x0578 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_6 0x0579 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_7 0x057a +#define WCD934X_SLNQ_DIG_SRAM_BYTE_8 0x057b +#define WCD934X_SLNQ_DIG_SRAM_BYTE_9 0x057c +#define WCD934X_SLNQ_DIG_SRAM_BYTE_A 0x057d +#define WCD934X_SLNQ_DIG_SRAM_BYTE_B 0x057e +#define WCD934X_SLNQ_DIG_SRAM_BYTE_C 0x057f +#define WCD934X_SLNQ_DIG_SRAM_BYTE_D 0x0580 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_E 0x0581 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_F 0x0582 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_10 0x0583 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_11 0x0584 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_12 0x0585 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_13 0x0586 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_14 0x0587 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_15 0x0588 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_16 0x0589 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_17 0x058a +#define WCD934X_SLNQ_DIG_SRAM_BYTE_18 0x058b +#define WCD934X_SLNQ_DIG_SRAM_BYTE_19 0x058c +#define WCD934X_SLNQ_DIG_SRAM_BYTE_1A 0x058d +#define WCD934X_SLNQ_DIG_SRAM_BYTE_1B 0x058e +#define WCD934X_SLNQ_DIG_SRAM_BYTE_1C 0x058f +#define WCD934X_SLNQ_DIG_SRAM_BYTE_1D 0x0590 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_1E 0x0591 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_1F 0x0592 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_20 0x0593 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_21 0x0594 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_22 0x0595 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_23 0x0596 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_24 0x0597 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_25 0x0598 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_26 0x0599 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_27 0x059a +#define WCD934X_SLNQ_DIG_SRAM_BYTE_28 0x059b +#define WCD934X_SLNQ_DIG_SRAM_BYTE_29 0x059c +#define WCD934X_SLNQ_DIG_SRAM_BYTE_2A 0x059d +#define WCD934X_SLNQ_DIG_SRAM_BYTE_2B 0x059e +#define WCD934X_SLNQ_DIG_SRAM_BYTE_2C 0x059f +#define WCD934X_SLNQ_DIG_SRAM_BYTE_2D 0x05a0 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_2E 0x05a1 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_2F 0x05a2 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_30 0x05a3 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_31 0x05a4 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_32 0x05a5 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_33 0x05a6 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_34 0x05a7 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_35 0x05a8 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_36 0x05a9 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_37 0x05aa +#define WCD934X_SLNQ_DIG_SRAM_BYTE_38 0x05ab +#define WCD934X_SLNQ_DIG_SRAM_BYTE_39 0x05ac +#define WCD934X_SLNQ_DIG_SRAM_BYTE_3A 0x05ad +#define WCD934X_SLNQ_DIG_SRAM_BYTE_3B 0x05ae +#define WCD934X_SLNQ_DIG_SRAM_BYTE_3C 0x05af +#define WCD934X_SLNQ_DIG_SRAM_BYTE_3D 0x05b0 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_3E 0x05b1 +#define WCD934X_SLNQ_DIG_SRAM_BYTE_3F 0x05b2 +#define WCD934X_SLNQ_DIG_TOP_CTRL1 0x05b3 +#define WCD934X_SLNQ_DIG_TOP_CTRL2 0x05b4 +#define WCD934X_SLNQ_DIG_PDM_CTRL 0x05b5 +#define WCD934X_SLNQ_DIG_PDM_MUTE_CTRL 0x05b6 +#define WCD934X_SLNQ_DIG_DEC_BYPASS_CTRL 0x05b7 +#define WCD934X_SLNQ_DIG_DEC_BYPASS_STATUS 0x05b8 +#define WCD934X_SLNQ_DIG_DEC_BYPASS_FS 0x05b9 +#define WCD934X_SLNQ_DIG_DEC_BYPASS_IN_SEL 0x05ba +#define WCD934X_SLNQ_DIG_GPOUT_ENABLE 0x05bb +#define WCD934X_SLNQ_DIG_GPOUT_VAL 0x05bc +#define WCD934X_SLNQ_DIG_ANA_INTERRUPT_MASK 0x05be +#define WCD934X_SLNQ_DIG_ANA_INTERRUPT_STATUS 0x05bf +#define WCD934X_SLNQ_DIG_ANA_INTERRUPT_CLR 0x05c0 +#define WCD934X_SLNQ_DIG_IP_TESTING 0x05c1 +#define WCD934X_SLNQ_DIG_INTERRUPT_CNTRL 0x05e3 +#define WCD934X_SLNQ_DIG_INTERRUPT_CNT 0x05e9 +#define WCD934X_SLNQ_DIG_INTERRUPT_CNT_MSB 0x05eb +#define WCD934X_SLNQ_DIG_INTERRUPT_CNT_LSB 0x05ec +#define WCD934X_SLNQ_DIG_INTERRUPT_MASK0 0x05f1 +#define WCD934X_SLNQ_DIG_INTERRUPT_MASK1 0x05f2 +#define WCD934X_SLNQ_DIG_INTERRUPT_MASK2 0x05f3 +#define WCD934X_SLNQ_DIG_INTERRUPT_MASK3 0x05f4 +#define WCD934X_SLNQ_DIG_INTERRUPT_MASK4 0x05f5 +#define WCD934X_SLNQ_DIG_INTERRUPT_STATUS0 0x05f6 +#define WCD934X_SLNQ_DIG_INTERRUPT_STATUS1 0x05f7 +#define WCD934X_SLNQ_DIG_INTERRUPT_STATUS2 0x05f8 +#define WCD934X_SLNQ_DIG_INTERRUPT_STATUS3 0x05f9 +#define WCD934X_SLNQ_DIG_INTERRUPT_STATUS4 0x05fa +#define WCD934X_SLNQ_DIG_INTERRUPT_CLR0 0x05fb +#define WCD934X_SLNQ_DIG_INTERRUPT_CLR1 0x05fc +#define WCD934X_SLNQ_DIG_INTERRUPT_CLR2 0x05fd +#define WCD934X_SLNQ_DIG_INTERRUPT_CLR3 0x05fe +#define WCD934X_SLNQ_DIG_INTERRUPT_CLR4 0x05ff +#define WCD934X_ANA_PAGE_REGISTER 0x0600 +#define WCD934X_ANA_BIAS 0x0601 +#define WCD934X_ANA_RCO 0x0603 +#define WCD934X_ANA_PAGE6_SPARE2 0x0604 +#define WCD934X_ANA_PAGE6_SPARE3 0x0605 +#define WCD934X_ANA_BUCK_CTL 0x0606 +#define WCD934X_ANA_BUCK_STATUS 0x0607 +#define WCD934X_ANA_RX_SUPPLIES 0x0608 +#define WCD934X_ANA_HPH 0x0609 +#define WCD934X_ANA_EAR 0x060a +#define WCD934X_ANA_LO_1_2 0x060b +#define WCD934X_ANA_MAD_SETUP 0x060d +#define WCD934X_ANA_AMIC1 0x060e +#define WCD934X_ANA_AMIC2 0x060f +#define WCD934X_ANA_AMIC3 0x0610 +#define WCD934X_ANA_AMIC4 0x0611 +#define WCD934X_ANA_MBHC_MECH 0x0614 +#define WCD934X_ANA_MBHC_ELECT 0x0615 +#define WCD934X_ANA_MBHC_ZDET 0x0616 +#define WCD934X_ANA_MBHC_RESULT_1 0x0617 +#define WCD934X_ANA_MBHC_RESULT_2 0x0618 +#define WCD934X_ANA_MBHC_RESULT_3 0x0619 +#define WCD934X_ANA_MBHC_BTN0 0x061a +#define WCD934X_ANA_MBHC_BTN1 0x061b +#define WCD934X_ANA_MBHC_BTN2 0x061c +#define WCD934X_ANA_MBHC_BTN3 0x061d +#define WCD934X_ANA_MBHC_BTN4 0x061e +#define WCD934X_ANA_MBHC_BTN5 0x061f +#define WCD934X_ANA_MBHC_BTN6 0x0620 +#define WCD934X_ANA_MBHC_BTN7 0x0621 +#define WCD934X_ANA_MICB1 0x0622 +#define WCD934X_ANA_MICB2 0x0623 +#define WCD934X_ANA_MICB2_RAMP 0x0624 +#define WCD934X_ANA_MICB3 0x0625 +#define WCD934X_ANA_MICB4 0x0626 +#define WCD934X_ANA_VBADC 0x0627 +#define WCD934X_BIAS_CTL 0x0628 +#define WCD934X_BIAS_VBG_FINE_ADJ 0x0629 +#define WCD934X_RCO_CTRL_1 0x062e +#define WCD934X_RCO_CTRL_2 0x062f +#define WCD934X_RCO_CAL 0x0630 +#define WCD934X_RCO_CAL_1 0x0631 +#define WCD934X_RCO_CAL_2 0x0632 +#define WCD934X_RCO_TEST_CTRL 0x0633 +#define WCD934X_RCO_CAL_OUT_1 0x0634 +#define WCD934X_RCO_CAL_OUT_2 0x0635 +#define WCD934X_RCO_CAL_OUT_3 0x0636 +#define WCD934X_RCO_CAL_OUT_4 0x0637 +#define WCD934X_RCO_CAL_OUT_5 0x0638 +#define WCD934X_SIDO_MODE_1 0x063a +#define WCD934X_SIDO_MODE_2 0x063b +#define WCD934X_SIDO_MODE_3 0x063c +#define WCD934X_SIDO_MODE_4 0x063d +#define WCD934X_SIDO_VCL_1 0x063e +#define WCD934X_SIDO_VCL_2 0x063f +#define WCD934X_SIDO_VCL_3 0x0640 +#define WCD934X_SIDO_CCL_1 0x0641 +#define WCD934X_SIDO_CCL_2 0x0642 +#define WCD934X_SIDO_CCL_3 0x0643 +#define WCD934X_SIDO_CCL_4 0x0644 +#define WCD934X_SIDO_CCL_5 0x0645 +#define WCD934X_SIDO_CCL_6 0x0646 +#define WCD934X_SIDO_CCL_7 0x0647 +#define WCD934X_SIDO_CCL_8 0x0648 +#define WCD934X_SIDO_CCL_9 0x0649 +#define WCD934X_SIDO_CCL_10 0x064a +#define WCD934X_SIDO_FILTER_1 0x064b +#define WCD934X_SIDO_FILTER_2 0x064c +#define WCD934X_SIDO_DRIVER_1 0x064d +#define WCD934X_SIDO_DRIVER_2 0x064e +#define WCD934X_SIDO_DRIVER_3 0x064f +#define WCD934X_SIDO_CAL_CODE_EXT_1 0x0650 +#define WCD934X_SIDO_CAL_CODE_EXT_2 0x0651 +#define WCD934X_SIDO_CAL_CODE_OUT_1 0x0652 +#define WCD934X_SIDO_CAL_CODE_OUT_2 0x0653 +#define WCD934X_SIDO_TEST_1 0x0654 +#define WCD934X_SIDO_TEST_2 0x0655 +#define WCD934X_MBHC_CTL_CLK 0x0656 +#define WCD934X_MBHC_CTL_ANA 0x0657 +#define WCD934X_MBHC_CTL_SPARE_1 0x0658 +#define WCD934X_MBHC_CTL_SPARE_2 0x0659 +#define WCD934X_MBHC_CTL_BCS 0x065a +#define WCD934X_MBHC_STATUS_SPARE_1 0x065b +#define WCD934X_MBHC_TEST_CTL 0x065c +#define WCD934X_VBADC_SUBBLOCK_EN 0x065d +#define WCD934X_VBADC_IBIAS_FE 0x065e +#define WCD934X_VBADC_BIAS_ADC 0x065f +#define WCD934X_VBADC_FE_CTRL 0x0660 +#define WCD934X_VBADC_ADC_REF 0x0661 +#define WCD934X_VBADC_ADC_IO 0x0662 +#define WCD934X_VBADC_ADC_SAR 0x0663 +#define WCD934X_VBADC_DEBUG 0x0664 +#define WCD934X_LDOH_MODE 0x0667 +#define WCD934X_LDOH_BIAS 0x0668 +#define WCD934X_LDOH_STB_LOADS 0x0669 +#define WCD934X_LDOH_SLOWRAMP 0x066a +#define WCD934X_MICB1_TEST_CTL_1 0x066b +#define WCD934X_MICB1_TEST_CTL_2 0x066c +#define WCD934X_MICB1_TEST_CTL_3 0x066d +#define WCD934X_MICB2_TEST_CTL_1 0x066e +#define WCD934X_MICB2_TEST_CTL_2 0x066f +#define WCD934X_MICB2_TEST_CTL_3 0x0670 +#define WCD934X_MICB3_TEST_CTL_1 0x0671 +#define WCD934X_MICB3_TEST_CTL_2 0x0672 +#define WCD934X_MICB3_TEST_CTL_3 0x0673 +#define WCD934X_MICB4_TEST_CTL_1 0x0674 +#define WCD934X_MICB4_TEST_CTL_2 0x0675 +#define WCD934X_MICB4_TEST_CTL_3 0x0676 +#define WCD934X_TX_COM_ADC_VCM 0x0677 +#define WCD934X_TX_COM_BIAS_ATEST 0x0678 +#define WCD934X_TX_COM_ADC_INT1_IB 0x0679 +#define WCD934X_TX_COM_ADC_INT2_IB 0x067a +#define WCD934X_TX_COM_TXFE_DIV_CTL 0x067b +#define WCD934X_TX_COM_TXFE_DIV_START 0x067c +#define WCD934X_TX_COM_TXFE_DIV_STOP_9P6M 0x067d +#define WCD934X_TX_COM_TXFE_DIV_STOP_12P288M 0x067e +#define WCD934X_TX_1_2_TEST_EN 0x067f +#define WCD934X_TX_1_2_ADC_IB 0x0680 +#define WCD934X_TX_1_2_ATEST_REFCTL 0x0681 +#define WCD934X_TX_1_2_TEST_CTL 0x0682 +#define WCD934X_TX_1_2_TEST_BLK_EN 0x0683 +#define WCD934X_TX_1_2_TXFE_CLKDIV 0x0684 +#define WCD934X_TX_1_2_SAR1_ERR 0x0685 +#define WCD934X_TX_1_2_SAR2_ERR 0x0686 +#define WCD934X_TX_3_4_TEST_EN 0x0687 +#define WCD934X_TX_3_4_ADC_IB 0x0688 +#define WCD934X_TX_3_4_ATEST_REFCTL 0x0689 +#define WCD934X_TX_3_4_TEST_CTL 0x068a +#define WCD934X_TX_3_4_TEST_BLK_EN 0x068b +#define WCD934X_TX_3_4_TXFE_CLKDIV 0x068c +#define WCD934X_TX_3_4_SAR1_ERR 0x068d +#define WCD934X_TX_3_4_SAR2_ERR 0x068e +#define WCD934X_CLASSH_MODE_1 0x0697 +#define WCD934X_CLASSH_MODE_2 0x0698 +#define WCD934X_CLASSH_MODE_3 0x0699 +#define WCD934X_CLASSH_CTRL_VCL_1 0x069a +#define WCD934X_CLASSH_CTRL_VCL_2 0x069b +#define WCD934X_CLASSH_CTRL_CCL_1 0x069c +#define WCD934X_CLASSH_CTRL_CCL_2 0x069d +#define WCD934X_CLASSH_CTRL_CCL_3 0x069e +#define WCD934X_CLASSH_CTRL_CCL_4 0x069f +#define WCD934X_CLASSH_CTRL_CCL_5 0x06a0 +#define WCD934X_CLASSH_BUCK_TMUX_A_D 0x06a1 +#define WCD934X_CLASSH_BUCK_SW_DRV_CNTL 0x06a2 +#define WCD934X_CLASSH_SPARE 0x06a3 +#define WCD934X_FLYBACK_EN 0x06a4 +#define WCD934X_FLYBACK_VNEG_CTRL_1 0x06a5 +#define WCD934X_FLYBACK_VNEG_CTRL_2 0x06a6 +#define WCD934X_FLYBACK_VNEG_CTRL_3 0x06a7 +#define WCD934X_FLYBACK_VNEG_CTRL_4 0x06a8 +#define WCD934X_FLYBACK_VNEG_CTRL_5 0x06a9 +#define WCD934X_FLYBACK_VNEG_CTRL_6 0x06aa +#define WCD934X_FLYBACK_VNEG_CTRL_7 0x06ab +#define WCD934X_FLYBACK_VNEG_CTRL_8 0x06ac +#define WCD934X_FLYBACK_VNEG_CTRL_9 0x06ad +#define WCD934X_FLYBACK_VNEGDAC_CTRL_1 0x06ae +#define WCD934X_FLYBACK_VNEGDAC_CTRL_2 0x06af +#define WCD934X_FLYBACK_VNEGDAC_CTRL_3 0x06b0 +#define WCD934X_FLYBACK_CTRL_1 0x06b1 +#define WCD934X_FLYBACK_TEST_CTL 0x06b2 +#define WCD934X_RX_AUX_SW_CTL 0x06b3 +#define WCD934X_RX_PA_AUX_IN_CONN 0x06b4 +#define WCD934X_RX_TIMER_DIV 0x06b5 +#define WCD934X_RX_OCP_CTL 0x06b6 +#define WCD934X_RX_OCP_COUNT 0x06b7 +#define WCD934X_RX_BIAS_EAR_DAC 0x06b8 +#define WCD934X_RX_BIAS_EAR_AMP 0x06b9 +#define WCD934X_RX_BIAS_HPH_LDO 0x06ba +#define WCD934X_RX_BIAS_HPH_PA 0x06bb +#define WCD934X_RX_BIAS_HPH_RDACBUFF_CNP2 0x06bc +#define WCD934X_RX_BIAS_HPH_RDAC_LDO 0x06bd +#define WCD934X_RX_BIAS_HPH_CNP1 0x06be +#define WCD934X_RX_BIAS_HPH_LOWPOWER 0x06bf +#define WCD934X_RX_BIAS_DIFFLO_PA 0x06c0 +#define WCD934X_RX_BIAS_DIFFLO_REF 0x06c1 +#define WCD934X_RX_BIAS_DIFFLO_LDO 0x06c2 +#define WCD934X_RX_BIAS_SELO_DAC_PA 0x06c3 +#define WCD934X_RX_BIAS_BUCK_RST 0x06c4 +#define WCD934X_RX_BIAS_BUCK_VREF_ERRAMP 0x06c5 +#define WCD934X_RX_BIAS_FLYB_ERRAMP 0x06c6 +#define WCD934X_RX_BIAS_FLYB_BUFF 0x06c7 +#define WCD934X_RX_BIAS_FLYB_MID_RST 0x06c8 +#define WCD934X_HPH_L_STATUS 0x06c9 +#define WCD934X_HPH_R_STATUS 0x06ca +#define WCD934X_HPH_CNP_EN 0x06cb +#define WCD934X_HPH_CNP_WG_CTL 0x06cc +#define WCD934X_HPH_CNP_WG_TIME 0x06cd +#define WCD934X_HPH_OCP_CTL 0x06ce +#define WCD934X_HPH_AUTO_CHOP 0x06cf +#define WCD934X_HPH_CHOP_CTL 0x06d0 +#define WCD934X_HPH_PA_CTL1 0x06d1 +#define WCD934X_HPH_PA_CTL2 0x06d2 +#define WCD934X_HPH_L_EN 0x06d3 +#define WCD934X_HPH_L_TEST 0x06d4 +#define WCD934X_HPH_L_ATEST 0x06d5 +#define WCD934X_HPH_R_EN 0x06d6 +#define WCD934X_HPH_R_TEST 0x06d7 +#define WCD934X_HPH_R_ATEST 0x06d8 +#define WCD934X_HPH_RDAC_CLK_CTL1 0x06d9 +#define WCD934X_HPH_RDAC_CLK_CTL2 0x06da +#define WCD934X_HPH_RDAC_LDO_CTL 0x06db +#define WCD934X_HPH_RDAC_CHOP_CLK_LP_CTL 0x06dc +#define WCD934X_HPH_REFBUFF_UHQA_CTL 0x06dd +#define WCD934X_HPH_REFBUFF_LP_CTL 0x06de +#define WCD934X_HPH_L_DAC_CTL 0x06df +#define WCD934X_HPH_R_DAC_CTL 0x06e0 +#define WCD934X_EAR_EN_REG 0x06e1 +#define WCD934X_EAR_CMBUFF 0x06e2 +#define WCD934X_EAR_ICTL 0x06e3 +#define WCD934X_EAR_EN_DBG_CTL 0x06e4 +#define WCD934X_EAR_CNP 0x06e5 +#define WCD934X_EAR_DAC_CTL_ATEST 0x06e6 +#define WCD934X_EAR_STATUS_REG 0x06e7 +#define WCD934X_EAR_EAR_MISC 0x06e8 +#define WCD934X_DIFF_LO_MISC 0x06e9 +#define WCD934X_DIFF_LO_LO2_COMPANDER 0x06ea +#define WCD934X_DIFF_LO_LO1_COMPANDER 0x06eb +#define WCD934X_DIFF_LO_COMMON 0x06ec +#define WCD934X_DIFF_LO_BYPASS_EN 0x06ed +#define WCD934X_DIFF_LO_CNP 0x06ee +#define WCD934X_DIFF_LO_CORE_OUT_PROG 0x06ef +#define WCD934X_DIFF_LO_LDO_OUT_PROG 0x06f0 +#define WCD934X_DIFF_LO_COM_SWCAP_REFBUF_FREQ 0x06f1 +#define WCD934X_DIFF_LO_COM_PA_FREQ 0x06f2 +#define WCD934X_DIFF_LO_RESERVED_REG 0x06f3 +#define WCD934X_DIFF_LO_LO1_STATUS_1 0x06f4 +#define WCD934X_DIFF_LO_LO1_STATUS_2 0x06f5 +#define WCD934X_ANA_NEW_PAGE_REGISTER 0x0700 +#define WCD934X_HPH_NEW_ANA_HPH2 0x0701 +#define WCD934X_HPH_NEW_ANA_HPH3 0x0702 +#define WCD934X_SLNQ_ANA_EN 0x0703 +#define WCD934X_SLNQ_ANA_STATUS 0x0704 +#define WCD934X_SLNQ_ANA_LDO_CONFIG 0x0705 +#define WCD934X_SLNQ_ANA_LDO_OCP_CONFIG 0x0706 +#define WCD934X_SLNQ_ANA_TX_LDO_CONFIG 0x0707 +#define WCD934X_SLNQ_ANA_TX_DRV_CONFIG 0x0708 +#define WCD934X_SLNQ_ANA_RX_CONFIG_1 0x0709 +#define WCD934X_SLNQ_ANA_RX_CONFIG_2 0x070a +#define WCD934X_SLNQ_ANA_PLL_ENABLES 0x070b +#define WCD934X_SLNQ_ANA_PLL_PRESET 0x070c +#define WCD934X_SLNQ_ANA_PLL_STATUS 0x070d +#define WCD934X_CLK_SYS_PLL_ENABLES 0x070e +#define WCD934X_CLK_SYS_PLL_PRESET 0x070f +#define WCD934X_CLK_SYS_PLL_STATUS 0x0710 +#define WCD934X_CLK_SYS_MCLK_PRG 0x0711 +#define WCD934X_CLK_SYS_MCLK2_PRG1 0x0712 +#define WCD934X_CLK_SYS_MCLK2_PRG2 0x0713 +#define WCD934X_CLK_SYS_XO_PRG 0x0714 +#define WCD934X_CLK_SYS_XO_CAP_XTP 0x0715 +#define WCD934X_CLK_SYS_XO_CAP_XTM 0x0716 +#define WCD934X_BOOST_BST_EN_DLY 0x0718 +#define WCD934X_BOOST_CTRL_ILIM 0x0719 +#define WCD934X_BOOST_VOUT_SETTING 0x071a +#define WCD934X_SIDO_NEW_VOUT_A_STARTUP 0x071b +#define WCD934X_SIDO_NEW_VOUT_D_STARTUP 0x071c +#define WCD934X_SIDO_NEW_VOUT_D_FREQ1 0x071d +#define WCD934X_SIDO_NEW_VOUT_D_FREQ2 0x071e +#define WCD934X_MBHC_NEW_ELECT_REM_CLAMP_CTL 0x071f +#define WCD934X_MBHC_NEW_CTL_1 0x0720 +#define WCD934X_MBHC_NEW_CTL_2 0x0721 +#define WCD934X_MBHC_NEW_PLUG_DETECT_CTL 0x0722 +#define WCD934X_MBHC_NEW_ZDET_ANA_CTL 0x0723 +#define WCD934X_MBHC_NEW_ZDET_RAMP_CTL 0x0724 +#define WCD934X_MBHC_NEW_FSM_STATUS 0x0725 +#define WCD934X_MBHC_NEW_ADC_RESULT 0x0726 +#define WCD934X_TX_NEW_AMIC_4_5_SEL 0x0727 +#define WCD934X_VBADC_NEW_ADC_MODE 0x072f +#define WCD934X_VBADC_NEW_ADC_DOUTMSB 0x0730 +#define WCD934X_VBADC_NEW_ADC_DOUTLSB 0x0731 +#define WCD934X_HPH_NEW_INT_RDAC_GAIN_CTL 0x0732 +#define WCD934X_HPH_NEW_INT_RDAC_HD2_CTL 0x0733 +#define WCD934X_HPH_NEW_INT_RDAC_HD2_CTL_L 0x0733 +#define WCD934X_HPH_NEW_INT_RDAC_VREF_CTL 0x0734 +#define WCD934X_HPH_NEW_INT_RDAC_OVERRIDE_CTL 0x0735 +#define WCD934X_HPH_NEW_INT_RDAC_MISC1 0x0736 +#define WCD934X_HPH_NEW_INT_RDAC_HD2_CTL_R 0x0736 +#define WCD934X_HPH_NEW_INT_PA_MISC1 0x0737 +#define WCD934X_HPH_NEW_INT_PA_MISC2 0x0738 +#define WCD934X_HPH_NEW_INT_PA_RDAC_MISC 0x0739 +#define WCD934X_HPH_NEW_INT_HPH_TIMER1 0x073a +#define WCD934X_HPH_NEW_INT_HPH_TIMER2 0x073b +#define WCD934X_HPH_NEW_INT_HPH_TIMER3 0x073c +#define WCD934X_HPH_NEW_INT_HPH_TIMER4 0x073d +#define WCD934X_HPH_NEW_INT_PA_RDAC_MISC2 0x073e +#define WCD934X_HPH_NEW_INT_PA_RDAC_MISC3 0x073f +#define WCD934X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI 0x0745 +#define WCD934X_RX_NEW_INT_HPH_RDAC_BIAS_ULP 0x0746 +#define WCD934X_RX_NEW_INT_HPH_RDAC_LDO_LP 0x0747 +#define WCD934X_SLNQ_INT_ANA_INT_LDO_TEST 0x074b +#define WCD934X_SLNQ_INT_ANA_INT_LDO_DEBUG_1 0x074c +#define WCD934X_SLNQ_INT_ANA_INT_LDO_DEBUG_2 0x074d +#define WCD934X_SLNQ_INT_ANA_INT_TX_LDO_TEST 0x074e +#define WCD934X_SLNQ_INT_ANA_INT_TX_DRV_TEST 0x074f +#define WCD934X_SLNQ_INT_ANA_INT_RX_TEST 0x0750 +#define WCD934X_SLNQ_INT_ANA_INT_RX_TEST_STATUS 0x0751 +#define WCD934X_SLNQ_INT_ANA_INT_RX_DEBUG_1 0x0752 +#define WCD934X_SLNQ_INT_ANA_INT_RX_DEBUG_2 0x0753 +#define WCD934X_SLNQ_INT_ANA_INT_CLK_CTRL 0x0754 +#define WCD934X_SLNQ_INT_ANA_INT_RESERVED_1 0x0755 +#define WCD934X_SLNQ_INT_ANA_INT_RESERVED_2 0x0756 +#define WCD934X_SLNQ_INT_ANA_INT_PLL_POST_DIV_REG0 0x0757 +#define WCD934X_SLNQ_INT_ANA_INT_PLL_POST_DIV_REG1 0x0758 +#define WCD934X_SLNQ_INT_ANA_INT_PLL_REF_DIV_REG0 0x0759 +#define WCD934X_SLNQ_INT_ANA_INT_PLL_REF_DIV_REG1 0x075a +#define WCD934X_SLNQ_INT_ANA_INT_PLL_FILTER_REG0 0x075b +#define WCD934X_SLNQ_INT_ANA_INT_PLL_FILTER_REG1 0x075c +#define WCD934X_SLNQ_INT_ANA_INT_PLL_L_VAL 0x075d +#define WCD934X_SLNQ_INT_ANA_INT_PLL_M_VAL 0x075e +#define WCD934X_SLNQ_INT_ANA_INT_PLL_N_VAL 0x075f +#define WCD934X_SLNQ_INT_ANA_INT_PLL_TEST_REG0 0x0760 +#define WCD934X_SLNQ_INT_ANA_INT_PLL_PFD_CP_DSM_PROG 0x0761 +#define WCD934X_SLNQ_INT_ANA_INT_PLL_VCO_PROG 0x0762 +#define WCD934X_SLNQ_INT_ANA_INT_PLL_TEST_REG1 0x0763 +#define WCD934X_SLNQ_INT_ANA_INT_PLL_LDO_LOCK_CFG 0x0764 +#define WCD934X_SLNQ_INT_ANA_INT_PLL_DIG_LOCK_DET_CFG 0x0765 +#define WCD934X_CLK_SYS_INT_POST_DIV_REG0 0x076c +#define WCD934X_CLK_SYS_INT_POST_DIV_REG1 0x076d +#define WCD934X_CLK_SYS_INT_REF_DIV_REG0 0x076e +#define WCD934X_CLK_SYS_INT_REF_DIV_REG1 0x076f +#define WCD934X_CLK_SYS_INT_FILTER_REG0 0x0770 +#define WCD934X_CLK_SYS_INT_FILTER_REG1 0x0771 +#define WCD934X_CLK_SYS_INT_PLL_L_VAL 0x0772 +#define WCD934X_CLK_SYS_INT_PLL_M_VAL 0x0773 +#define WCD934X_CLK_SYS_INT_PLL_N_VAL 0x0774 +#define WCD934X_CLK_SYS_INT_TEST_REG0 0x0775 +#define WCD934X_CLK_SYS_INT_PFD_CP_DSM_PROG 0x0776 +#define WCD934X_CLK_SYS_INT_VCO_PROG 0x0777 +#define WCD934X_CLK_SYS_INT_TEST_REG1 0x0778 +#define WCD934X_CLK_SYS_INT_LDO_LOCK_CFG 0x0779 +#define WCD934X_CLK_SYS_INT_DIG_LOCK_DET_CFG 0x077a +#define WCD934X_CLK_SYS_INT_CLK_TEST1 0x077b +#define WCD934X_CLK_SYS_INT_CLK_TEST2 0x077c +#define WCD934X_CLK_SYS_INT_CLK_TEST3 0x077d +#define WCD934X_CLK_SYS_INT_XO_TEST1 0x077e +#define WCD934X_CLK_SYS_INT_XO_TEST2 0x077f +#define WCD934X_BOOST_INT_VCOMP_HYST 0x0787 +#define WCD934X_BOOST_INT_VLOOP_FILTER 0x0788 +#define WCD934X_BOOST_INT_CTRL_IDELTA 0x0789 +#define WCD934X_BOOST_INT_CTRL_ILIM_STARTUP 0x078a +#define WCD934X_BOOST_INT_CTRL_MIN_ONTIME 0x078b +#define WCD934X_BOOST_INT_CTRL_MAX_ONTIME 0x078c +#define WCD934X_BOOST_INT_CTRL_TIMING 0x078d +#define WCD934X_BOOST_INT_TMUX_A_D 0x078e +#define WCD934X_BOOST_INT_SW_DRV_CNTL 0x078f +#define WCD934X_BOOST_INT_SPARE1 0x0790 +#define WCD934X_BOOST_INT_SPARE2 0x0791 +#define WCD934X_SIDO_NEW_INT_RAMP_STATUS 0x0796 +#define WCD934X_SIDO_NEW_INT_SPARE_1 0x0797 +#define WCD934X_SIDO_NEW_INT_DEBUG_VOUT_SETTING_A 0x0798 +#define WCD934X_SIDO_NEW_INT_DEBUG_VOUT_SETTING_D 0x0799 +#define WCD934X_SIDO_NEW_INT_RAMP_INC_WAIT 0x079a +#define WCD934X_SIDO_NEW_INT_DYNAMIC_IPEAK_CTL 0x079b +#define WCD934X_SIDO_NEW_INT_RAMP_IBLEED_CTL 0x079c +#define WCD934X_SIDO_NEW_INT_DEBUG_CPROVR_TEST 0x079d +#define WCD934X_SIDO_NEW_INT_RAMP_CTL_A 0x079e +#define WCD934X_SIDO_NEW_INT_RAMP_CTL_D 0x079f +#define WCD934X_SIDO_NEW_INT_RAMP_TIMEOUT_PERIOD 0x07a0 +#define WCD934X_SIDO_NEW_INT_DYNAMIC_IPEAK_SETTING1 0x07a1 +#define WCD934X_SIDO_NEW_INT_DYNAMIC_IPEAK_SETTING2 0x07a2 +#define WCD934X_SIDO_NEW_INT_DYNAMIC_IPEAK_SETTING3 0x07a3 +#define WCD934X_SIDO_NEW_INT_HIGH_ACCU_MODE_SEL1 0x07a4 +#define WCD934X_SIDO_NEW_INT_HIGH_ACCU_MODE_SEL2 0x07a5 +#define WCD934X_MBHC_NEW_INT_SLNQ_HPF 0x07af +#define WCD934X_MBHC_NEW_INT_SLNQ_REF 0x07b0 +#define WCD934X_MBHC_NEW_INT_SLNQ_COMP 0x07b1 +#define WCD934X_MBHC_NEW_INT_SPARE_2 0x07b2 +#define WCD934X_PAGE10_PAGE_REGISTER 0x0a00 +#define WCD934X_CDC_ANC0_CLK_RESET_CTL 0x0a01 +#define WCD934X_CDC_ANC0_MODE_1_CTL 0x0a02 +#define WCD934X_CDC_ANC0_MODE_2_CTL 0x0a03 +#define WCD934X_CDC_ANC0_FF_SHIFT 0x0a04 +#define WCD934X_CDC_ANC0_FB_SHIFT 0x0a05 +#define WCD934X_CDC_ANC0_LPF_FF_A_CTL 0x0a06 +#define WCD934X_CDC_ANC0_LPF_FF_B_CTL 0x0a07 +#define WCD934X_CDC_ANC0_LPF_FB_CTL 0x0a08 +#define WCD934X_CDC_ANC0_SMLPF_CTL 0x0a09 +#define WCD934X_CDC_ANC0_DCFLT_SHIFT_CTL 0x0a0a +#define WCD934X_CDC_ANC0_IIR_ADAPT_CTL 0x0a0b +#define WCD934X_CDC_ANC0_IIR_COEFF_1_CTL 0x0a0c +#define WCD934X_CDC_ANC0_IIR_COEFF_2_CTL 0x0a0d +#define WCD934X_CDC_ANC0_FF_A_GAIN_CTL 0x0a0e +#define WCD934X_CDC_ANC0_FF_B_GAIN_CTL 0x0a0f +#define WCD934X_CDC_ANC0_FB_GAIN_CTL 0x0a10 +#define WCD934X_CDC_ANC0_RC_COMMON_CTL 0x0a11 +#define WCD934X_CDC_ANC0_FIFO_COMMON_CTL 0x0a13 +#define WCD934X_CDC_ANC0_RC0_STATUS_FMIN_CNTR 0x0a14 +#define WCD934X_CDC_ANC0_RC1_STATUS_FMIN_CNTR 0x0a15 +#define WCD934X_CDC_ANC0_RC0_STATUS_FMAX_CNTR 0x0a16 +#define WCD934X_CDC_ANC0_RC1_STATUS_FMAX_CNTR 0x0a17 +#define WCD934X_CDC_ANC0_STATUS_FIFO 0x0a18 +#define WCD934X_CDC_ANC1_CLK_RESET_CTL 0x0a19 +#define WCD934X_CDC_ANC1_MODE_1_CTL 0x0a1a +#define WCD934X_CDC_ANC1_MODE_2_CTL 0x0a1b +#define WCD934X_CDC_ANC1_FF_SHIFT 0x0a1c +#define WCD934X_CDC_ANC1_FB_SHIFT 0x0a1d +#define WCD934X_CDC_ANC1_LPF_FF_A_CTL 0x0a1e +#define WCD934X_CDC_ANC1_LPF_FF_B_CTL 0x0a1f +#define WCD934X_CDC_ANC1_LPF_FB_CTL 0x0a20 +#define WCD934X_CDC_ANC1_SMLPF_CTL 0x0a21 +#define WCD934X_CDC_ANC1_DCFLT_SHIFT_CTL 0x0a22 +#define WCD934X_CDC_ANC1_IIR_ADAPT_CTL 0x0a23 +#define WCD934X_CDC_ANC1_IIR_COEFF_1_CTL 0x0a24 +#define WCD934X_CDC_ANC1_IIR_COEFF_2_CTL 0x0a25 +#define WCD934X_CDC_ANC1_FF_A_GAIN_CTL 0x0a26 +#define WCD934X_CDC_ANC1_FF_B_GAIN_CTL 0x0a27 +#define WCD934X_CDC_ANC1_FB_GAIN_CTL 0x0a28 +#define WCD934X_CDC_ANC1_RC_COMMON_CTL 0x0a29 +#define WCD934X_CDC_ANC1_FIFO_COMMON_CTL 0x0a2b +#define WCD934X_CDC_ANC1_RC0_STATUS_FMIN_CNTR 0x0a2c +#define WCD934X_CDC_ANC1_RC1_STATUS_FMIN_CNTR 0x0a2d +#define WCD934X_CDC_ANC1_RC0_STATUS_FMAX_CNTR 0x0a2e +#define WCD934X_CDC_ANC1_RC1_STATUS_FMAX_CNTR 0x0a2f +#define WCD934X_CDC_ANC1_STATUS_FIFO 0x0a30 +#define WCD934X_CDC_TX0_TX_PATH_CTL 0x0a31 +#define WCD934X_CDC_TX0_TX_PATH_CFG0 0x0a32 +#define WCD934X_CDC_TX0_TX_PATH_CFG1 0x0a33 +#define WCD934X_CDC_TX0_TX_VOL_CTL 0x0a34 +#define WCD934X_CDC_TX0_TX_PATH_192_CTL 0x0a35 +#define WCD934X_CDC_TX0_TX_PATH_192_CFG 0x0a36 +#define WCD934X_CDC_TX0_TX_PATH_SEC0 0x0a37 +#define WCD934X_CDC_TX0_TX_PATH_SEC1 0x0a38 +#define WCD934X_CDC_TX0_TX_PATH_SEC2 0x0a39 +#define WCD934X_CDC_TX0_TX_PATH_SEC3 0x0a3a +#define WCD934X_CDC_TX0_TX_PATH_SEC4 0x0a3b +#define WCD934X_CDC_TX0_TX_PATH_SEC5 0x0a3c +#define WCD934X_CDC_TX0_TX_PATH_SEC6 0x0a3d +#define WCD934X_CDC_TX0_TX_PATH_SEC7 0x0a3e +#define WCD934X_CDC_TX1_TX_PATH_CTL 0x0a41 +#define WCD934X_CDC_TX1_TX_PATH_CFG0 0x0a42 +#define WCD934X_CDC_TX1_TX_PATH_CFG1 0x0a43 +#define WCD934X_CDC_TX1_TX_VOL_CTL 0x0a44 +#define WCD934X_CDC_TX1_TX_PATH_192_CTL 0x0a45 +#define WCD934X_CDC_TX1_TX_PATH_192_CFG 0x0a46 +#define WCD934X_CDC_TX1_TX_PATH_SEC0 0x0a47 +#define WCD934X_CDC_TX1_TX_PATH_SEC1 0x0a48 +#define WCD934X_CDC_TX1_TX_PATH_SEC2 0x0a49 +#define WCD934X_CDC_TX1_TX_PATH_SEC3 0x0a4a +#define WCD934X_CDC_TX1_TX_PATH_SEC4 0x0a4b +#define WCD934X_CDC_TX1_TX_PATH_SEC5 0x0a4c +#define WCD934X_CDC_TX1_TX_PATH_SEC6 0x0a4d +#define WCD934X_CDC_TX2_TX_PATH_CTL 0x0a51 +#define WCD934X_CDC_TX2_TX_PATH_CFG0 0x0a52 +#define WCD934X_CDC_TX2_TX_PATH_CFG1 0x0a53 +#define WCD934X_CDC_TX2_TX_VOL_CTL 0x0a54 +#define WCD934X_CDC_TX2_TX_PATH_192_CTL 0x0a55 +#define WCD934X_CDC_TX2_TX_PATH_192_CFG 0x0a56 +#define WCD934X_CDC_TX2_TX_PATH_SEC0 0x0a57 +#define WCD934X_CDC_TX2_TX_PATH_SEC1 0x0a58 +#define WCD934X_CDC_TX2_TX_PATH_SEC2 0x0a59 +#define WCD934X_CDC_TX2_TX_PATH_SEC3 0x0a5a +#define WCD934X_CDC_TX2_TX_PATH_SEC4 0x0a5b +#define WCD934X_CDC_TX2_TX_PATH_SEC5 0x0a5c +#define WCD934X_CDC_TX2_TX_PATH_SEC6 0x0a5d +#define WCD934X_CDC_TX3_TX_PATH_CTL 0x0a61 +#define WCD934X_CDC_TX3_TX_PATH_CFG0 0x0a62 +#define WCD934X_CDC_TX3_TX_PATH_CFG1 0x0a63 +#define WCD934X_CDC_TX3_TX_VOL_CTL 0x0a64 +#define WCD934X_CDC_TX3_TX_PATH_192_CTL 0x0a65 +#define WCD934X_CDC_TX3_TX_PATH_192_CFG 0x0a66 +#define WCD934X_CDC_TX3_TX_PATH_SEC0 0x0a67 +#define WCD934X_CDC_TX3_TX_PATH_SEC1 0x0a68 +#define WCD934X_CDC_TX3_TX_PATH_SEC2 0x0a69 +#define WCD934X_CDC_TX3_TX_PATH_SEC3 0x0a6a +#define WCD934X_CDC_TX3_TX_PATH_SEC4 0x0a6b +#define WCD934X_CDC_TX3_TX_PATH_SEC5 0x0a6c +#define WCD934X_CDC_TX3_TX_PATH_SEC6 0x0a6d +#define WCD934X_CDC_TX4_TX_PATH_CTL 0x0a71 +#define WCD934X_CDC_TX4_TX_PATH_CFG0 0x0a72 +#define WCD934X_CDC_TX4_TX_PATH_CFG1 0x0a73 +#define WCD934X_CDC_TX4_TX_VOL_CTL 0x0a74 +#define WCD934X_CDC_TX4_TX_PATH_192_CTL 0x0a75 +#define WCD934X_CDC_TX4_TX_PATH_192_CFG 0x0a76 +#define WCD934X_CDC_TX4_TX_PATH_SEC0 0x0a77 +#define WCD934X_CDC_TX4_TX_PATH_SEC1 0x0a78 +#define WCD934X_CDC_TX4_TX_PATH_SEC2 0x0a79 +#define WCD934X_CDC_TX4_TX_PATH_SEC3 0x0a7a +#define WCD934X_CDC_TX4_TX_PATH_SEC4 0x0a7b +#define WCD934X_CDC_TX4_TX_PATH_SEC5 0x0a7c +#define WCD934X_CDC_TX4_TX_PATH_SEC6 0x0a7d +#define WCD934X_CDC_TX5_TX_PATH_CTL 0x0a81 +#define WCD934X_CDC_TX5_TX_PATH_CFG0 0x0a82 +#define WCD934X_CDC_TX5_TX_PATH_CFG1 0x0a83 +#define WCD934X_CDC_TX5_TX_VOL_CTL 0x0a84 +#define WCD934X_CDC_TX5_TX_PATH_192_CTL 0x0a85 +#define WCD934X_CDC_TX5_TX_PATH_192_CFG 0x0a86 +#define WCD934X_CDC_TX5_TX_PATH_SEC0 0x0a87 +#define WCD934X_CDC_TX5_TX_PATH_SEC1 0x0a88 +#define WCD934X_CDC_TX5_TX_PATH_SEC2 0x0a89 +#define WCD934X_CDC_TX5_TX_PATH_SEC3 0x0a8a +#define WCD934X_CDC_TX5_TX_PATH_SEC4 0x0a8b +#define WCD934X_CDC_TX5_TX_PATH_SEC5 0x0a8c +#define WCD934X_CDC_TX5_TX_PATH_SEC6 0x0a8d +#define WCD934X_CDC_TX6_TX_PATH_CTL 0x0a91 +#define WCD934X_CDC_TX6_TX_PATH_CFG0 0x0a92 +#define WCD934X_CDC_TX6_TX_PATH_CFG1 0x0a93 +#define WCD934X_CDC_TX6_TX_VOL_CTL 0x0a94 +#define WCD934X_CDC_TX6_TX_PATH_192_CTL 0x0a95 +#define WCD934X_CDC_TX6_TX_PATH_192_CFG 0x0a96 +#define WCD934X_CDC_TX6_TX_PATH_SEC0 0x0a97 +#define WCD934X_CDC_TX6_TX_PATH_SEC1 0x0a98 +#define WCD934X_CDC_TX6_TX_PATH_SEC2 0x0a99 +#define WCD934X_CDC_TX6_TX_PATH_SEC3 0x0a9a +#define WCD934X_CDC_TX6_TX_PATH_SEC4 0x0a9b +#define WCD934X_CDC_TX6_TX_PATH_SEC5 0x0a9c +#define WCD934X_CDC_TX6_TX_PATH_SEC6 0x0a9d +#define WCD934X_CDC_TX7_TX_PATH_CTL 0x0aa1 +#define WCD934X_CDC_TX7_TX_PATH_CFG0 0x0aa2 +#define WCD934X_CDC_TX7_TX_PATH_CFG1 0x0aa3 +#define WCD934X_CDC_TX7_TX_VOL_CTL 0x0aa4 +#define WCD934X_CDC_TX7_TX_PATH_192_CTL 0x0aa5 +#define WCD934X_CDC_TX7_TX_PATH_192_CFG 0x0aa6 +#define WCD934X_CDC_TX7_TX_PATH_SEC0 0x0aa7 +#define WCD934X_CDC_TX7_TX_PATH_SEC1 0x0aa8 +#define WCD934X_CDC_TX7_TX_PATH_SEC2 0x0aa9 +#define WCD934X_CDC_TX7_TX_PATH_SEC3 0x0aaa +#define WCD934X_CDC_TX7_TX_PATH_SEC4 0x0aab +#define WCD934X_CDC_TX7_TX_PATH_SEC5 0x0aac +#define WCD934X_CDC_TX7_TX_PATH_SEC6 0x0aad +#define WCD934X_CDC_TX8_TX_PATH_CTL 0x0ab1 +#define WCD934X_CDC_TX8_TX_PATH_CFG0 0x0ab2 +#define WCD934X_CDC_TX8_TX_PATH_CFG1 0x0ab3 +#define WCD934X_CDC_TX8_TX_VOL_CTL 0x0ab4 +#define WCD934X_CDC_TX8_TX_PATH_192_CTL 0x0ab5 +#define WCD934X_CDC_TX8_TX_PATH_192_CFG 0x0ab6 +#define WCD934X_CDC_TX8_TX_PATH_SEC0 0x0ab7 +#define WCD934X_CDC_TX8_TX_PATH_SEC1 0x0ab8 +#define WCD934X_CDC_TX8_TX_PATH_SEC2 0x0ab9 +#define WCD934X_CDC_TX8_TX_PATH_SEC3 0x0aba +#define WCD934X_CDC_TX8_TX_PATH_SEC4 0x0abb +#define WCD934X_CDC_TX8_TX_PATH_SEC5 0x0abc +#define WCD934X_CDC_TX8_TX_PATH_SEC6 0x0abd +#define WCD934X_CDC_TX9_SPKR_PROT_PATH_CTL 0x0ac2 +#define WCD934X_CDC_TX9_SPKR_PROT_PATH_CFG0 0x0ac3 +#define WCD934X_CDC_TX10_SPKR_PROT_PATH_CTL 0x0ac6 +#define WCD934X_CDC_TX10_SPKR_PROT_PATH_CFG0 0x0ac7 +#define WCD934X_CDC_TX11_SPKR_PROT_PATH_CTL 0x0aca +#define WCD934X_CDC_TX11_SPKR_PROT_PATH_CFG0 0x0acb +#define WCD934X_CDC_TX12_SPKR_PROT_PATH_CTL 0x0ace +#define WCD934X_CDC_TX12_SPKR_PROT_PATH_CFG0 0x0acf +#define WCD934X_PAGE11_PAGE_REGISTER 0x0b00 +#define WCD934X_CDC_COMPANDER1_CTL0 0x0b01 +#define WCD934X_CDC_COMPANDER1_CTL1 0x0b02 +#define WCD934X_CDC_COMPANDER1_CTL2 0x0b03 +#define WCD934X_CDC_COMPANDER1_CTL3 0x0b04 +#define WCD934X_CDC_COMPANDER1_CTL4 0x0b05 +#define WCD934X_CDC_COMPANDER1_CTL5 0x0b06 +#define WCD934X_CDC_COMPANDER1_CTL6 0x0b07 +#define WCD934X_CDC_COMPANDER1_CTL7 0x0b08 +#define WCD934X_CDC_COMPANDER2_CTL0 0x0b09 +#define WCD934X_CDC_COMPANDER2_CTL1 0x0b0a +#define WCD934X_CDC_COMPANDER2_CTL2 0x0b0b +#define WCD934X_CDC_COMPANDER2_CTL3 0x0b0c +#define WCD934X_CDC_COMPANDER2_CTL4 0x0b0d +#define WCD934X_CDC_COMPANDER2_CTL5 0x0b0e +#define WCD934X_CDC_COMPANDER2_CTL6 0x0b0f +#define WCD934X_CDC_COMPANDER2_CTL7 0x0b10 +#define WCD934X_CDC_COMPANDER3_CTL0 0x0b11 +#define WCD934X_CDC_COMPANDER3_CTL1 0x0b12 +#define WCD934X_CDC_COMPANDER3_CTL2 0x0b13 +#define WCD934X_CDC_COMPANDER3_CTL3 0x0b14 +#define WCD934X_CDC_COMPANDER3_CTL4 0x0b15 +#define WCD934X_CDC_COMPANDER3_CTL5 0x0b16 +#define WCD934X_CDC_COMPANDER3_CTL6 0x0b17 +#define WCD934X_CDC_COMPANDER3_CTL7 0x0b18 +#define WCD934X_CDC_COMPANDER4_CTL0 0x0b19 +#define WCD934X_CDC_COMPANDER4_CTL1 0x0b1a +#define WCD934X_CDC_COMPANDER4_CTL2 0x0b1b +#define WCD934X_CDC_COMPANDER4_CTL3 0x0b1c +#define WCD934X_CDC_COMPANDER4_CTL4 0x0b1d +#define WCD934X_CDC_COMPANDER4_CTL5 0x0b1e +#define WCD934X_CDC_COMPANDER4_CTL6 0x0b1f +#define WCD934X_CDC_COMPANDER4_CTL7 0x0b20 +#define WCD934X_CDC_COMPANDER7_CTL0 0x0b31 +#define WCD934X_CDC_COMPANDER7_CTL1 0x0b32 +#define WCD934X_CDC_COMPANDER7_CTL2 0x0b33 +#define WCD934X_CDC_COMPANDER7_CTL3 0x0b34 +#define WCD934X_CDC_COMPANDER7_CTL4 0x0b35 +#define WCD934X_CDC_COMPANDER7_CTL5 0x0b36 +#define WCD934X_CDC_COMPANDER7_CTL6 0x0b37 +#define WCD934X_CDC_COMPANDER7_CTL7 0x0b38 +#define WCD934X_CDC_COMPANDER8_CTL0 0x0b39 +#define WCD934X_CDC_COMPANDER8_CTL1 0x0b3a +#define WCD934X_CDC_COMPANDER8_CTL2 0x0b3b +#define WCD934X_CDC_COMPANDER8_CTL3 0x0b3c +#define WCD934X_CDC_COMPANDER8_CTL4 0x0b3d +#define WCD934X_CDC_COMPANDER8_CTL5 0x0b3e +#define WCD934X_CDC_COMPANDER8_CTL6 0x0b3f +#define WCD934X_CDC_COMPANDER8_CTL7 0x0b40 +#define WCD934X_CDC_RX0_RX_PATH_CTL 0x0b41 +#define WCD934X_CDC_RX0_RX_PATH_CFG0 0x0b42 +#define WCD934X_CDC_RX0_RX_PATH_CFG1 0x0b43 +#define WCD934X_CDC_RX0_RX_PATH_CFG2 0x0b44 +#define WCD934X_CDC_RX0_RX_VOL_CTL 0x0b45 +#define WCD934X_CDC_RX0_RX_PATH_MIX_CTL 0x0b46 +#define WCD934X_CDC_RX0_RX_PATH_MIX_CFG 0x0b47 +#define WCD934X_CDC_RX0_RX_VOL_MIX_CTL 0x0b48 +#define WCD934X_CDC_RX0_RX_PATH_SEC0 0x0b49 +#define WCD934X_CDC_RX0_RX_PATH_SEC1 0x0b4a +#define WCD934X_CDC_RX0_RX_PATH_SEC2 0x0b4b +#define WCD934X_CDC_RX0_RX_PATH_SEC3 0x0b4c +#define WCD934X_CDC_RX0_RX_PATH_SEC5 0x0b4e +#define WCD934X_CDC_RX0_RX_PATH_SEC6 0x0b4f +#define WCD934X_CDC_RX0_RX_PATH_SEC7 0x0b50 +#define WCD934X_CDC_RX0_RX_PATH_MIX_SEC0 0x0b51 +#define WCD934X_CDC_RX0_RX_PATH_MIX_SEC1 0x0b52 +#define WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL 0x0b53 +#define WCD934X_CDC_RX1_RX_PATH_CTL 0x0b55 +#define WCD934X_CDC_RX1_RX_PATH_CFG0 0x0b56 +#define WCD934X_CDC_RX1_RX_PATH_CFG1 0x0b57 +#define WCD934X_CDC_RX1_RX_PATH_CFG2 0x0b58 +#define WCD934X_CDC_RX1_RX_VOL_CTL 0x0b59 +#define WCD934X_CDC_RX1_RX_PATH_MIX_CTL 0x0b5a +#define WCD934X_CDC_RX1_RX_PATH_MIX_CFG 0x0b5b +#define WCD934X_CDC_RX1_RX_VOL_MIX_CTL 0x0b5c +#define WCD934X_CDC_RX1_RX_PATH_SEC0 0x0b5d +#define WCD934X_CDC_RX1_RX_PATH_SEC1 0x0b5e +#define WCD934X_CDC_RX1_RX_PATH_SEC2 0x0b5f +#define WCD934X_CDC_RX1_RX_PATH_SEC3 0x0b60 +#define WCD934X_CDC_RX1_RX_PATH_SEC4 0x0b61 +#define WCD934X_CDC_RX1_RX_PATH_SEC5 0x0b62 +#define WCD934X_CDC_RX1_RX_PATH_SEC6 0x0b63 +#define WCD934X_CDC_RX1_RX_PATH_SEC7 0x0b64 +#define WCD934X_CDC_RX1_RX_PATH_MIX_SEC0 0x0b65 +#define WCD934X_CDC_RX1_RX_PATH_MIX_SEC1 0x0b66 +#define WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL 0x0b67 +#define WCD934X_CDC_RX2_RX_PATH_CTL 0x0b69 +#define WCD934X_CDC_RX2_RX_PATH_CFG0 0x0b6a +#define WCD934X_CDC_RX2_RX_PATH_CFG1 0x0b6b +#define WCD934X_CDC_RX2_RX_PATH_CFG2 0x0b6c +#define WCD934X_CDC_RX2_RX_VOL_CTL 0x0b6d +#define WCD934X_CDC_RX2_RX_PATH_MIX_CTL 0x0b6e +#define WCD934X_CDC_RX2_RX_PATH_MIX_CFG 0x0b6f +#define WCD934X_CDC_RX2_RX_VOL_MIX_CTL 0x0b70 +#define WCD934X_CDC_RX2_RX_PATH_SEC0 0x0b71 +#define WCD934X_CDC_RX2_RX_PATH_SEC1 0x0b72 +#define WCD934X_CDC_RX2_RX_PATH_SEC2 0x0b73 +#define WCD934X_CDC_RX2_RX_PATH_SEC3 0x0b74 +#define WCD934X_CDC_RX2_RX_PATH_SEC4 0x0b75 +#define WCD934X_CDC_RX2_RX_PATH_SEC5 0x0b76 +#define WCD934X_CDC_RX2_RX_PATH_SEC6 0x0b77 +#define WCD934X_CDC_RX2_RX_PATH_SEC7 0x0b78 +#define WCD934X_CDC_RX2_RX_PATH_MIX_SEC0 0x0b79 +#define WCD934X_CDC_RX2_RX_PATH_MIX_SEC1 0x0b7a +#define WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL 0x0b7b +#define WCD934X_CDC_RX3_RX_PATH_CTL 0x0b7d +#define WCD934X_CDC_RX3_RX_PATH_CFG0 0x0b7e +#define WCD934X_CDC_RX3_RX_PATH_CFG1 0x0b7f +#define WCD934X_CDC_RX3_RX_PATH_CFG2 0x0b80 +#define WCD934X_CDC_RX3_RX_VOL_CTL 0x0b81 +#define WCD934X_CDC_RX3_RX_PATH_MIX_CTL 0x0b82 +#define WCD934X_CDC_RX3_RX_PATH_MIX_CFG 0x0b83 +#define WCD934X_CDC_RX3_RX_VOL_MIX_CTL 0x0b84 +#define WCD934X_CDC_RX3_RX_PATH_SEC0 0x0b85 +#define WCD934X_CDC_RX3_RX_PATH_SEC1 0x0b86 +#define WCD934X_CDC_RX3_RX_PATH_SEC2 0x0b87 +#define WCD934X_CDC_RX3_RX_PATH_SEC3 0x0b88 +#define WCD934X_CDC_RX3_RX_PATH_SEC5 0x0b8a +#define WCD934X_CDC_RX3_RX_PATH_SEC6 0x0b8b +#define WCD934X_CDC_RX3_RX_PATH_SEC7 0x0b8c +#define WCD934X_CDC_RX3_RX_PATH_MIX_SEC0 0x0b8d +#define WCD934X_CDC_RX3_RX_PATH_MIX_SEC1 0x0b8e +#define WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL 0x0b8f +#define WCD934X_CDC_RX4_RX_PATH_CTL 0x0b91 +#define WCD934X_CDC_RX4_RX_PATH_CFG0 0x0b92 +#define WCD934X_CDC_RX4_RX_PATH_CFG1 0x0b93 +#define WCD934X_CDC_RX4_RX_PATH_CFG2 0x0b94 +#define WCD934X_CDC_RX4_RX_VOL_CTL 0x0b95 +#define WCD934X_CDC_RX4_RX_PATH_MIX_CTL 0x0b96 +#define WCD934X_CDC_RX4_RX_PATH_MIX_CFG 0x0b97 +#define WCD934X_CDC_RX4_RX_VOL_MIX_CTL 0x0b98 +#define WCD934X_CDC_RX4_RX_PATH_SEC0 0x0b99 +#define WCD934X_CDC_RX4_RX_PATH_SEC1 0x0b9a +#define WCD934X_CDC_RX4_RX_PATH_SEC2 0x0b9b +#define WCD934X_CDC_RX4_RX_PATH_SEC3 0x0b9c +#define WCD934X_CDC_RX4_RX_PATH_SEC5 0x0b9e +#define WCD934X_CDC_RX4_RX_PATH_SEC6 0x0b9f +#define WCD934X_CDC_RX4_RX_PATH_SEC7 0x0ba0 +#define WCD934X_CDC_RX4_RX_PATH_MIX_SEC0 0x0ba1 +#define WCD934X_CDC_RX4_RX_PATH_MIX_SEC1 0x0ba2 +#define WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL 0x0ba3 +#define WCD934X_CDC_RX7_RX_PATH_CTL 0x0bcd +#define WCD934X_CDC_RX7_RX_PATH_CFG0 0x0bce +#define WCD934X_CDC_RX7_RX_PATH_CFG1 0x0bcf +#define WCD934X_CDC_RX7_RX_PATH_CFG2 0x0bd0 +#define WCD934X_CDC_RX7_RX_VOL_CTL 0x0bd1 +#define WCD934X_CDC_RX7_RX_PATH_MIX_CTL 0x0bd2 +#define WCD934X_CDC_RX7_RX_PATH_MIX_CFG 0x0bd3 +#define WCD934X_CDC_RX7_RX_VOL_MIX_CTL 0x0bd4 +#define WCD934X_CDC_RX7_RX_PATH_SEC0 0x0bd5 +#define WCD934X_CDC_RX7_RX_PATH_SEC1 0x0bd6 +#define WCD934X_CDC_RX7_RX_PATH_SEC2 0x0bd7 +#define WCD934X_CDC_RX7_RX_PATH_SEC3 0x0bd8 +#define WCD934X_CDC_RX7_RX_PATH_SEC5 0x0bda +#define WCD934X_CDC_RX7_RX_PATH_SEC6 0x0bdb +#define WCD934X_CDC_RX7_RX_PATH_SEC7 0x0bdc +#define WCD934X_CDC_RX7_RX_PATH_MIX_SEC0 0x0bdd +#define WCD934X_CDC_RX7_RX_PATH_MIX_SEC1 0x0bde +#define WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL 0x0bdf +#define WCD934X_CDC_RX8_RX_PATH_CTL 0x0be1 +#define WCD934X_CDC_RX8_RX_PATH_CFG0 0x0be2 +#define WCD934X_CDC_RX8_RX_PATH_CFG1 0x0be3 +#define WCD934X_CDC_RX8_RX_PATH_CFG2 0x0be4 +#define WCD934X_CDC_RX8_RX_VOL_CTL 0x0be5 +#define WCD934X_CDC_RX8_RX_PATH_MIX_CTL 0x0be6 +#define WCD934X_CDC_RX8_RX_PATH_MIX_CFG 0x0be7 +#define WCD934X_CDC_RX8_RX_VOL_MIX_CTL 0x0be8 +#define WCD934X_CDC_RX8_RX_PATH_SEC0 0x0be9 +#define WCD934X_CDC_RX8_RX_PATH_SEC1 0x0bea +#define WCD934X_CDC_RX8_RX_PATH_SEC2 0x0beb +#define WCD934X_CDC_RX8_RX_PATH_SEC3 0x0bec +#define WCD934X_CDC_RX8_RX_PATH_SEC5 0x0bee +#define WCD934X_CDC_RX8_RX_PATH_SEC6 0x0bef +#define WCD934X_CDC_RX8_RX_PATH_SEC7 0x0bf0 +#define WCD934X_CDC_RX8_RX_PATH_MIX_SEC0 0x0bf1 +#define WCD934X_CDC_RX8_RX_PATH_MIX_SEC1 0x0bf2 +#define WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL 0x0bf3 +#define WCD934X_PAGE12_PAGE_REGISTER 0x0c00 +#define WCD934X_CDC_CLSH_CRC 0x0c01 +#define WCD934X_CDC_CLSH_DLY_CTRL 0x0c02 +#define WCD934X_CDC_CLSH_DECAY_CTRL 0x0c03 +#define WCD934X_CDC_CLSH_HPH_V_PA 0x0c04 +#define WCD934X_CDC_CLSH_EAR_V_PA 0x0c05 +#define WCD934X_CDC_CLSH_HPH_V_HD 0x0c06 +#define WCD934X_CDC_CLSH_EAR_V_HD 0x0c07 +#define WCD934X_CDC_CLSH_K1_MSB 0x0c08 +#define WCD934X_CDC_CLSH_K1_LSB 0x0c09 +#define WCD934X_CDC_CLSH_K2_MSB 0x0c0a +#define WCD934X_CDC_CLSH_K2_LSB 0x0c0b +#define WCD934X_CDC_CLSH_IDLE_CTRL 0x0c0c +#define WCD934X_CDC_CLSH_IDLE_HPH 0x0c0d +#define WCD934X_CDC_CLSH_IDLE_EAR 0x0c0e +#define WCD934X_CDC_CLSH_TEST0 0x0c0f +#define WCD934X_CDC_CLSH_TEST1 0x0c10 +#define WCD934X_CDC_CLSH_OVR_VREF 0x0c11 +#define WCD934X_CDC_BOOST0_BOOST_PATH_CTL 0x0c19 +#define WCD934X_CDC_BOOST0_BOOST_CTL 0x0c1a +#define WCD934X_CDC_BOOST0_BOOST_CFG1 0x0c1b +#define WCD934X_CDC_BOOST0_BOOST_CFG2 0x0c1c +#define WCD934X_CDC_BOOST1_BOOST_PATH_CTL 0x0c21 +#define WCD934X_CDC_BOOST1_BOOST_CTL 0x0c22 +#define WCD934X_CDC_BOOST1_BOOST_CFG1 0x0c23 +#define WCD934X_CDC_BOOST1_BOOST_CFG2 0x0c24 +#define WCD934X_CDC_VBAT_VBAT_PATH_CTL 0x0c3d +#define WCD934X_CDC_VBAT_VBAT_CFG 0x0c3e +#define WCD934X_CDC_VBAT_VBAT_ADC_CAL1 0x0c3f +#define WCD934X_CDC_VBAT_VBAT_ADC_CAL2 0x0c40 +#define WCD934X_CDC_VBAT_VBAT_ADC_CAL3 0x0c41 +#define WCD934X_CDC_VBAT_VBAT_PK_EST1 0x0c42 +#define WCD934X_CDC_VBAT_VBAT_PK_EST2 0x0c43 +#define WCD934X_CDC_VBAT_VBAT_PK_EST3 0x0c44 +#define WCD934X_CDC_VBAT_VBAT_RF_PROC1 0x0c45 +#define WCD934X_CDC_VBAT_VBAT_RF_PROC2 0x0c46 +#define WCD934X_CDC_VBAT_VBAT_TAC1 0x0c47 +#define WCD934X_CDC_VBAT_VBAT_TAC2 0x0c48 +#define WCD934X_CDC_VBAT_VBAT_TAC3 0x0c49 +#define WCD934X_CDC_VBAT_VBAT_TAC4 0x0c4a +#define WCD934X_CDC_VBAT_VBAT_GAIN_UPD1 0x0c4b +#define WCD934X_CDC_VBAT_VBAT_GAIN_UPD2 0x0c4c +#define WCD934X_CDC_VBAT_VBAT_GAIN_UPD3 0x0c4d +#define WCD934X_CDC_VBAT_VBAT_GAIN_UPD4 0x0c4e +#define WCD934X_CDC_VBAT_VBAT_DEBUG1 0x0c4f +#define WCD934X_CDC_VBAT_VBAT_GAIN_UPD_MON 0x0c50 +#define WCD934X_CDC_VBAT_VBAT_GAIN_MON_VAL 0x0c51 +#define WCD934X_CDC_VBAT_VBAT_BAN 0x0c52 +#define WCD934X_MIXING_ASRC0_CLK_RST_CTL 0x0c55 +#define WCD934X_MIXING_ASRC0_CTL0 0x0c56 +#define WCD934X_MIXING_ASRC0_CTL1 0x0c57 +#define WCD934X_MIXING_ASRC0_FIFO_CTL 0x0c58 +#define WCD934X_MIXING_ASRC0_STATUS_FMIN_CNTR_LSB 0x0c59 +#define WCD934X_MIXING_ASRC0_STATUS_FMIN_CNTR_MSB 0x0c5a +#define WCD934X_MIXING_ASRC0_STATUS_FMAX_CNTR_LSB 0x0c5b +#define WCD934X_MIXING_ASRC0_STATUS_FMAX_CNTR_MSB 0x0c5c +#define WCD934X_MIXING_ASRC0_STATUS_FIFO 0x0c5d +#define WCD934X_MIXING_ASRC1_CLK_RST_CTL 0x0c61 +#define WCD934X_MIXING_ASRC1_CTL0 0x0c62 +#define WCD934X_MIXING_ASRC1_CTL1 0x0c63 +#define WCD934X_MIXING_ASRC1_FIFO_CTL 0x0c64 +#define WCD934X_MIXING_ASRC1_STATUS_FMIN_CNTR_LSB 0x0c65 +#define WCD934X_MIXING_ASRC1_STATUS_FMIN_CNTR_MSB 0x0c66 +#define WCD934X_MIXING_ASRC1_STATUS_FMAX_CNTR_LSB 0x0c67 +#define WCD934X_MIXING_ASRC1_STATUS_FMAX_CNTR_MSB 0x0c68 +#define WCD934X_MIXING_ASRC1_STATUS_FIFO 0x0c69 +#define WCD934X_MIXING_ASRC2_CLK_RST_CTL 0x0c6d +#define WCD934X_MIXING_ASRC2_CTL0 0x0c6e +#define WCD934X_MIXING_ASRC2_CTL1 0x0c6f +#define WCD934X_MIXING_ASRC2_FIFO_CTL 0x0c70 +#define WCD934X_MIXING_ASRC2_STATUS_FMIN_CNTR_LSB 0x0c71 +#define WCD934X_MIXING_ASRC2_STATUS_FMIN_CNTR_MSB 0x0c72 +#define WCD934X_MIXING_ASRC2_STATUS_FMAX_CNTR_LSB 0x0c73 +#define WCD934X_MIXING_ASRC2_STATUS_FMAX_CNTR_MSB 0x0c74 +#define WCD934X_MIXING_ASRC2_STATUS_FIFO 0x0c75 +#define WCD934X_MIXING_ASRC3_CLK_RST_CTL 0x0c79 +#define WCD934X_MIXING_ASRC3_CTL0 0x0c7a +#define WCD934X_MIXING_ASRC3_CTL1 0x0c7b +#define WCD934X_MIXING_ASRC3_FIFO_CTL 0x0c7c +#define WCD934X_MIXING_ASRC3_STATUS_FMIN_CNTR_LSB 0x0c7d +#define WCD934X_MIXING_ASRC3_STATUS_FMIN_CNTR_MSB 0x0c7e +#define WCD934X_MIXING_ASRC3_STATUS_FMAX_CNTR_LSB 0x0c7f +#define WCD934X_MIXING_ASRC3_STATUS_FMAX_CNTR_MSB 0x0c80 +#define WCD934X_MIXING_ASRC3_STATUS_FIFO 0x0c81 +#define WCD934X_SWR_AHB_BRIDGE_WR_DATA_0 0x0c85 +#define WCD934X_SWR_AHB_BRIDGE_WR_DATA_1 0x0c86 +#define WCD934X_SWR_AHB_BRIDGE_WR_DATA_2 0x0c87 +#define WCD934X_SWR_AHB_BRIDGE_WR_DATA_3 0x0c88 +#define WCD934X_SWR_AHB_BRIDGE_WR_ADDR_0 0x0c89 +#define WCD934X_SWR_AHB_BRIDGE_WR_ADDR_1 0x0c8a +#define WCD934X_SWR_AHB_BRIDGE_WR_ADDR_2 0x0c8b +#define WCD934X_SWR_AHB_BRIDGE_WR_ADDR_3 0x0c8c +#define WCD934X_SWR_AHB_BRIDGE_RD_ADDR_0 0x0c8d +#define WCD934X_SWR_AHB_BRIDGE_RD_ADDR_1 0x0c8e +#define WCD934X_SWR_AHB_BRIDGE_RD_ADDR_2 0x0c8f +#define WCD934X_SWR_AHB_BRIDGE_RD_ADDR_3 0x0c90 +#define WCD934X_SWR_AHB_BRIDGE_RD_DATA_0 0x0c91 +#define WCD934X_SWR_AHB_BRIDGE_RD_DATA_1 0x0c92 +#define WCD934X_SWR_AHB_BRIDGE_RD_DATA_2 0x0c93 +#define WCD934X_SWR_AHB_BRIDGE_RD_DATA_3 0x0c94 +#define WCD934X_SWR_AHB_BRIDGE_ACCESS_CFG 0x0c95 +#define WCD934X_SWR_AHB_BRIDGE_ACCESS_STATUS 0x0c96 +#define WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL 0x0cb5 +#define WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CFG1 0x0cb6 +#define WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL 0x0cb9 +#define WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CFG1 0x0cba +#define WCD934X_SIDETONE_ASRC0_CLK_RST_CTL 0x0cbd +#define WCD934X_SIDETONE_ASRC0_CTL0 0x0cbe +#define WCD934X_SIDETONE_ASRC0_CTL1 0x0cbf +#define WCD934X_SIDETONE_ASRC0_FIFO_CTL 0x0cc0 +#define WCD934X_SIDETONE_ASRC0_STATUS_FMIN_CNTR_LSB 0x0cc1 +#define WCD934X_SIDETONE_ASRC0_STATUS_FMIN_CNTR_MSB 0x0cc2 +#define WCD934X_SIDETONE_ASRC0_STATUS_FMAX_CNTR_LSB 0x0cc3 +#define WCD934X_SIDETONE_ASRC0_STATUS_FMAX_CNTR_MSB 0x0cc4 +#define WCD934X_SIDETONE_ASRC0_STATUS_FIFO 0x0cc5 +#define WCD934X_SIDETONE_ASRC1_CLK_RST_CTL 0x0cc9 +#define WCD934X_SIDETONE_ASRC1_CTL0 0x0cca +#define WCD934X_SIDETONE_ASRC1_CTL1 0x0ccb +#define WCD934X_SIDETONE_ASRC1_FIFO_CTL 0x0ccc +#define WCD934X_SIDETONE_ASRC1_STATUS_FMIN_CNTR_LSB 0x0ccd +#define WCD934X_SIDETONE_ASRC1_STATUS_FMIN_CNTR_MSB 0x0cce +#define WCD934X_SIDETONE_ASRC1_STATUS_FMAX_CNTR_LSB 0x0ccf +#define WCD934X_SIDETONE_ASRC1_STATUS_FMAX_CNTR_MSB 0x0cd0 +#define WCD934X_SIDETONE_ASRC1_STATUS_FIFO 0x0cd1 +#define WCD934X_EC_REF_HQ0_EC_REF_HQ_PATH_CTL 0x0cd5 +#define WCD934X_EC_REF_HQ0_EC_REF_HQ_CFG0 0x0cd6 +#define WCD934X_EC_REF_HQ1_EC_REF_HQ_PATH_CTL 0x0cdd +#define WCD934X_EC_REF_HQ1_EC_REF_HQ_CFG0 0x0cde +#define WCD934X_EC_ASRC0_CLK_RST_CTL 0x0ce5 +#define WCD934X_EC_ASRC0_CTL0 0x0ce6 +#define WCD934X_EC_ASRC0_CTL1 0x0ce7 +#define WCD934X_EC_ASRC0_FIFO_CTL 0x0ce8 +#define WCD934X_EC_ASRC0_STATUS_FMIN_CNTR_LSB 0x0ce9 +#define WCD934X_EC_ASRC0_STATUS_FMIN_CNTR_MSB 0x0cea +#define WCD934X_EC_ASRC0_STATUS_FMAX_CNTR_LSB 0x0ceb +#define WCD934X_EC_ASRC0_STATUS_FMAX_CNTR_MSB 0x0cec +#define WCD934X_EC_ASRC0_STATUS_FIFO 0x0ced +#define WCD934X_EC_ASRC1_CLK_RST_CTL 0x0cf1 +#define WCD934X_EC_ASRC1_CTL0 0x0cf2 +#define WCD934X_EC_ASRC1_CTL1 0x0cf3 +#define WCD934X_EC_ASRC1_FIFO_CTL 0x0cf4 +#define WCD934X_EC_ASRC1_STATUS_FMIN_CNTR_LSB 0x0cf5 +#define WCD934X_EC_ASRC1_STATUS_FMIN_CNTR_MSB 0x0cf6 +#define WCD934X_EC_ASRC1_STATUS_FMAX_CNTR_LSB 0x0cf7 +#define WCD934X_EC_ASRC1_STATUS_FMAX_CNTR_MSB 0x0cf8 +#define WCD934X_EC_ASRC1_STATUS_FIFO 0x0cf9 +#define WCD934X_PAGE13_PAGE_REGISTER 0x0d00 +#define WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0 0x0d01 +#define WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1 0x0d02 +#define WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0 0x0d03 +#define WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1 0x0d04 +#define WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0 0x0d05 +#define WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1 0x0d06 +#define WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0 0x0d07 +#define WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1 0x0d08 +#define WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0 0x0d09 +#define WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1 0x0d0a +#define WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0 0x0d0f +#define WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1 0x0d10 +#define WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0 0x0d11 +#define WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1 0x0d12 +#define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG0 0x0d13 +#define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG1 0x0d14 +#define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG2 0x0d15 +#define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG3 0x0d16 +#define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG4 0x0d17 +#define WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 0x0d18 +#define WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1 0x0d19 +#define WCD934X_CDC_RX_INP_MUX_ANC_CFG0 0x0d1a +#define WCD934X_CDC_RX_INP_MUX_SPLINE_ASRC_CFG0 0x0d1b +#define WCD934X_CDC_RX_INP_MUX_EC_REF_HQ_CFG0 0x0d1c +#define WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 0x0d1d +#define WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 0x0d1e +#define WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0 0x0d1f +#define WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1 0x0d20 +#define WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0 0x0d21 +#define WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1 0x0d22 +#define WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0 0x0d23 +#define WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1 0x0d25 +#define WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 0x0d26 +#define WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0 0x0d27 +#define WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0 0x0d28 +#define WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0 0x0d29 +#define WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0 0x0d2a +#define WCD934X_CDC_TX_INP_MUX_ADC_MUX10_CFG0 0x0d2b +#define WCD934X_CDC_TX_INP_MUX_ADC_MUX11_CFG0 0x0d2c +#define WCD934X_CDC_TX_INP_MUX_ADC_MUX12_CFG0 0x0d2d +#define WCD934X_CDC_TX_INP_MUX_ADC_MUX13_CFG0 0x0d2e +#define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0 0x0d31 +#define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1 0x0d32 +#define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2 0x0d33 +#define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3 0x0d34 +#define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0 0x0d35 +#define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1 0x0d36 +#define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2 0x0d37 +#define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3 0x0d38 +#define WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0 0x0d3a +#define WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1 0x0d3b +#define WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2 0x0d3c +#define WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3 0x0d3d +#define WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL 0x0d41 +#define WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL 0x0d42 +#define WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL 0x0d43 +#define WCD934X_CDC_CLK_RST_CTRL_DSD_CONTROL 0x0d44 +#define WCD934X_CDC_CLK_RST_CTRL_ASRC_SHARE_CONTROL 0x0d45 +#define WCD934X_CDC_CLK_RST_CTRL_GFM_CONTROL 0x0d46 +#define WCD934X_CDC_PROX_DETECT_PROX_CTL 0x0d49 +#define WCD934X_CDC_PROX_DETECT_PROX_POLL_PERIOD0 0x0d4a +#define WCD934X_CDC_PROX_DETECT_PROX_POLL_PERIOD1 0x0d4b +#define WCD934X_CDC_PROX_DETECT_PROX_SIG_PATTERN_LSB 0x0d4c +#define WCD934X_CDC_PROX_DETECT_PROX_SIG_PATTERN_MSB 0x0d4d +#define WCD934X_CDC_PROX_DETECT_PROX_STATUS 0x0d4e +#define WCD934X_CDC_PROX_DETECT_PROX_TEST_CTRL 0x0d4f +#define WCD934X_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB 0x0d50 +#define WCD934X_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB 0x0d51 +#define WCD934X_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB_RD 0x0d52 +#define WCD934X_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB_RD 0x0d53 +#define WCD934X_CDC_PROX_DETECT_PROX_CTL_REPEAT_PAT 0x0d54 +#define WCD934X_CDC_SIDETONE_IIR0_IIR_PATH_CTL 0x0d55 +#define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL 0x0d56 +#define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL 0x0d57 +#define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL 0x0d58 +#define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL 0x0d59 +#define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B5_CTL 0x0d5a +#define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B6_CTL 0x0d5b +#define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B7_CTL 0x0d5c +#define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B8_CTL 0x0d5d +#define WCD934X_CDC_SIDETONE_IIR0_IIR_CTL 0x0d5e +#define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL 0x0d5f +#define WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL 0x0d60 +#define WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL 0x0d61 +#define WCD934X_CDC_SIDETONE_IIR1_IIR_PATH_CTL 0x0d65 +#define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL 0x0d66 +#define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL 0x0d67 +#define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL 0x0d68 +#define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL 0x0d69 +#define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B5_CTL 0x0d6a +#define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B6_CTL 0x0d6b +#define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B7_CTL 0x0d6c +#define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B8_CTL 0x0d6d +#define WCD934X_CDC_SIDETONE_IIR1_IIR_CTL 0x0d6e +#define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL 0x0d6f +#define WCD934X_CDC_SIDETONE_IIR1_IIR_COEF_B1_CTL 0x0d70 +#define WCD934X_CDC_SIDETONE_IIR1_IIR_COEF_B2_CTL 0x0d71 +#define WCD934X_CDC_TOP_TOP_CFG0 0x0d81 +#define WCD934X_CDC_TOP_TOP_CFG1 0x0d82 +#define WCD934X_CDC_TOP_TOP_CFG7 0x0d88 +#define WCD934X_CDC_TOP_HPHL_COMP_WR_LSB 0x0d89 +#define WCD934X_CDC_TOP_HPHL_COMP_WR_MSB 0x0d8a +#define WCD934X_CDC_TOP_HPHL_COMP_LUT 0x0d8b +#define WCD934X_CDC_TOP_HPHL_COMP_RD_LSB 0x0d8c +#define WCD934X_CDC_TOP_HPHL_COMP_RD_MSB 0x0d8d +#define WCD934X_CDC_TOP_HPHR_COMP_WR_LSB 0x0d8e +#define WCD934X_CDC_TOP_HPHR_COMP_WR_MSB 0x0d8f +#define WCD934X_CDC_TOP_HPHR_COMP_LUT 0x0d90 +#define WCD934X_CDC_TOP_HPHR_COMP_RD_LSB 0x0d91 +#define WCD934X_CDC_TOP_HPHR_COMP_RD_MSB 0x0d92 +#define WCD934X_CDC_TOP_DIFFL_COMP_WR_LSB 0x0d93 +#define WCD934X_CDC_TOP_DIFFL_COMP_WR_MSB 0x0d94 +#define WCD934X_CDC_TOP_DIFFL_COMP_LUT 0x0d95 +#define WCD934X_CDC_TOP_DIFFL_COMP_RD_LSB 0x0d96 +#define WCD934X_CDC_TOP_DIFFL_COMP_RD_MSB 0x0d97 +#define WCD934X_CDC_TOP_DIFFR_COMP_WR_LSB 0x0d98 +#define WCD934X_CDC_TOP_DIFFR_COMP_WR_MSB 0x0d99 +#define WCD934X_CDC_TOP_DIFFR_COMP_LUT 0x0d9a +#define WCD934X_CDC_TOP_DIFFR_COMP_RD_LSB 0x0d9b +#define WCD934X_CDC_TOP_DIFFR_COMP_RD_MSB 0x0d9c +#define WCD934X_CDC_DSD0_PATH_CTL 0x0db1 +#define WCD934X_CDC_DSD0_CFG0 0x0db2 +#define WCD934X_CDC_DSD0_CFG1 0x0db3 +#define WCD934X_CDC_DSD0_CFG2 0x0db4 +#define WCD934X_CDC_DSD0_CFG3 0x0db5 +#define WCD934X_CDC_DSD0_CFG4 0x0db6 +#define WCD934X_CDC_DSD0_CFG5 0x0db7 +#define WCD934X_CDC_DSD1_PATH_CTL 0x0dc1 +#define WCD934X_CDC_DSD1_CFG0 0x0dc2 +#define WCD934X_CDC_DSD1_CFG1 0x0dc3 +#define WCD934X_CDC_DSD1_CFG2 0x0dc4 +#define WCD934X_CDC_DSD1_CFG3 0x0dc5 +#define WCD934X_CDC_DSD1_CFG4 0x0dc6 +#define WCD934X_CDC_DSD1_CFG5 0x0dc7 +#define WCD934X_CDC_RX_IDLE_DET_PATH_CTL 0x0dd1 +#define WCD934X_CDC_RX_IDLE_DET_CFG0 0x0dd2 +#define WCD934X_CDC_RX_IDLE_DET_CFG1 0x0dd3 +#define WCD934X_CDC_RX_IDLE_DET_CFG2 0x0dd4 +#define WCD934X_CDC_RX_IDLE_DET_CFG3 0x0dd5 +#define WCD934X_PAGE14_PAGE_REGISTER 0x0e00 +#define WCD934X_CDC_RATE_EST0_RE_CLK_RST_CTL 0x0e01 +#define WCD934X_CDC_RATE_EST0_RE_CTL 0x0e02 +#define WCD934X_CDC_RATE_EST0_RE_PULSE_SUPR_CTL 0x0e03 +#define WCD934X_CDC_RATE_EST0_RE_TIMER 0x0e04 +#define WCD934X_CDC_RATE_EST0_RE_BW_SW 0x0e05 +#define WCD934X_CDC_RATE_EST0_RE_THRESH 0x0e06 +#define WCD934X_CDC_RATE_EST0_RE_STATUS 0x0e07 +#define WCD934X_CDC_RATE_EST0_RE_DIAG_CTRL 0x0e09 +#define WCD934X_CDC_RATE_EST0_RE_DIAG_TIMER2 0x0e0c +#define WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW1 0x0e0d +#define WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW2 0x0e0e +#define WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW3 0x0e0f +#define WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW4 0x0e10 +#define WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW5 0x0e11 +#define WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW1 0x0e12 +#define WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW2 0x0e13 +#define WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW3 0x0e14 +#define WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW4 0x0e15 +#define WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW5 0x0e16 +#define WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW1 0x0e17 +#define WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW2 0x0e18 +#define WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW3 0x0e19 +#define WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW4 0x0e1a +#define WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW5 0x0e1b +#define WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW1 0x0e1c +#define WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW2 0x0e1d +#define WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW3 0x0e1e +#define WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW4 0x0e1f +#define WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW5 0x0e20 +#define WCD934X_CDC_RATE_EST0_RE_RMAX_DIAG 0x0e21 +#define WCD934X_CDC_RATE_EST0_RE_RMIN_DIAG 0x0e22 +#define WCD934X_CDC_RATE_EST0_RE_PH_DET 0x0e23 +#define WCD934X_CDC_RATE_EST0_RE_DIAG_CLR 0x0e24 +#define WCD934X_CDC_RATE_EST0_RE_MB_SW_STATE 0x0e25 +#define WCD934X_CDC_RATE_EST0_RE_MAST_DIAG_STATE 0x0e26 +#define WCD934X_CDC_RATE_EST0_RE_RATE_OUT_7_0 0x0e27 +#define WCD934X_CDC_RATE_EST0_RE_RATE_OUT_15_8 0x0e28 +#define WCD934X_CDC_RATE_EST0_RE_RATE_OUT_23_16 0x0e29 +#define WCD934X_CDC_RATE_EST0_RE_RATE_OUT_31_24 0x0e2a +#define WCD934X_CDC_RATE_EST0_RE_RATE_OUT_39_32 0x0e2b +#define WCD934X_CDC_RATE_EST0_RE_RATE_OUT_40_43 0x0e2c +#define WCD934X_CDC_RATE_EST1_RE_CLK_RST_CTL 0x0e31 +#define WCD934X_CDC_RATE_EST1_RE_CTL 0x0e32 +#define WCD934X_CDC_RATE_EST1_RE_PULSE_SUPR_CTL 0x0e33 +#define WCD934X_CDC_RATE_EST1_RE_TIMER 0x0e34 +#define WCD934X_CDC_RATE_EST1_RE_BW_SW 0x0e35 +#define WCD934X_CDC_RATE_EST1_RE_THRESH 0x0e36 +#define WCD934X_CDC_RATE_EST1_RE_STATUS 0x0e37 +#define WCD934X_CDC_RATE_EST1_RE_DIAG_CTRL 0x0e39 +#define WCD934X_CDC_RATE_EST1_RE_DIAG_TIMER2 0x0e3c +#define WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW1 0x0e3d +#define WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW2 0x0e3e +#define WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW3 0x0e3f +#define WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW4 0x0e40 +#define WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW5 0x0e41 +#define WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW1 0x0e42 +#define WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW2 0x0e43 +#define WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW3 0x0e44 +#define WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW4 0x0e45 +#define WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW5 0x0e46 +#define WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW1 0x0e47 +#define WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW2 0x0e48 +#define WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW3 0x0e49 +#define WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW4 0x0e4a +#define WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW5 0x0e4b +#define WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW1 0x0e4c +#define WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW2 0x0e4d +#define WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW3 0x0e4e +#define WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW4 0x0e4f +#define WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW5 0x0e50 +#define WCD934X_CDC_RATE_EST1_RE_RMAX_DIAG 0x0e51 +#define WCD934X_CDC_RATE_EST1_RE_RMIN_DIAG 0x0e52 +#define WCD934X_CDC_RATE_EST1_RE_PH_DET 0x0e53 +#define WCD934X_CDC_RATE_EST1_RE_DIAG_CLR 0x0e54 +#define WCD934X_CDC_RATE_EST1_RE_MB_SW_STATE 0x0e55 +#define WCD934X_CDC_RATE_EST1_RE_MAST_DIAG_STATE 0x0e56 +#define WCD934X_CDC_RATE_EST1_RE_RATE_OUT_7_0 0x0e57 +#define WCD934X_CDC_RATE_EST1_RE_RATE_OUT_15_8 0x0e58 +#define WCD934X_CDC_RATE_EST1_RE_RATE_OUT_23_16 0x0e59 +#define WCD934X_CDC_RATE_EST1_RE_RATE_OUT_31_24 0x0e5a +#define WCD934X_CDC_RATE_EST1_RE_RATE_OUT_39_32 0x0e5b +#define WCD934X_CDC_RATE_EST1_RE_RATE_OUT_40_43 0x0e5c +#define WCD934X_CDC_RATE_EST2_RE_CLK_RST_CTL 0x0e61 +#define WCD934X_CDC_RATE_EST2_RE_CTL 0x0e62 +#define WCD934X_CDC_RATE_EST2_RE_PULSE_SUPR_CTL 0x0e63 +#define WCD934X_CDC_RATE_EST2_RE_TIMER 0x0e64 +#define WCD934X_CDC_RATE_EST2_RE_BW_SW 0x0e65 +#define WCD934X_CDC_RATE_EST2_RE_THRESH 0x0e66 +#define WCD934X_CDC_RATE_EST2_RE_STATUS 0x0e67 +#define WCD934X_CDC_RATE_EST2_RE_DIAG_CTRL 0x0e69 +#define WCD934X_CDC_RATE_EST2_RE_DIAG_TIMER2 0x0e6c +#define WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW1 0x0e6d +#define WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW2 0x0e6e +#define WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW3 0x0e6f +#define WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW4 0x0e70 +#define WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW5 0x0e71 +#define WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW1 0x0e72 +#define WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW2 0x0e73 +#define WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW3 0x0e74 +#define WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW4 0x0e75 +#define WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW5 0x0e76 +#define WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW1 0x0e77 +#define WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW2 0x0e78 +#define WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW3 0x0e79 +#define WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW4 0x0e7a +#define WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW5 0x0e7b +#define WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW1 0x0e7c +#define WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW2 0x0e7d +#define WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW3 0x0e7e +#define WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW4 0x0e7f +#define WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW5 0x0e80 +#define WCD934X_CDC_RATE_EST2_RE_RMAX_DIAG 0x0e81 +#define WCD934X_CDC_RATE_EST2_RE_RMIN_DIAG 0x0e82 +#define WCD934X_CDC_RATE_EST2_RE_PH_DET 0x0e83 +#define WCD934X_CDC_RATE_EST2_RE_DIAG_CLR 0x0e84 +#define WCD934X_CDC_RATE_EST2_RE_MB_SW_STATE 0x0e85 +#define WCD934X_CDC_RATE_EST2_RE_MAST_DIAG_STATE 0x0e86 +#define WCD934X_CDC_RATE_EST2_RE_RATE_OUT_7_0 0x0e87 +#define WCD934X_CDC_RATE_EST2_RE_RATE_OUT_15_8 0x0e88 +#define WCD934X_CDC_RATE_EST2_RE_RATE_OUT_23_16 0x0e89 +#define WCD934X_CDC_RATE_EST2_RE_RATE_OUT_31_24 0x0e8a +#define WCD934X_CDC_RATE_EST2_RE_RATE_OUT_39_32 0x0e8b +#define WCD934X_CDC_RATE_EST2_RE_RATE_OUT_40_43 0x0e8c +#define WCD934X_CDC_RATE_EST3_RE_CLK_RST_CTL 0x0e91 +#define WCD934X_CDC_RATE_EST3_RE_CTL 0x0e92 +#define WCD934X_CDC_RATE_EST3_RE_PULSE_SUPR_CTL 0x0e93 +#define WCD934X_CDC_RATE_EST3_RE_TIMER 0x0e94 +#define WCD934X_CDC_RATE_EST3_RE_BW_SW 0x0e95 +#define WCD934X_CDC_RATE_EST3_RE_THRESH 0x0e96 +#define WCD934X_CDC_RATE_EST3_RE_STATUS 0x0e97 +#define WCD934X_CDC_RATE_EST3_RE_DIAG_CTRL 0x0e99 +#define WCD934X_CDC_RATE_EST3_RE_DIAG_TIMER2 0x0e9c +#define WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW1 0x0e9d +#define WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW2 0x0e9e +#define WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW3 0x0e9f +#define WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW4 0x0ea0 +#define WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW5 0x0ea1 +#define WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW1 0x0ea2 +#define WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW2 0x0ea3 +#define WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW3 0x0ea4 +#define WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW4 0x0ea5 +#define WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW5 0x0ea6 +#define WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW1 0x0ea7 +#define WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW2 0x0ea8 +#define WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW3 0x0ea9 +#define WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW4 0x0eaa +#define WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW5 0x0eab +#define WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW1 0x0eac +#define WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW2 0x0ead +#define WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW3 0x0eae +#define WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW4 0x0eaf +#define WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW5 0x0eb0 +#define WCD934X_CDC_RATE_EST3_RE_RMAX_DIAG 0x0eb1 +#define WCD934X_CDC_RATE_EST3_RE_RMIN_DIAG 0x0eb2 +#define WCD934X_CDC_RATE_EST3_RE_PH_DET 0x0eb3 +#define WCD934X_CDC_RATE_EST3_RE_DIAG_CLR 0x0eb4 +#define WCD934X_CDC_RATE_EST3_RE_MB_SW_STATE 0x0eb5 +#define WCD934X_CDC_RATE_EST3_RE_MAST_DIAG_STATE 0x0eb6 +#define WCD934X_CDC_RATE_EST3_RE_RATE_OUT_7_0 0x0eb7 +#define WCD934X_CDC_RATE_EST3_RE_RATE_OUT_15_8 0x0eb8 +#define WCD934X_CDC_RATE_EST3_RE_RATE_OUT_23_16 0x0eb9 +#define WCD934X_CDC_RATE_EST3_RE_RATE_OUT_31_24 0x0eba +#define WCD934X_CDC_RATE_EST3_RE_RATE_OUT_39_32 0x0ebb +#define WCD934X_CDC_RATE_EST3_RE_RATE_OUT_40_43 0x0ebc +#define WCD934X_PAGE15_PAGE_REGISTER 0x0f00 +#define WCD934X_SPLINE_SRC0_CLK_RST_CTL_0 0x0f01 +#define WCD934X_SPLINE_SRC0_STATUS 0x0f02 +#define WCD934X_SPLINE_SRC1_CLK_RST_CTL_0 0x0f19 +#define WCD934X_SPLINE_SRC1_STATUS 0x0f1a +#define WCD934X_SPLINE_SRC2_CLK_RST_CTL_0 0x0f31 +#define WCD934X_SPLINE_SRC2_STATUS 0x0f32 +#define WCD934X_SPLINE_SRC3_CLK_RST_CTL_0 0x0f49 +#define WCD934X_SPLINE_SRC3_STATUS 0x0f4a +#define WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG0 0x0fa1 +#define WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG1 0x0fa2 +#define WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG2 0x0fa3 +#define WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG3 0x0fa4 +#define WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG0 0x0fa5 +#define WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG1 0x0fa6 +#define WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG2 0x0fa7 +#define WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG3 0x0fa8 +#define WCD934X_CDC_DEBUG_SPLINE_SRC_DEBUG_CFG0 0x0fa9 +#define WCD934X_CDC_DEBUG_SPLINE_SRC_DEBUG_CFG1 0x0faa +#define WCD934X_CDC_DEBUG_RC_RE_ASRC_DEBUG_CFG0 0x0fab +#define WCD934X_CDC_DEBUG_ANC0_RC0_FIFO_CTL 0x0fac +#define WCD934X_CDC_DEBUG_ANC0_RC1_FIFO_CTL 0x0fad +#define WCD934X_CDC_DEBUG_ANC1_RC0_FIFO_CTL 0x0fae +#define WCD934X_CDC_DEBUG_ANC1_RC1_FIFO_CTL 0x0faf +#define WCD934X_CDC_DEBUG_ANC_RC_RST_DBG_CNTR 0x0fb0 +#define WCD934X_PAGE80_PAGE_REGISTER 0x5000 +#define WCD934X_CODEC_CPR_WR_DATA_0 0x5001 +#define WCD934X_CODEC_CPR_WR_DATA_1 0x5002 +#define WCD934X_CODEC_CPR_WR_DATA_2 0x5003 +#define WCD934X_CODEC_CPR_WR_DATA_3 0x5004 +#define WCD934X_CODEC_CPR_WR_ADDR_0 0x5005 +#define WCD934X_CODEC_CPR_WR_ADDR_1 0x5006 +#define WCD934X_CODEC_CPR_WR_ADDR_2 0x5007 +#define WCD934X_CODEC_CPR_WR_ADDR_3 0x5008 +#define WCD934X_CODEC_CPR_RD_ADDR_0 0x5009 +#define WCD934X_CODEC_CPR_RD_ADDR_1 0x500a +#define WCD934X_CODEC_CPR_RD_ADDR_2 0x500b +#define WCD934X_CODEC_CPR_RD_ADDR_3 0x500c +#define WCD934X_CODEC_CPR_RD_DATA_0 0x500d +#define WCD934X_CODEC_CPR_RD_DATA_1 0x500e +#define WCD934X_CODEC_CPR_RD_DATA_2 0x500f +#define WCD934X_CODEC_CPR_RD_DATA_3 0x5010 +#define WCD934X_CODEC_CPR_ACCESS_CFG 0x5011 +#define WCD934X_CODEC_CPR_ACCESS_STATUS 0x5012 +#define WCD934X_CODEC_CPR_NOM_CX_VDD 0x5021 +#define WCD934X_CODEC_CPR_SVS_CX_VDD 0x5022 +#define WCD934X_CODEC_CPR_SVS2_CX_VDD 0x5023 +#define WCD934X_CODEC_CPR_NOM_MX_VDD 0x5024 +#define WCD934X_CODEC_CPR_SVS_MX_VDD 0x5025 +#define WCD934X_CODEC_CPR_SVS2_MX_VDD 0x5026 +#define WCD934X_CODEC_CPR_SVS2_MIN_CX_VDD 0x5027 +#define WCD934X_CODEC_CPR_MAX_SVS2_STEP 0x5028 +#define WCD934X_CODEC_CPR_CTL 0x5029 +#define WCD934X_CODEC_CPR_SW_MODECHNG_STATUS 0x502a +#define WCD934X_CODEC_CPR_SW_MODECHNG_START 0x502b +#define WCD934X_CODEC_CPR_CPR_STATUS 0x502c +#define WCD934X_PAGE128_PAGE_REGISTER 0x8000 +#define WCD934X_TLMM_BIST_MODE_PINCFG 0x8001 +#define WCD934X_TLMM_RF_PA_ON_PINCFG 0x8002 +#define WCD934X_TLMM_INTR1_PINCFG 0x8003 +#define WCD934X_TLMM_INTR2_PINCFG 0x8004 +#define WCD934X_TLMM_SWR_DATA_PINCFG 0x8005 +#define WCD934X_TLMM_SWR_CLK_PINCFG 0x8006 +#define WCD934X_TLMM_I2S_2_SCK_PINCFG 0x8007 +#define WCD934X_TLMM_SLIMBUS_DATA1_PINCFG 0x8008 +#define WCD934X_TLMM_SLIMBUS_DATA2_PINCFG 0x8009 +#define WCD934X_TLMM_SLIMBUS_CLK_PINCFG 0x800a +#define WCD934X_TLMM_I2C_CLK_PINCFG 0x800b +#define WCD934X_TLMM_I2C_DATA_PINCFG 0x800c +#define WCD934X_TLMM_I2S_0_RX_PINCFG 0x800d +#define WCD934X_TLMM_I2S_0_TX_PINCFG 0x800e +#define WCD934X_TLMM_I2S_0_SCK_PINCFG 0x800f +#define WCD934X_TLMM_I2S_0_WS_PINCFG 0x8010 +#define WCD934X_TLMM_I2S_1_RX_PINCFG 0x8011 +#define WCD934X_TLMM_I2S_1_TX_PINCFG 0x8012 +#define WCD934X_TLMM_I2S_1_SCK_PINCFG 0x8013 +#define WCD934X_TLMM_I2S_1_WS_PINCFG 0x8014 +#define WCD934X_TLMM_DMIC1_CLK_PINCFG 0x8015 +#define WCD934X_TLMM_DMIC1_DATA_PINCFG 0x8016 +#define WCD934X_TLMM_DMIC2_CLK_PINCFG 0x8017 +#define WCD934X_TLMM_DMIC2_DATA_PINCFG 0x8018 +#define WCD934X_TLMM_DMIC3_CLK_PINCFG 0x8019 +#define WCD934X_TLMM_DMIC3_DATA_PINCFG 0x801a +#define WCD934X_TLMM_JTCK_PINCFG 0x801b +#define WCD934X_TLMM_GPIO1_PINCFG 0x801c +#define WCD934X_TLMM_GPIO2_PINCFG 0x801d +#define WCD934X_TLMM_GPIO3_PINCFG 0x801e +#define WCD934X_TLMM_GPIO4_PINCFG 0x801f +#define WCD934X_TLMM_SPI_S_CSN_PINCFG 0x8020 +#define WCD934X_TLMM_SPI_S_CLK_PINCFG 0x8021 +#define WCD934X_TLMM_SPI_S_DOUT_PINCFG 0x8022 +#define WCD934X_TLMM_SPI_S_DIN_PINCFG 0x8023 +#define WCD934X_TLMM_BA_N_PINCFG 0x8024 +#define WCD934X_TLMM_GPIO0_PINCFG 0x8025 +#define WCD934X_TLMM_I2S_2_RX_PINCFG 0x8026 +#define WCD934X_TLMM_I2S_2_WS_PINCFG 0x8027 +#define WCD934X_TEST_DEBUG_PIN_CTL_OE_0 0x8031 +#define WCD934X_TEST_DEBUG_PIN_CTL_OE_1 0x8032 +#define WCD934X_TEST_DEBUG_PIN_CTL_OE_2 0x8033 +#define WCD934X_TEST_DEBUG_PIN_CTL_OE_3 0x8034 +#define WCD934X_TEST_DEBUG_PIN_CTL_OE_4 0x8035 +#define WCD934X_TEST_DEBUG_PIN_CTL_DATA_0 0x8036 +#define WCD934X_TEST_DEBUG_PIN_CTL_DATA_1 0x8037 +#define WCD934X_TEST_DEBUG_PIN_CTL_DATA_2 0x8038 +#define WCD934X_TEST_DEBUG_PIN_CTL_DATA_3 0x8039 +#define WCD934X_TEST_DEBUG_PIN_CTL_DATA_4 0x803a +#define WCD934X_TEST_DEBUG_PAD_DRVCTL_0 0x803b +#define WCD934X_TEST_DEBUG_PAD_DRVCTL_1 0x803c +#define WCD934X_TEST_DEBUG_PIN_STATUS 0x803d +#define WCD934X_TEST_DEBUG_NPL_DLY_TEST_1 0x803e +#define WCD934X_TEST_DEBUG_NPL_DLY_TEST_2 0x803f +#define WCD934X_TEST_DEBUG_MEM_CTRL 0x8040 +#define WCD934X_TEST_DEBUG_DEBUG_BUS_SEL 0x8041 +#define WCD934X_TEST_DEBUG_DEBUG_JTAG 0x8042 +#define WCD934X_TEST_DEBUG_DEBUG_EN_1 0x8043 +#define WCD934X_TEST_DEBUG_DEBUG_EN_2 0x8044 +#define WCD934X_TEST_DEBUG_DEBUG_EN_3 0x8045 +#define WCD934X_TEST_DEBUG_DEBUG_EN_4 0x8046 +#define WCD934X_TEST_DEBUG_DEBUG_EN_5 0x8047 +#define WCD934X_TEST_DEBUG_ANA_DTEST_DIR 0x804a +#define WCD934X_TEST_DEBUG_PAD_INP_DISABLE_0 0x804b +#define WCD934X_TEST_DEBUG_PAD_INP_DISABLE_1 0x804c +#define WCD934X_TEST_DEBUG_PAD_INP_DISABLE_2 0x804d +#define WCD934X_TEST_DEBUG_PAD_INP_DISABLE_3 0x804e +#define WCD934X_TEST_DEBUG_PAD_INP_DISABLE_4 0x804f +#define WCD934X_TEST_DEBUG_SYSMEM_CTRL 0x8050 +#define WCD934X_TEST_DEBUG_SOC_SW_PWR_SEQ_DELAY 0x8051 +#define WCD934X_TEST_DEBUG_LVAL_NOM_LOW 0x8052 +#define WCD934X_TEST_DEBUG_LVAL_NOM_HIGH 0x8053 +#define WCD934X_TEST_DEBUG_LVAL_SVS_SVS2_LOW 0x8054 +#define WCD934X_TEST_DEBUG_LVAL_SVS_SVS2_HIGH 0x8055 +#define WCD934X_TEST_DEBUG_SPI_SLAVE_CHAR 0x8056 +#define WCD934X_TEST_DEBUG_CODEC_DIAGS 0x8057 +#define WCD934X_MAX_REGISTER 0x80FF + +/* SLIMBUS Slave Registers */ +#define WCD934X_SLIM_PGD_PORT_INT_RX_EN0 (0x30) +#define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (0x32) +#define WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0 (0x34) +#define WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_1 (0x35) +#define WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_0 (0x36) +#define WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1 (0x37) +#define WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 (0x38) +#define WCD934X_SLIM_PGD_PORT_INT_CLR_RX_1 (0x39) +#define WCD934X_SLIM_PGD_PORT_INT_CLR_TX_0 (0x3A) +#define WCD934X_SLIM_PGD_PORT_INT_CLR_TX_1 (0x3B) +#define WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 (0x60) +#define WCD934X_SLIM_PGD_PORT_INT_TX_SOURCE0 (0x70) + +#endif diff --git a/include/linux/mfd/wcd9xxx/Kbuild b/include/linux/mfd/wcd9xxx/Kbuild new file mode 100755 index 000000000000..8e55965bbe7e --- /dev/null +++ b/include/linux/mfd/wcd9xxx/Kbuild @@ -0,0 +1,2 @@ +header-y += wcd9xxx_registers.h +header-y += wcd9320_registers.h diff --git a/include/linux/mfd/wcd9xxx/core.h b/include/linux/mfd/wcd9xxx/core.h new file mode 100644 index 000000000000..6eb8c1893a53 --- /dev/null +++ b/include/linux/mfd/wcd9xxx/core.h @@ -0,0 +1,437 @@ +/* Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MFD_TABLA_CORE_H__ +#define __MFD_TABLA_CORE_H__ + +#include <linux/types.h> +#include <linux/platform_device.h> +#include <linux/of_irq.h> +#include <linux/interrupt.h> +#include <linux/pm_qos.h> + +#define WCD9XXX_MAX_IRQ_REGS 4 +#define WCD9XXX_MAX_NUM_IRQS (WCD9XXX_MAX_IRQ_REGS * 8) +#define WCD9XXX_SLIM_NUM_PORT_REG 3 +#define TABLA_VERSION_1_0 0 +#define TABLA_VERSION_1_1 1 +#define TABLA_VERSION_2_0 2 +#define TABLA_IS_1_X(ver) \ + (((ver == TABLA_VERSION_1_0) || (ver == TABLA_VERSION_1_1)) ? 1 : 0) +#define TABLA_IS_2_0(ver) ((ver == TABLA_VERSION_2_0) ? 1 : 0) + +#define WCD9XXX_SUPPLY_BUCK_NAME "cdc-vdd-buck" + +#define SITAR_VERSION_1P0 0 +#define SITAR_VERSION_1P1 1 +#define SITAR_IS_1P0(ver) \ + ((ver == SITAR_VERSION_1P0) ? 1 : 0) +#define SITAR_IS_1P1(ver) \ + ((ver == SITAR_VERSION_1P1) ? 1 : 0) + +#define TAIKO_VERSION_1_0 1 +#define TAIKO_IS_1_0(ver) \ + ((ver == TAIKO_VERSION_1_0) ? 1 : 0) + +#define TAPAN_VERSION_1_0 0 +#define TAPAN_IS_1_0(ver) \ + ((ver == TAPAN_VERSION_1_0) ? 1 : 0) + +#define TOMTOM_VERSION_1_0 1 +#define TOMTOM_IS_1_0(ver) \ + ((ver == TOMTOM_VERSION_1_0) ? 1 : 0) + +#define TASHA_VERSION_1_0 0 +#define TASHA_VERSION_1_1 1 +#define TASHA_VERSION_2_0 2 + +#define TASHA_IS_1_0(wcd) \ + ((wcd->type == WCD9335 || wcd->type == WCD9326) ? \ + ((wcd->version == TASHA_VERSION_1_0) ? 1 : 0) : 0) + +#define TASHA_IS_1_1(wcd) \ + ((wcd->type == WCD9335 || wcd->type == WCD9326) ? \ + ((wcd->version == TASHA_VERSION_1_1) ? 1 : 0) : 0) + +#define TASHA_IS_2_0(wcd) \ + ((wcd->type == WCD9335 || wcd->type == WCD9326) ? \ + ((wcd->version == TASHA_VERSION_2_0) ? 1 : 0) : 0) + +/* + * As fine version info cannot be retrieved before tavil probe. + * Define three coarse versions for possible future use before tavil probe. + */ +#define TAVIL_VERSION_1_0 0 +#define TAVIL_VERSION_1_1 1 +#define TAVIL_VERSION_WCD9340_1_0 2 +#define TAVIL_VERSION_WCD9341_1_0 3 +#define TAVIL_VERSION_WCD9340_1_1 4 +#define TAVIL_VERSION_WCD9341_1_1 5 + +#define TAVIL_IS_1_0(wcd) \ + ((wcd->type == WCD934X) ? \ + ((wcd->version == TAVIL_VERSION_1_0 || \ + wcd->version == TAVIL_VERSION_WCD9340_1_0 || \ + wcd->version == TAVIL_VERSION_WCD9341_1_0) ? 1 : 0) : 0) +#define TAVIL_IS_1_1(wcd) \ + ((wcd->type == WCD934X) ? \ + ((wcd->version == TAVIL_VERSION_1_1 || \ + wcd->version == TAVIL_VERSION_WCD9340_1_1 || \ + wcd->version == TAVIL_VERSION_WCD9341_1_1) ? 1 : 0) : 0) +#define TAVIL_IS_WCD9340_1_0(wcd) \ + ((wcd->type == WCD934X) ? \ + ((wcd->version == TAVIL_VERSION_WCD9340_1_0) ? 1 : 0) : 0) +#define TAVIL_IS_WCD9341_1_0(wcd) \ + ((wcd->type == WCD934X) ? \ + ((wcd->version == TAVIL_VERSION_WCD9341_1_0) ? 1 : 0) : 0) +#define TAVIL_IS_WCD9340_1_1(wcd) \ + ((wcd->type == WCD934X) ? \ + ((wcd->version == TAVIL_VERSION_WCD9340_1_1) ? 1 : 0) : 0) +#define TAVIL_IS_WCD9341_1_1(wcd) \ + ((wcd->type == WCD934X) ? \ + ((wcd->version == TAVIL_VERSION_WCD9341_1_1) ? 1 : 0) : 0) + +#define IS_CODEC_TYPE(wcd, wcdtype) \ + ((wcd->type == wcdtype) ? true : false) +#define IS_CODEC_VERSION(wcd, wcdversion) \ + ((wcd->version == wcdversion) ? true : false) + +enum { + CDC_V_1_0, + CDC_V_1_1, + CDC_V_2_0, +}; + +enum codec_variant { + WCD9XXX, + WCD9330, + WCD9335, + WCD9326, + WCD934X, +}; + +enum wcd9xxx_slim_slave_addr_type { + WCD9XXX_SLIM_SLAVE_ADDR_TYPE_0, + WCD9XXX_SLIM_SLAVE_ADDR_TYPE_1, +}; + +enum wcd9xxx_pm_state { + WCD9XXX_PM_SLEEPABLE, + WCD9XXX_PM_AWAKE, + WCD9XXX_PM_ASLEEP, +}; + +enum { + WCD9XXX_INTR_STATUS_BASE = 0, + WCD9XXX_INTR_CLEAR_BASE, + WCD9XXX_INTR_MASK_BASE, + WCD9XXX_INTR_LEVEL_BASE, + WCD9XXX_INTR_CLR_COMMIT, + WCD9XXX_INTR_REG_MAX, +}; + +enum wcd9xxx_intf_status { + WCD9XXX_INTERFACE_TYPE_PROBING, + WCD9XXX_INTERFACE_TYPE_SLIMBUS, + WCD9XXX_INTERFACE_TYPE_I2C, +}; + +enum { + /* INTR_REG 0 */ + WCD9XXX_IRQ_SLIMBUS = 0, + WCD9XXX_IRQ_MBHC_REMOVAL, + WCD9XXX_IRQ_MBHC_SHORT_TERM, + WCD9XXX_IRQ_MBHC_PRESS, + WCD9XXX_IRQ_MBHC_RELEASE, + WCD9XXX_IRQ_MBHC_POTENTIAL, + WCD9XXX_IRQ_MBHC_INSERTION, + WCD9XXX_IRQ_BG_PRECHARGE, + /* INTR_REG 1 */ + WCD9XXX_IRQ_PA1_STARTUP, + WCD9XXX_IRQ_PA2_STARTUP, + WCD9XXX_IRQ_PA3_STARTUP, + WCD9XXX_IRQ_PA4_STARTUP, + WCD9306_IRQ_HPH_PA_OCPR_FAULT = WCD9XXX_IRQ_PA4_STARTUP, + WCD9XXX_IRQ_PA5_STARTUP, + WCD9XXX_IRQ_MICBIAS1_PRECHARGE, + WCD9306_IRQ_HPH_PA_OCPL_FAULT = WCD9XXX_IRQ_MICBIAS1_PRECHARGE, + WCD9XXX_IRQ_MICBIAS2_PRECHARGE, + WCD9XXX_IRQ_MICBIAS3_PRECHARGE, + /* INTR_REG 2 */ + WCD9XXX_IRQ_HPH_PA_OCPL_FAULT, + WCD9XXX_IRQ_HPH_PA_OCPR_FAULT, + WCD9XXX_IRQ_EAR_PA_OCPL_FAULT, + WCD9XXX_IRQ_HPH_L_PA_STARTUP, + WCD9XXX_IRQ_HPH_R_PA_STARTUP, + WCD9320_IRQ_EAR_PA_STARTUP, + WCD9306_IRQ_MBHC_JACK_SWITCH = WCD9320_IRQ_EAR_PA_STARTUP, + WCD9310_NUM_IRQS, + WCD9XXX_IRQ_RESERVED_0 = WCD9310_NUM_IRQS, + WCD9XXX_IRQ_RESERVED_1, + WCD9330_IRQ_SVASS_ERR_EXCEPTION = WCD9310_NUM_IRQS, + WCD9330_IRQ_MBHC_JACK_SWITCH, + /* INTR_REG 3 */ + WCD9XXX_IRQ_MAD_AUDIO, + WCD9XXX_IRQ_MAD_ULTRASOUND, + WCD9XXX_IRQ_MAD_BEACON, + WCD9XXX_IRQ_SPEAKER_CLIPPING, + WCD9320_IRQ_MBHC_JACK_SWITCH, + WCD9306_NUM_IRQS, + WCD9XXX_IRQ_VBAT_MONITOR_ATTACK = WCD9306_NUM_IRQS, + WCD9XXX_IRQ_VBAT_MONITOR_RELEASE, + WCD9XXX_NUM_IRQS, + /* WCD9330 INTR1_REG 3*/ + WCD9330_IRQ_SVASS_ENGINE = WCD9XXX_IRQ_MAD_AUDIO, + WCD9330_IRQ_MAD_AUDIO, + WCD9330_IRQ_MAD_ULTRASOUND, + WCD9330_IRQ_MAD_BEACON, + WCD9330_IRQ_SPEAKER1_CLIPPING, + WCD9330_IRQ_SPEAKER2_CLIPPING, + WCD9330_IRQ_VBAT_MONITOR_ATTACK, + WCD9330_IRQ_VBAT_MONITOR_RELEASE, + WCD9330_NUM_IRQS, + WCD9XXX_IRQ_RESERVED_2 = WCD9330_NUM_IRQS, +}; + +enum { + TABLA_NUM_IRQS = WCD9310_NUM_IRQS, + SITAR_NUM_IRQS = WCD9310_NUM_IRQS, + TAIKO_NUM_IRQS = WCD9XXX_NUM_IRQS, + TAPAN_NUM_IRQS = WCD9306_NUM_IRQS, + TOMTOM_NUM_IRQS = WCD9330_NUM_IRQS, +}; + +struct intr_data { + int intr_num; + bool clear_first; +}; + +struct wcd9xxx_core_resource { + struct mutex irq_lock; + struct mutex nested_irq_lock; + + enum wcd9xxx_pm_state pm_state; + struct mutex pm_lock; + /* pm_wq notifies change of pm_state */ + wait_queue_head_t pm_wq; + struct pm_qos_request pm_qos_req; + int wlock_holders; + + + /* holds the table of interrupts per codec */ + const struct intr_data *intr_table; + int intr_table_size; + unsigned int irq_base; + unsigned int irq; + u8 irq_masks_cur[WCD9XXX_MAX_IRQ_REGS]; + u8 irq_masks_cache[WCD9XXX_MAX_IRQ_REGS]; + bool irq_level_high[WCD9XXX_MAX_NUM_IRQS]; + int num_irqs; + int num_irq_regs; + u16 intr_reg[WCD9XXX_INTR_REG_MAX]; + struct regmap *wcd_core_regmap; + + /* Pointer to parent container data structure */ + void *parent; + + struct device *dev; + struct irq_domain *domain; +}; + +/* + * data structure for Slimbus and I2S channel. + * Some of fields are only used in smilbus mode + */ +struct wcd9xxx_ch { + u32 sph; /* share channel handle - slimbus only */ + u32 ch_num; /* + * vitrual channel number, such as 128 -144. + * apply for slimbus only + */ + u16 ch_h; /* chanel handle - slimbus only */ + u16 port; /* + * tabla port for RX and TX + * such as 0-9 for TX and 10 -16 for RX + * apply for both i2s and slimbus + */ + u16 shift; /* + * shift bit for RX and TX + * apply for both i2s and slimbus + */ + struct list_head list; /* + * channel link list + * apply for both i2s and slimbus + */ +}; + +struct wcd9xxx_codec_dai_data { + u32 rate; /* sample rate */ + u32 bit_width; /* sit width 16,24,32 */ + struct list_head wcd9xxx_ch_list; /* channel list */ + u16 grph; /* slimbus group handle */ + unsigned long ch_mask; + wait_queue_head_t dai_wait; + bool bus_down_in_recovery; +}; + +#define WCD9XXX_CH(xport, xshift) \ + {.port = xport, .shift = xshift} + +enum wcd9xxx_chipid_major { + TABLA_MAJOR = cpu_to_le16(0x100), + SITAR_MAJOR = cpu_to_le16(0x101), + TAIKO_MAJOR = cpu_to_le16(0x102), + TAPAN_MAJOR = cpu_to_le16(0x103), + TOMTOM_MAJOR = cpu_to_le16(0x105), + TASHA_MAJOR = cpu_to_le16(0x0), + TASHA2P0_MAJOR = cpu_to_le16(0x107), + TAVIL_MAJOR = cpu_to_le16(0x108), +}; + +enum codec_power_states { + WCD_REGION_POWER_COLLAPSE_REMOVE, + WCD_REGION_POWER_COLLAPSE_BEGIN, + WCD_REGION_POWER_DOWN, +}; + +enum wcd_power_regions { + WCD9XXX_DIG_CORE_REGION_1, + WCD9XXX_MAX_PWR_REGIONS, +}; + +struct wcd9xxx_codec_type { + u16 id_major; + u16 id_minor; + struct mfd_cell *dev; + int size; + int num_irqs; + int version; /* -1 to retrive version from chip version register */ + enum wcd9xxx_slim_slave_addr_type slim_slave_type; + u16 i2c_chip_status; + const struct intr_data *intr_tbl; + int intr_tbl_size; + u16 intr_reg[WCD9XXX_INTR_REG_MAX]; +}; + +struct wcd9xxx_power_region { + enum codec_power_states power_state; + u16 pwr_collapse_reg_min; + u16 pwr_collapse_reg_max; +}; + +struct wcd9xxx { + struct device *dev; + struct slim_device *slim; + struct slim_device *slim_slave; + struct mutex io_lock; + struct mutex xfer_lock; + struct mutex reset_lock; + u8 version; + + int reset_gpio; + struct device_node *wcd_rst_np; + + int (*read_dev)(struct wcd9xxx *wcd9xxx, unsigned short reg, + int bytes, void *dest, bool interface_reg); + int (*write_dev)(struct wcd9xxx *wcd9xxx, unsigned short reg, + int bytes, void *src, bool interface_reg); + int (*multi_reg_write)(struct wcd9xxx *wcd9xxx, const void *data, + size_t count); + int (*dev_down)(struct wcd9xxx *wcd9xxx); + int (*post_reset)(struct wcd9xxx *wcd9xxx); + + void *ssr_priv; + bool dev_up; + + u32 num_of_supplies; + struct regulator_bulk_data *supplies; + + struct wcd9xxx_core_resource core_res; + + u16 id_minor; + u16 id_major; + + /* Slimbus or I2S port */ + u32 num_rx_port; + u32 num_tx_port; + struct wcd9xxx_ch *rx_chs; + struct wcd9xxx_ch *tx_chs; + u32 mclk_rate; + enum codec_variant type; + struct regmap *regmap; + + struct wcd9xxx_codec_type *codec_type; + bool prev_pg_valid; + u8 prev_pg; + u8 avoid_cdc_rstlow; + struct wcd9xxx_power_region *wcd9xxx_pwr[WCD9XXX_MAX_PWR_REGIONS]; +}; + +struct wcd9xxx_reg_val { + unsigned short reg; /* register address */ + u8 *buf; /* buffer to be written to reg. addr */ + int bytes; /* number of bytes to be written */ +}; + +int wcd9xxx_interface_reg_read(struct wcd9xxx *wcd9xxx, unsigned short reg); +int wcd9xxx_interface_reg_write(struct wcd9xxx *wcd9xxx, unsigned short reg, + u8 val); +int wcd9xxx_get_logical_addresses(u8 *pgd_la, u8 *inf_la); +int wcd9xxx_slim_write_repeat(struct wcd9xxx *wcd9xxx, unsigned short reg, + int bytes, void *src); +int wcd9xxx_slim_reserve_bw(struct wcd9xxx *wcd9xxx, + u32 bw_ops, bool commit); +int wcd9xxx_set_power_state(struct wcd9xxx *, enum codec_power_states, + enum wcd_power_regions); +int wcd9xxx_get_current_power_state(struct wcd9xxx *, + enum wcd_power_regions); + +int wcd9xxx_page_write(struct wcd9xxx *wcd9xxx, unsigned short *reg); + +int wcd9xxx_slim_bulk_write(struct wcd9xxx *wcd9xxx, + struct wcd9xxx_reg_val *bulk_reg, + unsigned int size, bool interface); + +extern int wcd9xxx_core_res_init( + struct wcd9xxx_core_resource*, + int, int, struct regmap *); + +extern void wcd9xxx_core_res_deinit( + struct wcd9xxx_core_resource *); + +extern int wcd9xxx_core_res_suspend( + struct wcd9xxx_core_resource *, + pm_message_t); + +extern int wcd9xxx_core_res_resume( + struct wcd9xxx_core_resource *); + +extern int wcd9xxx_core_irq_init( + struct wcd9xxx_core_resource*); + +extern int wcd9xxx_assign_irq(struct wcd9xxx_core_resource*, + unsigned int, + unsigned int); + +extern enum wcd9xxx_intf_status wcd9xxx_get_intf_type(void); +extern void wcd9xxx_set_intf_type(enum wcd9xxx_intf_status); + +extern enum wcd9xxx_pm_state wcd9xxx_pm_cmpxchg( + struct wcd9xxx_core_resource *, + enum wcd9xxx_pm_state, + enum wcd9xxx_pm_state); +static inline int __init wcd9xxx_irq_of_init(struct device_node *node, + struct device_node *parent) +{ + return 0; +} +#endif diff --git a/include/linux/mfd/wcd9xxx/pdata.h b/include/linux/mfd/wcd9xxx/pdata.h new file mode 100755 index 000000000000..7bf2bff2f173 --- /dev/null +++ b/include/linux/mfd/wcd9xxx/pdata.h @@ -0,0 +1,197 @@ +/* Copyright (c) 2011-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MFD_WCD9XXX_PDATA_H__ + +#define __MFD_WCD9XXX_PDATA_H__ + +#include <linux/slimbus/slimbus.h> +#include <linux/mfd/msm-cdc-supply.h> + +#define MICBIAS_EXT_BYP_CAP 0x00 +#define MICBIAS_NO_EXT_BYP_CAP 0x01 + +#define SITAR_LDOH_1P95_V 0x0 +#define SITAR_LDOH_2P35_V 0x1 +#define SITAR_LDOH_2P75_V 0x2 +#define SITAR_LDOH_2P85_V 0x3 + +#define SITAR_CFILT1_SEL 0x0 +#define SITAR_CFILT2_SEL 0x1 +#define SITAR_CFILT3_SEL 0x2 + +#define WCD9XXX_LDOH_1P95_V 0x0 +#define WCD9XXX_LDOH_2P35_V 0x1 +#define WCD9XXX_LDOH_2P75_V 0x2 +#define WCD9XXX_LDOH_2P85_V 0x3 +#define WCD9XXX_LDOH_3P0_V 0x3 + +#define TABLA_LDOH_1P95_V 0x0 +#define TABLA_LDOH_2P35_V 0x1 +#define TABLA_LDOH_2P75_V 0x2 +#define TABLA_LDOH_2P85_V 0x3 + +#define TABLA_CFILT1_SEL 0x0 +#define TABLA_CFILT2_SEL 0x1 +#define TABLA_CFILT3_SEL 0x2 + +#define MAX_AMIC_CHANNEL 7 + +#define TABLA_OCP_300_MA 0x0 +#define TABLA_OCP_350_MA 0x2 +#define TABLA_OCP_365_MA 0x3 +#define TABLA_OCP_150_MA 0x4 +#define TABLA_OCP_190_MA 0x6 +#define TABLA_OCP_220_MA 0x7 + +#define TABLA_DCYCLE_255 0x0 +#define TABLA_DCYCLE_511 0x1 +#define TABLA_DCYCLE_767 0x2 +#define TABLA_DCYCLE_1023 0x3 +#define TABLA_DCYCLE_1279 0x4 +#define TABLA_DCYCLE_1535 0x5 +#define TABLA_DCYCLE_1791 0x6 +#define TABLA_DCYCLE_2047 0x7 +#define TABLA_DCYCLE_2303 0x8 +#define TABLA_DCYCLE_2559 0x9 +#define TABLA_DCYCLE_2815 0xA +#define TABLA_DCYCLE_3071 0xB +#define TABLA_DCYCLE_3327 0xC +#define TABLA_DCYCLE_3583 0xD +#define TABLA_DCYCLE_3839 0xE +#define TABLA_DCYCLE_4095 0xF + +#define WCD9XXX_MCLK_CLK_12P288MHZ 12288000 +#define WCD9XXX_MCLK_CLK_9P6HZ 9600000 + +/* Only valid for 9.6 MHz mclk */ +#define WCD9XXX_DMIC_SAMPLE_RATE_600KHZ 600000 +#define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000 +#define WCD9XXX_DMIC_SAMPLE_RATE_3P2MHZ 3200000 +#define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000 + +/* Only valid for 12.288 MHz mclk */ +#define WCD9XXX_DMIC_SAMPLE_RATE_768KHZ 768000 +#define WCD9XXX_DMIC_SAMPLE_RATE_2P048MHZ 2048000 +#define WCD9XXX_DMIC_SAMPLE_RATE_3P072MHZ 3072000 +#define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000 +#define WCD9XXX_DMIC_SAMPLE_RATE_6P144MHZ 6144000 + +#define WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED 0 + +#define WCD9XXX_DMIC_CLK_DRIVE_UNDEFINED 0 + +struct wcd9xxx_amic { + /*legacy mode, txfe_enable and txfe_buff take 7 input + * each bit represent the channel / TXFE number + * and numbered as below + * bit 0 = channel 1 / TXFE1_ENABLE / TXFE1_BUFF + * bit 1 = channel 2 / TXFE2_ENABLE / TXFE2_BUFF + * ... + * bit 7 = channel 7 / TXFE7_ENABLE / TXFE7_BUFF + */ + u8 legacy_mode:MAX_AMIC_CHANNEL; + u8 txfe_enable:MAX_AMIC_CHANNEL; + u8 txfe_buff:MAX_AMIC_CHANNEL; + u8 use_pdata:MAX_AMIC_CHANNEL; +}; + +/* Each micbias can be assigned to one of three cfilters + * Vbatt_min >= .15V + ldoh_v + * ldoh_v >= .15v + cfiltx_mv + * If ldoh_v = 1.95 160 mv < cfiltx_mv < 1800 mv + * If ldoh_v = 2.35 200 mv < cfiltx_mv < 2200 mv + * If ldoh_v = 2.75 240 mv < cfiltx_mv < 2600 mv + * If ldoh_v = 2.85 250 mv < cfiltx_mv < 2700 mv + */ + +struct wcd9xxx_micbias_setting { + u8 ldoh_v; + u32 cfilt1_mv; /* in mv */ + u32 cfilt2_mv; /* in mv */ + u32 cfilt3_mv; /* in mv */ + u32 micb1_mv; + u32 micb2_mv; + u32 micb3_mv; + u32 micb4_mv; + /* Different WCD9xxx series codecs may not + * have 4 mic biases. If a codec has fewer + * mic biases, some of these properties will + * not be used. + */ + u8 bias1_cfilt_sel; + u8 bias2_cfilt_sel; + u8 bias3_cfilt_sel; + u8 bias4_cfilt_sel; + u8 bias1_cap_mode; + u8 bias2_cap_mode; + u8 bias3_cap_mode; + u8 bias4_cap_mode; + bool bias2_is_headset_only; +}; + +struct wcd9xxx_ocp_setting { + unsigned int use_pdata:1; /* 0 - use sys default as recommended */ + unsigned int num_attempts:4; /* up to 15 attempts */ + unsigned int run_time:4; /* in duty cycle */ + unsigned int wait_time:4; /* in duty cycle */ + unsigned int hph_ocp_limit:3; /* Headphone OCP current limit */ +}; + +#define WCD9XXX_MAX_REGULATOR 9 +/* + * format : TABLA_<POWER_SUPPLY_PIN_NAME>_CUR_MAX + * + * <POWER_SUPPLY_PIN_NAME> from Tabla objective spec +*/ + +#define WCD9XXX_CDC_VDDA_CP_CUR_MAX 500000 +#define WCD9XXX_CDC_VDDA_RX_CUR_MAX 20000 +#define WCD9XXX_CDC_VDDA_TX_CUR_MAX 20000 +#define WCD9XXX_VDDIO_CDC_CUR_MAX 5000 + +#define WCD9XXX_VDDD_CDC_D_CUR_MAX 5000 +#define WCD9XXX_VDDD_CDC_A_CUR_MAX 5000 + +#define WCD9XXX_VDD_SPKDRV_NAME "cdc-vdd-spkdrv" +#define WCD9XXX_VDD_SPKDRV2_NAME "cdc-vdd-spkdrv-2" + +struct wcd9xxx_regulator { + const char *name; + int min_uV; + int max_uV; + int optimum_uA; + bool ondemand; + struct regulator *regulator; +}; + +struct wcd9xxx_pdata { + int irq; + int irq_base; + int num_irqs; + int reset_gpio; + struct device_node *wcd_rst_np; + struct wcd9xxx_amic amic_settings; + struct slim_device slimbus_slave_device; + struct wcd9xxx_micbias_setting micbias; + struct wcd9xxx_ocp_setting ocp; + struct cdc_regulator *regulator; + int num_supplies; + u32 mclk_rate; + u32 dmic_sample_rate; + u32 mad_dmic_sample_rate; + u32 ecpp_dmic_sample_rate; + u32 dmic_clk_drv; + u16 use_pinctrl; +}; + +#endif diff --git a/include/linux/mfd/wcd9xxx/wcd9310_registers.h b/include/linux/mfd/wcd9xxx/wcd9310_registers.h new file mode 100755 index 000000000000..cec0ce2dd558 --- /dev/null +++ b/include/linux/mfd/wcd9xxx/wcd9310_registers.h @@ -0,0 +1,1106 @@ +#ifndef TABLA_CODEC_DIGITAL_H + +#define TABLA_CODEC_DIGITAL_H +#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h> + +#define TABLA_A_CHIP_CTL WCD9XXX_A_CHIP_CTL +#define TABLA_A_CHIP_CTL__POR WCD9XXX_A_CHIP_CTL__POR +#define TABLA_A_CHIP_STATUS WCD9XXX_A_CHIP_STATUS +#define TABLA_A_CHIP_STATUS__POR WCD9XXX_A_CHIP_STATUS__POR +#define TABLA_A_CHIP_ID_BYTE_0 WCD9XXX_A_CHIP_ID_BYTE_0 +#define TABLA_A_CHIP_ID_BYTE_0__POR WCD9XXX_A_CHIP_ID_BYTE_0__POR +#define TABLA_A_CHIP_ID_BYTE_1 WCD9XXX_A_CHIP_ID_BYTE_1 +#define TABLA_A_CHIP_ID_BYTE_1__POR WCD9XXX_A_CHIP_ID_BYTE_1__POR +#define TABLA_A_CHIP_ID_BYTE_2 WCD9XXX_A_CHIP_ID_BYTE_2 +#define TABLA_A_CHIP_ID_BYTE_2__POR WCD9XXX_A_CHIP_ID_BYTE_2__POR +#define TABLA_A_CHIP_ID_BYTE_3 WCD9XXX_A_CHIP_ID_BYTE_3 +#define TABLA_A_CHIP_ID_BYTE_3__POR WCD9XXX_A_CHIP_ID_BYTE_3__POR +#define TABLA_A_CHIP_VERSION WCD9XXX_A_CHIP_VERSION +#define TABLA_A_CHIP_VERSION__POR WCD9XXX_A_CHIP_VERSION__POR +#define TABLA_A_SB_VERSION WCD9XXX_A_SB_VERSION +#define TABLA_A_SB_VERSION__POR WCD9XXX_A_SB_VERSION__POR +#define TABLA_A_SLAVE_ID_1 WCD9XXX_A_SLAVE_ID_1 +#define TABLA_A_SLAVE_ID_1__POR WCD9XXX_A_SLAVE_ID_1__POR +#define TABLA_A_SLAVE_ID_2 WCD9XXX_A_SLAVE_ID_2 +#define TABLA_A_SLAVE_ID_2__POR WCD9XXX_A_SLAVE_ID_2__POR +#define TABLA_A_SLAVE_ID_3 WCD9XXX_A_SLAVE_ID_3 +#define TABLA_A_SLAVE_ID_3__POR WCD9XXX_A_SLAVE_ID_3__POR +#define TABLA_A_PIN_CTL_OE0 (0x10) +#define TABLA_A_PIN_CTL_OE0__POR (0x00000000) +#define TABLA_A_PIN_CTL_OE1 (0x11) +#define TABLA_A_PIN_CTL_OE1__POR (0x00000000) +#define TABLA_A_PIN_CTL_DATA0 (0x12) +#define TABLA_A_PIN_CTL_DATA0__POR (0x00000000) +#define TABLA_A_PIN_CTL_DATA1 (0x13) +#define TABLA_A_PIN_CTL_DATA1__POR (0x00000000) +#define TABLA_A_HDRIVE_GENERIC (0x18) +#define TABLA_A_HDRIVE_GENERIC__POR (0x00000000) +#define TABLA_A_HDRIVE_OVERRIDE (0x19) +#define TABLA_A_HDRIVE_OVERRIDE__POR (0x00000008) +#define TABLA_A_ANA_CSR_WAIT_STATE (0x20) +#define TABLA_A_ANA_CSR_WAIT_STATE__POR (0x00000044) +#define TABLA_A_PROCESS_MONITOR_CTL0 (0x40) +#define TABLA_A_PROCESS_MONITOR_CTL0__POR (0x00000080) +#define TABLA_A_PROCESS_MONITOR_CTL1 (0x41) +#define TABLA_A_PROCESS_MONITOR_CTL1__POR (0x00000000) +#define TABLA_A_PROCESS_MONITOR_CTL2 (0x42) +#define TABLA_A_PROCESS_MONITOR_CTL2__POR (0x00000000) +#define TABLA_A_PROCESS_MONITOR_CTL3 (0x43) +#define TABLA_A_PROCESS_MONITOR_CTL3__POR (0x00000001) +#define TABLA_A_QFUSE_CTL (0x48) +#define TABLA_A_QFUSE_CTL__POR (0x00000000) +#define TABLA_A_QFUSE_STATUS (0x49) +#define TABLA_A_QFUSE_STATUS__POR (0x00000000) +#define TABLA_A_QFUSE_DATA_OUT0 (0x4A) +#define TABLA_A_QFUSE_DATA_OUT0__POR (0x00000000) +#define TABLA_A_QFUSE_DATA_OUT1 (0x4B) +#define TABLA_A_QFUSE_DATA_OUT1__POR (0x00000000) +#define TABLA_A_QFUSE_DATA_OUT2 (0x4C) +#define TABLA_A_QFUSE_DATA_OUT2__POR (0x00000000) +#define TABLA_A_QFUSE_DATA_OUT3 (0x4D) +#define TABLA_A_QFUSE_DATA_OUT3__POR (0x00000000) +#define TABLA_A_CDC_CTL WCD9XXX_A_CDC_CTL +#define TABLA_A_CDC_CTL__POR WCD9XXX_A_CDC_CTL__POR +#define TABLA_A_LEAKAGE_CTL WCD9XXX_A_LEAKAGE_CTL +#define TABLA_A_LEAKAGE_CTL__POR WCD9XXX_A_LEAKAGE_CTL__POR +#define TABLA_A_INTR_MODE (0x90) +#define TABLA_A_INTR_MODE__POR (0x00000000) +#define TABLA_A_INTR_MASK0 (0x94) +#define TABLA_A_INTR_MASK0__POR (0x000000ff) +#define TABLA_A_INTR_MASK1 (0x95) +#define TABLA_A_INTR_MASK1__POR (0x000000ff) +#define TABLA_A_INTR_MASK2 (0x96) +#define TABLA_A_INTR_MASK2__POR (0x000000ff) +#define TABLA_A_INTR_STATUS0 (0x98) +#define TABLA_A_INTR_STATUS0__POR (0x00000000) +#define TABLA_A_INTR_STATUS1 (0x99) +#define TABLA_A_INTR_STATUS1__POR (0x00000000) +#define TABLA_A_INTR_STATUS2 (0x9A) +#define TABLA_A_INTR_STATUS2__POR (0x00000000) +#define TABLA_A_INTR_CLEAR0 (0x9C) +#define TABLA_A_INTR_CLEAR0__POR (0x00000000) +#define TABLA_A_INTR_CLEAR1 (0x9D) +#define TABLA_A_INTR_CLEAR1__POR (0x00000000) +#define TABLA_A_INTR_CLEAR2 (0x9E) +#define TABLA_A_INTR_CLEAR2__POR (0x00000000) +#define TABLA_A_INTR_LEVEL0 (0xA0) +#define TABLA_A_INTR_LEVEL0__POR (0x00000001) +#define TABLA_A_INTR_LEVEL1 (0xA1) +#define TABLA_A_INTR_LEVEL1__POR (0x00000000) +#define TABLA_A_INTR_LEVEL2 (0xA2) +#define TABLA_A_INTR_LEVEL2__POR (0x00000000) +#define TABLA_A_INTR_TEST0 (0xA4) +#define TABLA_A_INTR_TEST0__POR (0x00000000) +#define TABLA_A_INTR_TEST1 (0xA5) +#define TABLA_A_INTR_TEST1__POR (0x00000000) +#define TABLA_A_INTR_TEST2 (0xA6) +#define TABLA_A_INTR_TEST2__POR (0x00000000) +#define TABLA_A_INTR_SET0 (0xA8) +#define TABLA_A_INTR_SET0__POR (0x00000000) +#define TABLA_A_INTR_SET1 (0xA9) +#define TABLA_A_INTR_SET1__POR (0x00000000) +#define TABLA_A_INTR_SET2 (0xAA) +#define TABLA_A_INTR_SET2__POR (0x00000000) +#define TABLA_A_CDC_TX_I2S_SCK_MODE (0xC0) +#define TABLA_A_CDC_TX_I2S_SCK_MODE__POR (0x00000000) +#define TABLA_A_CDC_TX_I2S_WS_MODE (0xC1) +#define TABLA_A_CDC_TX_I2S_WS_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_DATA0_MODE (0xC4) +#define TABLA_A_CDC_DMIC_DATA0_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_CLK0_MODE (0xC5) +#define TABLA_A_CDC_DMIC_CLK0_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_DATA1_MODE (0xC6) +#define TABLA_A_CDC_DMIC_DATA1_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_CLK1_MODE (0xC7) +#define TABLA_A_CDC_DMIC_CLK1_MODE__POR (0x00000000) +#define TABLA_A_CDC_RX_I2S_SCK_MODE (0xC8) +#define TABLA_A_CDC_RX_I2S_SCK_MODE__POR (0x00000000) +#define TABLA_A_CDC_RX_I2S_WS_MODE (0xC9) +#define TABLA_A_CDC_RX_I2S_WS_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_DATA2_MODE (0xCA) +#define TABLA_A_CDC_DMIC_DATA2_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_CLK2_MODE (0xCB) +#define TABLA_A_CDC_DMIC_CLK2_MODE__POR (0x00000000) +#define TABLA_A_CDC_INTR_MODE (0xCC) +#define TABLA_A_CDC_INTR_MODE__POR (0x00000000) +#define TABLA_A_BIAS_REF_CTL (0x0100) +#define TABLA_A_BIAS_REF_CTL__POR (0x0000001C) +#define TABLA_A_BIAS_CENTRAL_BG_CTL (0x0101) +#define TABLA_A_BIAS_CENTRAL_BG_CTL__POR (0x00000050) +#define TABLA_A_BIAS_PRECHRG_CTL (0x0102) +#define TABLA_A_BIAS_PRECHRG_CTL__POR (0x00000007) +#define TABLA_A_BIAS_CURR_CTL_1 (0x0103) +#define TABLA_A_BIAS_CURR_CTL_1__POR (0x00000052) +#define TABLA_A_BIAS_CURR_CTL_2 (0x0104) +#define TABLA_A_BIAS_CURR_CTL_2__POR (0x00000000) +#define TABLA_A_BIAS_CONFIG_MODE_BG_CTL (0x0105) +#define TABLA_A_BIAS_CONFIG_MODE_BG_CTL__POR (0x00000016) +#define TABLA_A_BIAS_BG_STATUS (0x0106) +#define TABLA_A_BIAS_BG_STATUS__POR (0x00000000) +#define TABLA_A_CLK_BUFF_EN1 (0x0108) +#define TABLA_A_CLK_BUFF_EN1__POR (0x00000004) +#define TABLA_A_CLK_BUFF_EN2 (0x0109) +#define TABLA_A_CLK_BUFF_EN2__POR (0x00000002) +#define TABLA_A_LDO_H_MODE_1 (0x0110) +#define TABLA_A_LDO_H_MODE_1__POR (0x00000065) +#define TABLA_A_LDO_H_MODE_2 (0x0111) +#define TABLA_A_LDO_H_MODE_2__POR (0x000000A8) +#define TABLA_A_LDO_H_LOOP_CTL (0x0112) +#define TABLA_A_LDO_H_LOOP_CTL__POR (0x0000006B) +#define TABLA_A_LDO_H_COMP_1 (0x0113) +#define TABLA_A_LDO_H_COMP_1__POR (0x00000084) +#define TABLA_A_LDO_H_COMP_2 (0x0114) +#define TABLA_A_LDO_H_COMP_2__POR (0x000000E0) +#define TABLA_A_LDO_H_BIAS_1 (0x0115) +#define TABLA_A_LDO_H_BIAS_1__POR (0x0000006D) +#define TABLA_A_LDO_H_BIAS_2 (0x0116) +#define TABLA_A_LDO_H_BIAS_2__POR (0x000000A5) +#define TABLA_A_LDO_H_BIAS_3 (0x0117) +#define TABLA_A_LDO_H_BIAS_3__POR (0x00000060) +#define TABLA_A_LDO_L_MODE_1 (0x0118) +#define TABLA_A_LDO_L_MODE_1__POR (0x00000028) +#define TABLA_A_LDO_L_MODE_2 (0x0119) +#define TABLA_A_LDO_L_MODE_2__POR (0x000000A8) +#define TABLA_A_LDO_L_LOOP_CTL (0x011A) +#define TABLA_A_LDO_L_LOOP_CTL__POR (0x0000006D) +#define TABLA_A_LDO_L_COMP_1 (0x011B) +#define TABLA_A_LDO_L_COMP_1__POR (0x00000031) +#define TABLA_A_LDO_L_COMP_2 (0x011C) +#define TABLA_A_LDO_L_COMP_2__POR (0x000000A0) +#define TABLA_A_LDO_L_BIAS_1 (0x011D) +#define TABLA_A_LDO_L_BIAS_1__POR (0x0000006D) +#define TABLA_A_LDO_L_BIAS_2 (0x011E) +#define TABLA_A_LDO_L_BIAS_2__POR (0x00000065) +#define TABLA_A_LDO_L_BIAS_3 (0x011F) +#define TABLA_A_LDO_L_BIAS_3__POR (0x00000050) +#define TABLA_A_MICB_CFILT_1_CTL (0x0128) +#define TABLA_A_MICB_CFILT_1_CTL__POR (0x00000040) +#define TABLA_A_MICB_CFILT_1_VAL (0x0129) +#define TABLA_A_MICB_CFILT_1_VAL__POR (0x00000080) +#define TABLA_A_MICB_CFILT_1_PRECHRG (0x012A) +#define TABLA_A_MICB_CFILT_1_PRECHRG__POR (0x00000038) +#define TABLA_A_MICB_1_CTL (0x012B) +#define TABLA_A_MICB_1_CTL__POR (0x00000016) +#define TABLA_A_MICB_1_INT_RBIAS (0x012C) +#define TABLA_A_MICB_1_INT_RBIAS__POR (0x00000000) +#define TABLA_A_MICB_1_MBHC (0x012D) +#define TABLA_A_MICB_1_MBHC__POR (0x00000001) +#define TABLA_A_MICB_CFILT_2_CTL (0x012E) +#define TABLA_A_MICB_CFILT_2_CTL__POR (0x00000040) +#define TABLA_A_MICB_CFILT_2_VAL (0x012F) +#define TABLA_A_MICB_CFILT_2_VAL__POR (0x00000080) +#define TABLA_A_MICB_CFILT_2_PRECHRG (0x0130) +#define TABLA_A_MICB_CFILT_2_PRECHRG__POR (0x00000038) +#define TABLA_A_MICB_2_CTL (0x0131) +#define TABLA_A_MICB_2_CTL__POR (0x00000016) +#define TABLA_A_MICB_2_INT_RBIAS (0x0132) +#define TABLA_A_MICB_2_INT_RBIAS__POR (0x00000000) +#define TABLA_A_MICB_2_MBHC (0x0133) +#define TABLA_A_MICB_2_MBHC__POR (0x00000000) +#define TABLA_A_MICB_CFILT_3_CTL (0x0134) +#define TABLA_A_MICB_CFILT_3_CTL__POR (0x00000040) +#define TABLA_A_MICB_CFILT_3_VAL (0x0135) +#define TABLA_A_MICB_CFILT_3_VAL__POR (0x00000080) +#define TABLA_A_MICB_CFILT_3_PRECHRG (0x0136) +#define TABLA_A_MICB_CFILT_3_PRECHRG__POR (0x00000038) +#define TABLA_A_MICB_3_CTL (0x0137) +#define TABLA_A_MICB_3_CTL__POR (0x00000016) +#define TABLA_A_MICB_3_INT_RBIAS (0x0138) +#define TABLA_A_MICB_3_INT_RBIAS__POR (0x00000000) +#define TABLA_A_MICB_3_MBHC (0x0139) +#define TABLA_A_MICB_3_MBHC__POR (0x00000000) +#define TABLA_1_A_MICB_4_CTL (0x013A) +#define TABLA_2_A_MICB_4_CTL (0x013D) +#define TABLA_A_MICB_4_CTL__POR (0x00000016) +#define TABLA_1_A_MICB_4_INT_RBIAS (0x013B) +#define TABLA_2_A_MICB_4_INT_RBIAS (0x013E) +#define TABLA_A_MICB_4_INT_RBIAS__POR (0x00000000) +#define TABLA_1_A_MICB_4_MBHC (0x013C) +#define TABLA_2_A_MICB_4_MBHC (0x013F) +#define TABLA_A_MICB_4_MBHC__POR (0x00000001) +#define TABLA_A_TX_COM_BIAS (0x014C) +#define TABLA_A_TX_COM_BIAS__POR (0x000000E0) +#define TABLA_A_MBHC_SCALING_MUX_1 (0x014E) +#define TABLA_A_MBHC_SCALING_MUX_1__POR (0x00000000) +#define TABLA_A_MBHC_SCALING_MUX_2 (0x014F) +#define TABLA_A_MBHC_SCALING_MUX_2__POR (0x00000080) +#define TABLA_A_TX_SUP_SWITCH_CTRL_1 (0x0151) +#define TABLA_A_TX_SUP_SWITCH_CTRL_1__POR (0x00000000) +#define TABLA_A_TX_SUP_SWITCH_CTRL_2 (0x0152) +#define TABLA_A_TX_SUP_SWITCH_CTRL_2__POR (0x00000080) +#define TABLA_A_TX_1_2_EN (0x0153) +#define TABLA_A_TX_1_2_EN__POR (0x00000000) +#define TABLA_A_TX_1_2_TEST_EN (0x0154) +#define TABLA_A_TX_1_2_TEST_EN__POR (0x000000CC) +#define TABLA_A_TX_1_2_ADC_CH1 (0x0155) +#define TABLA_A_TX_1_2_ADC_CH1__POR (0x00000044) +#define TABLA_A_TX_1_2_ADC_CH2 (0x0156) +#define TABLA_A_TX_1_2_ADC_CH2__POR (0x00000044) +#define TABLA_A_TX_1_2_ATEST_REFCTRL (0x0157) +#define TABLA_A_TX_1_2_ATEST_REFCTRL__POR (0x00000000) +#define TABLA_A_TX_1_2_TEST_CTL (0x0158) +#define TABLA_A_TX_1_2_TEST_CTL__POR (0x00000038) +#define TABLA_A_TX_1_2_TEST_BLOCK_EN (0x0159) +#define TABLA_A_TX_1_2_TEST_BLOCK_EN__POR (0x000000FF) +#define TABLA_A_TX_1_2_TXFE_CLKDIV (0x015A) +#define TABLA_A_TX_1_2_TXFE_CLKDIV__POR (0x000000EE) +#define TABLA_A_TX_1_2_SAR_ERR_CH1 (0x015B) +#define TABLA_A_TX_1_2_SAR_ERR_CH1__POR (0x00000000) +#define TABLA_A_TX_1_2_SAR_ERR_CH2 (0x015C) +#define TABLA_A_TX_1_2_SAR_ERR_CH2__POR (0x00000000) +#define TABLA_A_TX_3_4_EN (0x015D) +#define TABLA_A_TX_3_4_EN__POR (0x00000000) +#define TABLA_A_TX_3_4_TEST_EN (0x015E) +#define TABLA_A_TX_3_4_TEST_EN__POR (0x000000CC) +#define TABLA_A_TX_3_4_ADC_CH3 (0x015F) +#define TABLA_A_TX_3_4_ADC_CH3__POR (0x00000044) +#define TABLA_A_TX_3_4_ADC_CH4 (0x0160) +#define TABLA_A_TX_3_4_ADC_CH4__POR (0x00000044) +#define TABLA_A_TX_3_4_ATEST_REFCTRL (0x0161) +#define TABLA_A_TX_3_4_ATEST_REFCTRL__POR (0x00000000) +#define TABLA_A_TX_3_4_TEST_CTL (0x0162) +#define TABLA_A_TX_3_4_TEST_CTL__POR (0x00000038) +#define TABLA_A_TX_3_4_TEST_BLOCK_EN (0x0163) +#define TABLA_A_TX_3_4_TEST_BLOCK_EN__POR (0x000000FF) +#define TABLA_A_TX_3_4_TXFE_CKDIV (0x0164) +#define TABLA_A_TX_3_4_TXFE_CKDIV__POR (0x000000EE) +#define TABLA_A_TX_3_4_SAR_ERR_CH3 (0x0165) +#define TABLA_A_TX_3_4_SAR_ERR_CH3__POR (0x00000000) +#define TABLA_A_TX_3_4_SAR_ERR_CH4 (0x0166) +#define TABLA_A_TX_3_4_SAR_ERR_CH4__POR (0x00000000) +#define TABLA_A_TX_5_6_EN (0x0167) +#define TABLA_A_TX_5_6_EN__POR (0x00000011) +#define TABLA_A_TX_5_6_TEST_EN (0x0168) +#define TABLA_A_TX_5_6_TEST_EN__POR (0x000000CC) +#define TABLA_A_TX_5_6_ADC_CH5 (0x0169) +#define TABLA_A_TX_5_6_ADC_CH5__POR (0x00000044) +#define TABLA_A_TX_5_6_ADC_CH6 (0x016A) +#define TABLA_A_TX_5_6_ADC_CH6__POR (0x00000044) +#define TABLA_A_TX_5_6_ATEST_REFCTRL (0x016B) +#define TABLA_A_TX_5_6_ATEST_REFCTRL__POR (0x00000000) +#define TABLA_A_TX_5_6_TEST_CTL (0x016C) +#define TABLA_A_TX_5_6_TEST_CTL__POR (0x00000038) +#define TABLA_A_TX_5_6_TEST_BLOCK_EN (0x016D) +#define TABLA_A_TX_5_6_TEST_BLOCK_EN__POR (0x000000FF) +#define TABLA_A_TX_5_6_TXFE_CKDIV (0x016E) +#define TABLA_A_TX_5_6_TXFE_CKDIV__POR (0x000000EE) +#define TABLA_A_TX_5_6_SAR_ERR_CH5 (0x016F) +#define TABLA_A_TX_5_6_SAR_ERR_CH5__POR (0x00000000) +#define TABLA_A_TX_5_6_SAR_ERR_CH6 (0x0170) +#define TABLA_A_TX_5_6_SAR_ERR_CH6__POR (0x00000000) +#define TABLA_A_TX_7_MBHC_EN (0x0171) +#define TABLA_A_TX_7_MBHC_EN__POR (0x0000000C) +#define TABLA_A_TX_7_MBHC_ATEST_REFCTRL (0x0172) +#define TABLA_A_TX_7_MBHC_ATEST_REFCTRL__POR (0x00000000) +#define TABLA_A_TX_7_MBHC_ADC (0x0173) +#define TABLA_A_TX_7_MBHC_ADC__POR (0x00000044) +#define TABLA_A_TX_7_MBHC_TEST_CTL (0x0174) +#define TABLA_A_TX_7_MBHC_TEST_CTL__POR (0x00000038) +#define TABLA_A_TX_7_MBHC_SAR_ERR (0x0175) +#define TABLA_A_TX_7_MBHC_SAR_ERR__POR (0x00000000) +#define TABLA_A_TX_7_TXFE_CLKDIV (0x0176) +#define TABLA_A_TX_7_TXFE_CLKDIV__POR (0x0000001C) +#define TABLA_A_AUX_COM_CTL (0x0180) +#define TABLA_A_AUX_COM_CTL__POR (0x00000034) +#define TABLA_A_AUX_COM_ATEST (0x0181) +#define TABLA_A_AUX_COM_ATEST__POR (0x00000000) +#define TABLA_A_AUX_L_EN (0x0182) +#define TABLA_A_AUX_L_EN__POR (0x00000000) +#define TABLA_A_AUX_L_GAIN (0x0183) +#define TABLA_A_AUX_L_GAIN__POR (0x0000001F) +#define TABLA_A_AUX_L_PA_CONN (0x0184) +#define TABLA_A_AUX_L_PA_CONN__POR (0x00000000) +#define TABLA_A_AUX_L_PA_CONN_INV (0x0185) +#define TABLA_A_AUX_L_PA_CONN_INV__POR (0x00000000) +#define TABLA_A_AUX_R_EN (0x0186) +#define TABLA_A_AUX_R_EN__POR (0x00000000) +#define TABLA_A_AUX_R_GAIN (0x0187) +#define TABLA_A_AUX_R_GAIN__POR (0x0000001F) +#define TABLA_A_AUX_R_PA_CONN (0x0188) +#define TABLA_A_AUX_R_PA_CONN__POR (0x00000000) +#define TABLA_A_AUX_R_PA_CONN_INV (0x0189) +#define TABLA_A_AUX_R_PA_CONN_INV__POR (0x00000000) +#define TABLA_A_CP_EN (0x0192) +#define TABLA_A_CP_EN__POR (0x000000E6) +#define TABLA_A_CP_CLK (0x0193) +#define TABLA_A_CP_CLK__POR (0x00000029) +#define TABLA_A_CP_STATIC (0x0194) +#define TABLA_A_CP_STATIC__POR (0x00000010) +#define TABLA_A_CP_DCC1 (0x0195) +#define TABLA_A_CP_DCC1__POR (0x00000052) +#define TABLA_A_CP_DCC3 (0x0196) +#define TABLA_A_CP_DCC3__POR (0x00000001) +#define TABLA_A_CP_ATEST (0x0197) +#define TABLA_A_CP_ATEST__POR (0x00000000) +#define TABLA_A_CP_DTEST (0x0198) +#define TABLA_A_CP_DTEST__POR (0x00000000) +#define TABLA_A_RX_COM_TIMER_DIV (0x019E) +#define TABLA_A_RX_COM_TIMER_DIV__POR (0x000000E8) +#define TABLA_A_RX_COM_OCP_CTL (0x019F) +#define TABLA_A_RX_COM_OCP_CTL__POR (0x0000001F) +#define TABLA_A_RX_COM_OCP_COUNT (0x01A0) +#define TABLA_A_RX_COM_OCP_COUNT__POR (0x00000077) +#define TABLA_A_RX_COM_DAC_CTL (0x01A1) +#define TABLA_A_RX_COM_DAC_CTL__POR (0x00000000) +#define TABLA_A_RX_COM_BIAS (0x01A2) +#define TABLA_A_RX_COM_BIAS__POR (0x00000000) +#define TABLA_A_RX_HPH_BIAS_PA (0x01A6) +#define TABLA_A_RX_HPH_BIAS_PA__POR (0x000000AA) +#define TABLA_A_RX_HPH_BIAS_LDO (0x01A7) +#define TABLA_A_RX_HPH_BIAS_LDO__POR (0x00000086) +#define TABLA_A_RX_HPH_BIAS_CNP (0x01A8) +#define TABLA_A_RX_HPH_BIAS_CNP__POR (0x0000008A) +#define TABLA_A_RX_HPH_BIAS_WG (0x01A9) +#define TABLA_A_RX_HPH_BIAS_WG__POR (0x00000060) +#define TABLA_A_RX_HPH_OCP_CTL (0x01AA) +#define TABLA_A_RX_HPH_OCP_CTL__POR (0x000000E8) +#define TABLA_A_RX_HPH_CNP_EN (0x01AB) +#define TABLA_A_RX_HPH_CNP_EN__POR (0x00000080) +#define TABLA_A_RX_HPH_CNP_WG_CTL (0x01AC) +#define TABLA_A_RX_HPH_CNP_WG_CTL__POR (0x000000DC) +#define TABLA_A_RX_HPH_CNP_WG_TIME (0x01AD) +#define TABLA_A_RX_HPH_CNP_WG_TIME__POR (0x00000028) +#define TABLA_A_RX_HPH_L_GAIN (0x01AE) +#define TABLA_A_RX_HPH_L_GAIN__POR (0x00000000) +#define TABLA_A_RX_HPH_L_TEST (0x01AF) +#define TABLA_A_RX_HPH_L_TEST__POR (0x00000001) +#define TABLA_A_RX_HPH_L_PA_CTL (0x01B0) +#define TABLA_A_RX_HPH_L_PA_CTL__POR (0x00000040) +#define TABLA_A_RX_HPH_L_DAC_CTL (0x01B1) +#define TABLA_A_RX_HPH_L_DAC_CTL__POR (0x00000000) +#define TABLA_A_RX_HPH_L_ATEST (0x01B2) +#define TABLA_A_RX_HPH_L_ATEST__POR (0x00000000) +#define TABLA_A_RX_HPH_L_STATUS (0x01B3) +#define TABLA_A_RX_HPH_L_STATUS__POR (0x00000004) +#define TABLA_A_RX_HPH_R_GAIN (0x01B4) +#define TABLA_A_RX_HPH_R_GAIN__POR (0x00000000) +#define TABLA_A_RX_HPH_R_TEST (0x01B5) +#define TABLA_A_RX_HPH_R_TEST__POR (0x00000001) +#define TABLA_A_RX_HPH_R_PA_CTL (0x01B6) +#define TABLA_A_RX_HPH_R_PA_CTL__POR (0x00000040) +#define TABLA_A_RX_HPH_R_DAC_CTL (0x01B7) +#define TABLA_A_RX_HPH_R_DAC_CTL__POR (0x00000000) +#define TABLA_A_RX_HPH_R_ATEST (0x01B8) +#define TABLA_A_RX_HPH_R_ATEST__POR (0x00000000) +#define TABLA_A_RX_HPH_R_STATUS (0x01B9) +#define TABLA_A_RX_HPH_R_STATUS__POR (0x00000004) +#define TABLA_A_RX_EAR_BIAS_PA (0x01BA) +#define TABLA_A_RX_EAR_BIAS_PA__POR (0x000000AA) +#define TABLA_A_RX_EAR_BIAS_CMBUFF (0x01BB) +#define TABLA_A_RX_EAR_BIAS_CMBUFF__POR (0x000000A0) +#define TABLA_A_RX_EAR_EN (0x01BC) +#define TABLA_A_RX_EAR_EN__POR (0x00000000) +#define TABLA_A_RX_EAR_GAIN (0x01BD) +#define TABLA_A_RX_EAR_GAIN__POR (0x00000008) +#define TABLA_A_RX_EAR_CMBUFF (0x01BE) +#define TABLA_A_RX_EAR_CMBUFF__POR (0x00000000) +#define TABLA_A_RX_EAR_ICTL (0x01BF) +#define TABLA_A_RX_EAR_ICTL__POR (0x00000040) +#define TABLA_A_RX_EAR_CCOMP (0x01C0) +#define TABLA_A_RX_EAR_CCOMP__POR (0x00000008) +#define TABLA_A_RX_EAR_VCM (0x01C1) +#define TABLA_A_RX_EAR_VCM__POR (0x00000000) +#define TABLA_A_RX_EAR_CNP (0x01C2) +#define TABLA_A_RX_EAR_CNP__POR (0x00000080) +#define TABLA_A_RX_EAR_ATEST (0x01C3) +#define TABLA_A_RX_EAR_ATEST__POR (0x00000000) +#define TABLA_A_RX_EAR_STATUS (0x01C5) +#define TABLA_A_RX_EAR_STATUS__POR (0x00000004) +#define TABLA_A_RX_LINE_BIAS_PA (0x01C6) +#define TABLA_A_RX_LINE_BIAS_PA__POR (0x000000AA) +#define TABLA_A_RX_LINE_BIAS_DAC (0x01C7) +#define TABLA_A_RX_LINE_BIAS_DAC__POR (0x000000A0) +#define TABLA_A_RX_LINE_BIAS_CNP (0x01C8) +#define TABLA_A_RX_LINE_BIAS_CNP__POR (0x0000003A) +#define TABLA_A_RX_LINE_COM (0x01C9) +#define TABLA_A_RX_LINE_COM__POR (0x00000000) +#define TABLA_A_RX_LINE_CNP_EN (0x01CA) +#define TABLA_A_RX_LINE_CNP_EN__POR (0x00000080) +#define TABLA_A_RX_LINE_CNP_WG_CTL (0x01CB) +#define TABLA_A_RX_LINE_CNP_WG_CTL__POR (0x0000001C) +#define TABLA_A_RX_LINE_CNP_WG_TIME (0x01CC) +#define TABLA_A_RX_LINE_CNP_WG_TIME__POR (0x00000064) +#define TABLA_A_RX_LINE_1_GAIN (0x01CD) +#define TABLA_A_RX_LINE_1_GAIN__POR (0x00000000) +#define TABLA_A_RX_LINE_1_TEST (0x01CE) +#define TABLA_A_RX_LINE_1_TEST__POR (0x00000000) +#define TABLA_A_RX_LINE_1_DAC_CTL (0x01CF) +#define TABLA_A_RX_LINE_1_DAC_CTL__POR (0x0000000C) +#define TABLA_A_RX_LINE_1_STATUS (0x01D0) +#define TABLA_A_RX_LINE_1_STATUS__POR (0x00000000) +#define TABLA_A_RX_LINE_2_GAIN (0x01D1) +#define TABLA_A_RX_LINE_2_GAIN__POR (0x00000000) +#define TABLA_A_RX_LINE_2_TEST (0x01D2) +#define TABLA_A_RX_LINE_2_TEST__POR (0x00000000) +#define TABLA_A_RX_LINE_2_DAC_CTL (0x01D3) +#define TABLA_A_RX_LINE_2_DAC_CTL__POR (0x0000000C) +#define TABLA_A_RX_LINE_2_STATUS (0x01D4) +#define TABLA_A_RX_LINE_2_STATUS__POR (0x00000000) +#define TABLA_A_RX_LINE_3_GAIN (0x01D5) +#define TABLA_A_RX_LINE_3_GAIN__POR (0x00000000) +#define TABLA_A_RX_LINE_3_TEST (0x01D6) +#define TABLA_A_RX_LINE_3_TEST__POR (0x00000000) +#define TABLA_A_RX_LINE_3_DAC_CTL (0x01D7) +#define TABLA_A_RX_LINE_3_DAC_CTL__POR (0x0000000C) +#define TABLA_A_RX_LINE_3_STATUS (0x01D8) +#define TABLA_A_RX_LINE_3_STATUS__POR (0x00000000) +#define TABLA_A_RX_LINE_4_GAIN (0x01D9) +#define TABLA_A_RX_LINE_4_GAIN__POR (0x00000000) +#define TABLA_A_RX_LINE_4_TEST (0x01DA) +#define TABLA_A_RX_LINE_4_TEST__POR (0x00000000) +#define TABLA_A_RX_LINE_4_DAC_CTL (0x01DB) +#define TABLA_A_RX_LINE_4_DAC_CTL__POR (0x0000000C) +#define TABLA_A_RX_LINE_4_STATUS (0x01DC) +#define TABLA_A_RX_LINE_4_STATUS__POR (0x00000000) +#define TABLA_A_RX_LINE_5_GAIN (0x01DD) +#define TABLA_A_RX_LINE_5_GAIN__POR (0x00000000) +#define TABLA_A_RX_LINE_5_TEST (0x01DE) +#define TABLA_A_RX_LINE_5_TEST__POR (0x00000000) +#define TABLA_A_RX_LINE_5_DAC_CTL (0x01DF) +#define TABLA_A_RX_LINE_5_DAC_CTL__POR (0x0000000C) +#define TABLA_A_RX_LINE_5_STATUS (0x01E0) +#define TABLA_A_RX_LINE_5_STATUS__POR (0x00000000) +#define TABLA_A_RX_LINE_CNP_DBG (0x01EC) +#define TABLA_A_RX_LINE_CNP_DBG__POR (0x00000000) +#define TABLA_A_MBHC_HPH (0x01ED) +#define TABLA_A_MBHC_HPH__POR (0x00000048) +#define TABLA_A_CONFIG_MODE_FREQ (0x01F7) +#define TABLA_A_CONFIG_MODE_FREQ__POR (0x00000047) +#define TABLA_A_CONFIG_MODE_TEST (0x01F8) +#define TABLA_A_CONFIG_MODE_TEST__POR (0x0000000A) +#define TABLA_A_CONFIG_MODE_STATUS (0x01F9) +#define TABLA_A_CONFIG_MODE_STATUS__POR (0x0000001C) +#define TABLA_A_CONFIG_MODE_TUNER (0x01FA) +#define TABLA_A_CONFIG_MODE_TUNER__POR (0x00000000) +#define TABLA_A_CDC_ANC1_CTL (0x00000200) +#define TABLA_A_CDC_ANC1_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_CTL (0x00000280) +#define TABLA_A_CDC_ANC2_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_SHIFT (0x00000201) +#define TABLA_A_CDC_ANC1_SHIFT__POR (0x00000000) +#define TABLA_A_CDC_ANC2_SHIFT (0x00000281) +#define TABLA_A_CDC_ANC2_SHIFT__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT1_B1_CTL (0x00000202) +#define TABLA_A_CDC_ANC1_FILT1_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT1_B1_CTL (0x00000282) +#define TABLA_A_CDC_ANC2_FILT1_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT1_B2_CTL (0x00000203) +#define TABLA_A_CDC_ANC1_FILT1_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT1_B2_CTL (0x00000283) +#define TABLA_A_CDC_ANC2_FILT1_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT1_B3_CTL (0x00000204) +#define TABLA_A_CDC_ANC1_FILT1_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT1_B3_CTL (0x00000284) +#define TABLA_A_CDC_ANC2_FILT1_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT1_B4_CTL (0x00000205) +#define TABLA_A_CDC_ANC1_FILT1_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT1_B4_CTL (0x00000285) +#define TABLA_A_CDC_ANC2_FILT1_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT2_B1_CTL (0x00000206) +#define TABLA_A_CDC_ANC1_FILT2_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT2_B1_CTL (0x00000286) +#define TABLA_A_CDC_ANC2_FILT2_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT2_B2_CTL (0x00000207) +#define TABLA_A_CDC_ANC1_FILT2_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT2_B2_CTL (0x00000287) +#define TABLA_A_CDC_ANC2_FILT2_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT2_B3_CTL (0x00000208) +#define TABLA_A_CDC_ANC1_FILT2_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT2_B3_CTL (0x00000288) +#define TABLA_A_CDC_ANC2_FILT2_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_SPARE (0x00000209) +#define TABLA_A_CDC_ANC1_SPARE__POR (0x00000000) +#define TABLA_A_CDC_ANC2_SPARE (0x00000289) +#define TABLA_A_CDC_ANC2_SPARE__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT3_CTL (0x0000020A) +#define TABLA_A_CDC_ANC1_FILT3_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT3_CTL (0x0000028A) +#define TABLA_A_CDC_ANC2_FILT3_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT4_CTL (0x0000020B) +#define TABLA_A_CDC_ANC1_FILT4_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT4_CTL (0x0000028B) +#define TABLA_A_CDC_ANC2_FILT4_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX1_VOL_CTL_TIMER (0x00000220) +#define TABLA_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX2_VOL_CTL_TIMER (0x00000228) +#define TABLA_A_CDC_TX2_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX3_VOL_CTL_TIMER (0x00000230) +#define TABLA_A_CDC_TX3_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX4_VOL_CTL_TIMER (0x00000238) +#define TABLA_A_CDC_TX4_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX5_VOL_CTL_TIMER (0x00000240) +#define TABLA_A_CDC_TX5_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX6_VOL_CTL_TIMER (0x00000248) +#define TABLA_A_CDC_TX6_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX7_VOL_CTL_TIMER (0x00000250) +#define TABLA_A_CDC_TX7_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX8_VOL_CTL_TIMER (0x00000258) +#define TABLA_A_CDC_TX8_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX9_VOL_CTL_TIMER (0x00000260) +#define TABLA_A_CDC_TX9_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX10_VOL_CTL_TIMER (0x00000268) +#define TABLA_A_CDC_TX10_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX1_VOL_CTL_GAIN (0x00000221) +#define TABLA_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX2_VOL_CTL_GAIN (0x00000229) +#define TABLA_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX3_VOL_CTL_GAIN (0x00000231) +#define TABLA_A_CDC_TX3_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX4_VOL_CTL_GAIN (0x00000239) +#define TABLA_A_CDC_TX4_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX5_VOL_CTL_GAIN (0x00000241) +#define TABLA_A_CDC_TX5_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX6_VOL_CTL_GAIN (0x00000249) +#define TABLA_A_CDC_TX6_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX7_VOL_CTL_GAIN (0x00000251) +#define TABLA_A_CDC_TX7_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX8_VOL_CTL_GAIN (0x00000259) +#define TABLA_A_CDC_TX8_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX9_VOL_CTL_GAIN (0x00000261) +#define TABLA_A_CDC_TX9_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX10_VOL_CTL_GAIN (0x00000269) +#define TABLA_A_CDC_TX10_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX1_VOL_CTL_CFG (0x00000222) +#define TABLA_A_CDC_TX1_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX2_VOL_CTL_CFG (0x0000022A) +#define TABLA_A_CDC_TX2_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX3_VOL_CTL_CFG (0x00000232) +#define TABLA_A_CDC_TX3_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX4_VOL_CTL_CFG (0x0000023A) +#define TABLA_A_CDC_TX4_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX5_VOL_CTL_CFG (0x00000242) +#define TABLA_A_CDC_TX5_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX6_VOL_CTL_CFG (0x0000024A) +#define TABLA_A_CDC_TX6_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX7_VOL_CTL_CFG (0x00000252) +#define TABLA_A_CDC_TX7_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX8_VOL_CTL_CFG (0x0000025A) +#define TABLA_A_CDC_TX8_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX9_VOL_CTL_CFG (0x00000262) +#define TABLA_A_CDC_TX9_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX10_VOL_CTL_CFG (0x0000026A) +#define TABLA_A_CDC_TX10_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX1_MUX_CTL (0x00000223) +#define TABLA_A_CDC_TX1_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX2_MUX_CTL (0x0000022B) +#define TABLA_A_CDC_TX2_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX3_MUX_CTL (0x00000233) +#define TABLA_A_CDC_TX3_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX4_MUX_CTL (0x0000023B) +#define TABLA_A_CDC_TX4_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX5_MUX_CTL (0x00000243) +#define TABLA_A_CDC_TX5_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX6_MUX_CTL (0x0000024B) +#define TABLA_A_CDC_TX6_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX7_MUX_CTL (0x00000253) +#define TABLA_A_CDC_TX7_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX8_MUX_CTL (0x0000025B) +#define TABLA_A_CDC_TX8_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX9_MUX_CTL (0x00000263) +#define TABLA_A_CDC_TX9_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX10_MUX_CTL (0x0000026B) +#define TABLA_A_CDC_TX10_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX1_CLK_FS_CTL (0x00000224) +#define TABLA_A_CDC_TX1_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX2_CLK_FS_CTL (0x0000022C) +#define TABLA_A_CDC_TX2_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX3_CLK_FS_CTL (0x00000234) +#define TABLA_A_CDC_TX3_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX4_CLK_FS_CTL (0x0000023C) +#define TABLA_A_CDC_TX4_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX5_CLK_FS_CTL (0x00000244) +#define TABLA_A_CDC_TX5_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX6_CLK_FS_CTL (0x0000024C) +#define TABLA_A_CDC_TX6_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX7_CLK_FS_CTL (0x00000254) +#define TABLA_A_CDC_TX7_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX8_CLK_FS_CTL (0x0000025C) +#define TABLA_A_CDC_TX8_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX9_CLK_FS_CTL (0x00000264) +#define TABLA_A_CDC_TX9_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX10_CLK_FS_CTL (0x0000026C) +#define TABLA_A_CDC_TX10_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX1_DMIC_CTL (0x00000225) +#define TABLA_A_CDC_TX1_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX2_DMIC_CTL (0x0000022D) +#define TABLA_A_CDC_TX2_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX3_DMIC_CTL (0x00000235) +#define TABLA_A_CDC_TX3_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX4_DMIC_CTL (0x0000023D) +#define TABLA_A_CDC_TX4_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX5_DMIC_CTL (0x00000245) +#define TABLA_A_CDC_TX5_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX6_DMIC_CTL (0x0000024D) +#define TABLA_A_CDC_TX6_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX7_DMIC_CTL (0x00000255) +#define TABLA_A_CDC_TX7_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX8_DMIC_CTL (0x0000025D) +#define TABLA_A_CDC_TX8_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX9_DMIC_CTL (0x00000265) +#define TABLA_A_CDC_TX9_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX10_DMIC_CTL (0x0000026D) +#define TABLA_A_CDC_TX10_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_SRC1_PDA_CFG (0x000002A0) +#define TABLA_A_CDC_SRC1_PDA_CFG__POR (0x00000000) +#define TABLA_A_CDC_SRC2_PDA_CFG (0x000002A8) +#define TABLA_A_CDC_SRC2_PDA_CFG__POR (0x00000000) +#define TABLA_A_CDC_SRC1_FS_CTL (0x000002A1) +#define TABLA_A_CDC_SRC1_FS_CTL__POR (0x0000001b) +#define TABLA_A_CDC_SRC2_FS_CTL (0x000002A9) +#define TABLA_A_CDC_SRC2_FS_CTL__POR (0x0000001b) +#define TABLA_A_CDC_RX1_B1_CTL (0x000002B0) +#define TABLA_A_CDC_RX1_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX2_B1_CTL (0x000002B8) +#define TABLA_A_CDC_RX2_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_B1_CTL (0x000002C0) +#define TABLA_A_CDC_RX3_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX4_B1_CTL (0x000002C8) +#define TABLA_A_CDC_RX4_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_B1_CTL (0x000002D0) +#define TABLA_A_CDC_RX5_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX6_B1_CTL (0x000002D8) +#define TABLA_A_CDC_RX6_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_B1_CTL (0x000002E0) +#define TABLA_A_CDC_RX7_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX1_B2_CTL (0x000002B1) +#define TABLA_A_CDC_RX1_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX2_B2_CTL (0x000002B9) +#define TABLA_A_CDC_RX2_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_B2_CTL (0x000002C1) +#define TABLA_A_CDC_RX3_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX4_B2_CTL (0x000002C9) +#define TABLA_A_CDC_RX4_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_B2_CTL (0x000002D1) +#define TABLA_A_CDC_RX5_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX6_B2_CTL (0x000002D9) +#define TABLA_A_CDC_RX6_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_B2_CTL (0x000002E1) +#define TABLA_A_CDC_RX7_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX1_B3_CTL (0x000002B2) +#define TABLA_A_CDC_RX1_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX2_B3_CTL (0x000002BA) +#define TABLA_A_CDC_RX2_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_B3_CTL (0x000002C2) +#define TABLA_A_CDC_RX3_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX4_B3_CTL (0x000002CA) +#define TABLA_A_CDC_RX4_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_B3_CTL (0x000002D2) +#define TABLA_A_CDC_RX5_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX6_B3_CTL (0x000002DA) +#define TABLA_A_CDC_RX6_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_B3_CTL (0x000002E2) +#define TABLA_A_CDC_RX7_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX1_B4_CTL (0x000002B3) +#define TABLA_A_CDC_RX1_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX2_B4_CTL (0x000002BB) +#define TABLA_A_CDC_RX2_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_B4_CTL (0x000002C3) +#define TABLA_A_CDC_RX3_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX4_B4_CTL (0x000002CB) +#define TABLA_A_CDC_RX4_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_B4_CTL (0x000002D3) +#define TABLA_A_CDC_RX5_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX6_B4_CTL (0x000002DB) +#define TABLA_A_CDC_RX6_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_B4_CTL (0x000002E3) +#define TABLA_A_CDC_RX7_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX1_B5_CTL (0x000002B4) +#define TABLA_A_CDC_RX1_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX2_B5_CTL (0x000002BC) +#define TABLA_A_CDC_RX2_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX3_B5_CTL (0x000002C4) +#define TABLA_A_CDC_RX3_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX4_B5_CTL (0x000002CC) +#define TABLA_A_CDC_RX4_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX5_B5_CTL (0x000002D4) +#define TABLA_A_CDC_RX5_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX6_B5_CTL (0x000002DC) +#define TABLA_A_CDC_RX6_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX7_B5_CTL (0x000002E4) +#define TABLA_A_CDC_RX7_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX1_B6_CTL (0x000002B5) +#define TABLA_A_CDC_RX1_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX2_B6_CTL (0x000002BD) +#define TABLA_A_CDC_RX2_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_B6_CTL (0x000002C5) +#define TABLA_A_CDC_RX3_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX4_B6_CTL (0x000002CD) +#define TABLA_A_CDC_RX4_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_B6_CTL (0x000002D5) +#define TABLA_A_CDC_RX5_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX6_B6_CTL (0x000002DD) +#define TABLA_A_CDC_RX6_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_B6_CTL (0x000002E5) +#define TABLA_A_CDC_RX7_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX1_VOL_CTL_B1_CTL (0x000002B6) +#define TABLA_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX2_VOL_CTL_B1_CTL (0x000002BE) +#define TABLA_A_CDC_RX2_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_VOL_CTL_B1_CTL (0x000002C6) +#define TABLA_A_CDC_RX3_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX4_VOL_CTL_B1_CTL (0x000002CE) +#define TABLA_A_CDC_RX4_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_VOL_CTL_B1_CTL (0x000002D6) +#define TABLA_A_CDC_RX5_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX6_VOL_CTL_B1_CTL (0x000002DE) +#define TABLA_A_CDC_RX6_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_VOL_CTL_B1_CTL (0x000002E6) +#define TABLA_A_CDC_RX7_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX1_VOL_CTL_B2_CTL (0x000002B7) +#define TABLA_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX2_VOL_CTL_B2_CTL (0x000002BF) +#define TABLA_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_VOL_CTL_B2_CTL (0x000002C7) +#define TABLA_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX4_VOL_CTL_B2_CTL (0x000002CF) +#define TABLA_A_CDC_RX4_VOL_CTL_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_VOL_CTL_B2_CTL (0x000002D7) +#define TABLA_A_CDC_RX5_VOL_CTL_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX6_VOL_CTL_B2_CTL (0x000002DF) +#define TABLA_A_CDC_RX6_VOL_CTL_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_VOL_CTL_B2_CTL (0x000002E7) +#define TABLA_A_CDC_RX7_VOL_CTL_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_ANC_RESET_CTL (0x00000300) +#define TABLA_A_CDC_CLK_ANC_RESET_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_RX_RESET_CTL (0x00000301) +#define TABLA_A_CDC_CLK_RX_RESET_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_TX_RESET_B1_CTL (0x00000302) +#define TABLA_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_TX_RESET_B2_CTL (0x00000303) +#define TABLA_A_CDC_CLK_TX_RESET_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_DMIC_CTL (0x00000304) +#define TABLA_A_CDC_CLK_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_RX_I2S_CTL (0x00000305) +#define TABLA_A_CDC_CLK_RX_I2S_CTL__POR (0x00000003) +#define TABLA_A_CDC_CLK_TX_I2S_CTL (0x00000306) +#define TABLA_A_CDC_CLK_TX_I2S_CTL__POR (0x00000003) +#define TABLA_A_CDC_CLK_OTHR_RESET_CTL (0x00000307) +#define TABLA_A_CDC_CLK_OTHR_RESET_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x00000308) +#define TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_TX_CLK_EN_B2_CTL (0x00000309) +#define TABLA_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_OTHR_CTL (0x0000030A) +#define TABLA_A_CDC_CLK_OTHR_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_RDAC_CLK_EN_CTL (0x0000030B) +#define TABLA_A_CDC_CLK_RDAC_CLK_EN_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_ANC_CLK_EN_CTL (0x0000030C) +#define TABLA_A_CDC_CLK_ANC_CLK_EN_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_RX_B1_CTL (0x0000030D) +#define TABLA_A_CDC_CLK_RX_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_RX_B2_CTL (0x0000030E) +#define TABLA_A_CDC_CLK_RX_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_MCLK_CTL (0x0000030F) +#define TABLA_A_CDC_CLK_MCLK_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_PDM_CTL (0x00000310) +#define TABLA_A_CDC_CLK_PDM_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_SD_CTL (0x00000311) +#define TABLA_A_CDC_CLK_SD_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B1_CTL (0x00000320) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B1_CTL__POR (0x00000007) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B2_CTL (0x00000321) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B2_CTL__POR (0x00000013) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B3_CTL (0x00000322) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B3_CTL__POR (0x00000053) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B4_CTL (0x00000323) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B4_CTL__POR (0x0000007f) +#define TABLA_A_CDC_CLSG_GAIN_THRESH_CTL (0x00000324) +#define TABLA_A_CDC_CLSG_GAIN_THRESH_CTL__POR (0x00000026) +#define TABLA_A_CDC_CLSG_TIMER_B1_CFG (0x00000325) +#define TABLA_A_CDC_CLSG_TIMER_B1_CFG__POR (0x0000000a) +#define TABLA_A_CDC_CLSG_TIMER_B2_CFG (0x00000326) +#define TABLA_A_CDC_CLSG_TIMER_B2_CFG__POR (0x00000000) +#define TABLA_A_CDC_CLSG_CTL (0x00000327) +#define TABLA_A_CDC_CLSG_CTL__POR (0x00000013) +#define TABLA_A_CDC_IIR1_GAIN_B1_CTL (0x00000340) +#define TABLA_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B1_CTL (0x00000350) +#define TABLA_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_GAIN_B2_CTL (0x00000341) +#define TABLA_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B2_CTL (0x00000351) +#define TABLA_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_GAIN_B3_CTL (0x00000342) +#define TABLA_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B3_CTL (0x00000352) +#define TABLA_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_GAIN_B4_CTL (0x00000343) +#define TABLA_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B4_CTL (0x00000353) +#define TABLA_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_GAIN_B5_CTL (0x00000344) +#define TABLA_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B5_CTL (0x00000354) +#define TABLA_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_GAIN_B6_CTL (0x00000345) +#define TABLA_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B6_CTL (0x00000355) +#define TABLA_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_GAIN_B7_CTL (0x00000346) +#define TABLA_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B7_CTL (0x00000356) +#define TABLA_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_GAIN_B8_CTL (0x00000347) +#define TABLA_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B8_CTL (0x00000357) +#define TABLA_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_CTL (0x00000348) +#define TABLA_A_CDC_IIR1_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_CTL (0x00000358) +#define TABLA_A_CDC_IIR2_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_GAIN_TIMER_CTL (0x00000349) +#define TABLA_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_TIMER_CTL (0x00000359) +#define TABLA_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_COEF_B1_CTL (0x0000034A) +#define TABLA_A_CDC_IIR1_COEF_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_COEF_B1_CTL (0x0000035A) +#define TABLA_A_CDC_IIR2_COEF_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_COEF_B2_CTL (0x0000034B) +#define TABLA_A_CDC_IIR1_COEF_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_COEF_B2_CTL (0x0000035B) +#define TABLA_A_CDC_IIR2_COEF_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_COEF_B3_CTL (0x0000034C) +#define TABLA_A_CDC_IIR1_COEF_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_COEF_B3_CTL (0x0000035C) +#define TABLA_A_CDC_IIR2_COEF_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_COEF_B4_CTL (0x0000034D) +#define TABLA_A_CDC_IIR1_COEF_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_COEF_B4_CTL (0x0000035D) +#define TABLA_A_CDC_IIR2_COEF_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_COEF_B5_CTL (0x0000034E) +#define TABLA_A_CDC_IIR1_COEF_B5_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_COEF_B5_CTL (0x0000035E) +#define TABLA_A_CDC_IIR2_COEF_B5_CTL__POR (0x00000000) +#define TABLA_A_CDC_TOP_GAIN_UPDATE (0x00000360) +#define TABLA_A_CDC_TOP_GAIN_UPDATE__POR (0x00000000) +#define TABLA_A_CDC_DEBUG_B1_CTL (0x00000368) +#define TABLA_A_CDC_DEBUG_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_DEBUG_B2_CTL (0x00000369) +#define TABLA_A_CDC_DEBUG_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_DEBUG_B3_CTL (0x0000036A) +#define TABLA_A_CDC_DEBUG_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_DEBUG_B4_CTL (0x0000036B) +#define TABLA_A_CDC_DEBUG_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_DEBUG_B5_CTL (0x0000036C) +#define TABLA_A_CDC_DEBUG_B5_CTL__POR (0x00000000) +#define TABLA_A_CDC_DEBUG_B6_CTL (0x0000036D) +#define TABLA_A_CDC_DEBUG_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_COMP1_B1_CTL (0x00000370) +#define TABLA_A_CDC_COMP1_B1_CTL__POR (0x00000030) +#define TABLA_A_CDC_COMP1_B2_CTL (0x00000371) +#define TABLA_A_CDC_COMP1_B2_CTL__POR (0x000000B5) +#define TABLA_A_CDC_COMP1_B3_CTL (0x00000372) +#define TABLA_A_CDC_COMP1_B3_CTL__POR (0x00000028) +#define TABLA_A_CDC_COMP1_B4_CTL (0x00000373) +#define TABLA_A_CDC_COMP1_B4_CTL__POR (0x0000003C) +#define TABLA_A_CDC_COMP1_B5_CTL (0x00000374) +#define TABLA_A_CDC_COMP1_B5_CTL__POR (0x0000001F) +#define TABLA_A_CDC_COMP1_B6_CTL (0x00000375) +#define TABLA_A_CDC_COMP1_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_COMP1_SHUT_DOWN_STATUS (0x00000376) +#define TABLA_A_CDC_COMP1_SHUT_DOWN_STATUS__POR (0x00000000) +#define TABLA_A_CDC_COMP1_FS_CFG (0x00000377) +#define TABLA_A_CDC_COMP1_FS_CFG__POR (0x0000001B) +#define TABLA_A_CDC_COMP2_B1_CTL (0x00000378) +#define TABLA_A_CDC_COMP2_B1_CTL__POR (0x00000030) +#define TABLA_A_CDC_COMP2_B2_CTL (0x00000379) +#define TABLA_A_CDC_COMP2_B2_CTL__POR (0x000000B5) +#define TABLA_A_CDC_COMP2_B3_CTL (0x0000037A) +#define TABLA_A_CDC_COMP2_B3_CTL__POR (0x00000028) +#define TABLA_A_CDC_COMP2_B4_CTL (0x0000037B) +#define TABLA_A_CDC_COMP2_B4_CTL__POR (0x0000003C) +#define TABLA_A_CDC_COMP2_B5_CTL (0x0000037C) +#define TABLA_A_CDC_COMP2_B5_CTL__POR (0x0000001F) +#define TABLA_A_CDC_COMP2_B6_CTL (0x0000037D) +#define TABLA_A_CDC_COMP2_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_COMP2_SHUT_DOWN_STATUS (0x0000037E) +#define TABLA_A_CDC_COMP2_SHUT_DOWN_STATUS__POR (0x00000000) +#define TABLA_A_CDC_COMP2_FS_CFG (0x0000037F) +#define TABLA_A_CDC_COMP2_FS_CFG__POR (0x0000001B) +#define TABLA_A_CDC_CONN_RX1_B1_CTL (0x00000380) +#define TABLA_A_CDC_CONN_RX1_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX1_B2_CTL (0x00000381) +#define TABLA_A_CDC_CONN_RX1_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX1_B3_CTL (0x00000382) +#define TABLA_A_CDC_CONN_RX1_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX2_B1_CTL (0x00000383) +#define TABLA_A_CDC_CONN_RX2_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX2_B2_CTL (0x00000384) +#define TABLA_A_CDC_CONN_RX2_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX2_B3_CTL (0x00000385) +#define TABLA_A_CDC_CONN_RX2_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX3_B1_CTL (0x00000386) +#define TABLA_A_CDC_CONN_RX3_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX3_B2_CTL (0x00000387) +#define TABLA_A_CDC_CONN_RX3_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX3_B3_CTL (0x00000388) +#define TABLA_A_CDC_CONN_RX3_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX4_B1_CTL (0x00000389) +#define TABLA_A_CDC_CONN_RX4_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX4_B2_CTL (0x0000038A) +#define TABLA_A_CDC_CONN_RX4_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX5_B1_CTL (0x0000038B) +#define TABLA_A_CDC_CONN_RX5_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX5_B2_CTL (0x0000038C) +#define TABLA_A_CDC_CONN_RX5_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX6_B1_CTL (0x0000038D) +#define TABLA_A_CDC_CONN_RX6_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX6_B2_CTL (0x0000038E) +#define TABLA_A_CDC_CONN_RX6_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX7_B1_CTL (0x0000038F) +#define TABLA_A_CDC_CONN_RX7_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX7_B2_CTL (0x00000390) +#define TABLA_A_CDC_CONN_RX7_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_ANC_B1_CTL (0x00000391) +#define TABLA_A_CDC_CONN_ANC_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_ANC_B2_CTL (0x00000392) +#define TABLA_A_CDC_CONN_ANC_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_B1_CTL (0x00000393) +#define TABLA_A_CDC_CONN_TX_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_B2_CTL (0x00000394) +#define TABLA_A_CDC_CONN_TX_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_B3_CTL (0x00000395) +#define TABLA_A_CDC_CONN_TX_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_B4_CTL (0x00000396) +#define TABLA_A_CDC_CONN_TX_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ1_B1_CTL (0x00000397) +#define TABLA_A_CDC_CONN_EQ1_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ1_B2_CTL (0x00000398) +#define TABLA_A_CDC_CONN_EQ1_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ1_B3_CTL (0x00000399) +#define TABLA_A_CDC_CONN_EQ1_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ1_B4_CTL (0x0000039A) +#define TABLA_A_CDC_CONN_EQ1_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ2_B1_CTL (0x0000039B) +#define TABLA_A_CDC_CONN_EQ2_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ2_B2_CTL (0x0000039C) +#define TABLA_A_CDC_CONN_EQ2_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ2_B3_CTL (0x0000039D) +#define TABLA_A_CDC_CONN_EQ2_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ2_B4_CTL (0x0000039E) +#define TABLA_A_CDC_CONN_EQ2_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_SRC1_B1_CTL (0x0000039F) +#define TABLA_A_CDC_CONN_SRC1_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_SRC1_B2_CTL (0x000003A0) +#define TABLA_A_CDC_CONN_SRC1_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_SRC2_B1_CTL (0x000003A1) +#define TABLA_A_CDC_CONN_SRC2_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_SRC2_B2_CTL (0x000003A2) +#define TABLA_A_CDC_CONN_SRC2_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B1_CTL (0x000003A3) +#define TABLA_A_CDC_CONN_TX_SB_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B2_CTL (0x000003A4) +#define TABLA_A_CDC_CONN_TX_SB_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B3_CTL (0x000003A5) +#define TABLA_A_CDC_CONN_TX_SB_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B4_CTL (0x000003A6) +#define TABLA_A_CDC_CONN_TX_SB_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B5_CTL (0x000003A7) +#define TABLA_A_CDC_CONN_TX_SB_B5_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B6_CTL (0x000003A8) +#define TABLA_A_CDC_CONN_TX_SB_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B7_CTL (0x000003A9) +#define TABLA_A_CDC_CONN_TX_SB_B7_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B8_CTL (0x000003AA) +#define TABLA_A_CDC_CONN_TX_SB_B8_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B9_CTL (0x000003AB) +#define TABLA_A_CDC_CONN_TX_SB_B9_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B10_CTL (0x000003AC) +#define TABLA_A_CDC_CONN_TX_SB_B10_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B11_CTL (0x000003AD) +#define TABLA_A_CDC_CONN_TX_SB_B11_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX_SB_B1_CTL (0x000003AE) +#define TABLA_A_CDC_CONN_RX_SB_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX_SB_B2_CTL (0x000003AF) +#define TABLA_A_CDC_CONN_RX_SB_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_CLSG_CTL (0x000003B0) +#define TABLA_A_CDC_CONN_CLSG_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_SPARE (0x000003B1) +#define TABLA_A_CDC_CONN_SPARE__POR (0x00000000) +#define TABLA_A_CDC_MBHC_EN_CTL (0x000003C0) +#define TABLA_A_CDC_MBHC_EN_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_FEATURE_B1_CFG (0x000003C1) +#define TABLA_A_CDC_MBHC_FEATURE_B1_CFG__POR (0x00000000) +#define TABLA_A_CDC_MBHC_FEATURE_B2_CFG (0x000003C2) +#define TABLA_A_CDC_MBHC_FEATURE_B2_CFG__POR (0x00000006) +#define TABLA_A_CDC_MBHC_TIMER_B1_CTL (0x000003C3) +#define TABLA_A_CDC_MBHC_TIMER_B1_CTL__POR (0x00000003) +#define TABLA_A_CDC_MBHC_TIMER_B2_CTL (0x000003C4) +#define TABLA_A_CDC_MBHC_TIMER_B2_CTL__POR (0x00000009) +#define TABLA_A_CDC_MBHC_TIMER_B3_CTL (0x000003C5) +#define TABLA_A_CDC_MBHC_TIMER_B3_CTL__POR (0x0000001e) +#define TABLA_A_CDC_MBHC_TIMER_B4_CTL (0x000003C6) +#define TABLA_A_CDC_MBHC_TIMER_B4_CTL__POR (0x00000045) +#define TABLA_A_CDC_MBHC_TIMER_B5_CTL (0x000003C7) +#define TABLA_A_CDC_MBHC_TIMER_B5_CTL__POR (0x00000004) +#define TABLA_A_CDC_MBHC_TIMER_B6_CTL (0x000003C8) +#define TABLA_A_CDC_MBHC_TIMER_B6_CTL__POR (0x00000078) +#define TABLA_A_CDC_MBHC_B1_STATUS (0x000003C9) +#define TABLA_A_CDC_MBHC_B1_STATUS__POR (0x00000000) +#define TABLA_A_CDC_MBHC_B2_STATUS (0x000003CA) +#define TABLA_A_CDC_MBHC_B2_STATUS__POR (0x00000000) +#define TABLA_A_CDC_MBHC_B3_STATUS (0x000003CB) +#define TABLA_A_CDC_MBHC_B3_STATUS__POR (0x00000000) +#define TABLA_A_CDC_MBHC_B4_STATUS (0x000003CC) +#define TABLA_A_CDC_MBHC_B4_STATUS__POR (0x00000000) +#define TABLA_A_CDC_MBHC_B5_STATUS (0x000003CD) +#define TABLA_A_CDC_MBHC_B5_STATUS__POR (0x00000000) +#define TABLA_A_CDC_MBHC_B1_CTL (0x000003CE) +#define TABLA_A_CDC_MBHC_B1_CTL__POR (0x000000c0) +#define TABLA_A_CDC_MBHC_B2_CTL (0x000003CF) +#define TABLA_A_CDC_MBHC_B2_CTL__POR (0x0000005d) +#define TABLA_A_CDC_MBHC_VOLT_B1_CTL (0x000003D0) +#define TABLA_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_VOLT_B2_CTL (0x000003D1) +#define TABLA_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_VOLT_B3_CTL (0x000003D2) +#define TABLA_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_VOLT_B4_CTL (0x000003D3) +#define TABLA_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_VOLT_B5_CTL (0x000003D4) +#define TABLA_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_VOLT_B6_CTL (0x000003D5) +#define TABLA_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_VOLT_B7_CTL (0x000003D6) +#define TABLA_A_CDC_MBHC_VOLT_B7_CTL__POR (0x000000ff) +#define TABLA_A_CDC_MBHC_VOLT_B8_CTL (0x000003D7) +#define TABLA_A_CDC_MBHC_VOLT_B8_CTL__POR (0x00000007) +#define TABLA_A_CDC_MBHC_VOLT_B9_CTL (0x000003D8) +#define TABLA_A_CDC_MBHC_VOLT_B9_CTL__POR (0x000000ff) +#define TABLA_A_CDC_MBHC_VOLT_B10_CTL (0x000003D9) +#define TABLA_A_CDC_MBHC_VOLT_B10_CTL__POR (0x0000007f) +#define TABLA_A_CDC_MBHC_VOLT_B11_CTL (0x000003DA) +#define TABLA_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_VOLT_B12_CTL (0x000003DB) +#define TABLA_A_CDC_MBHC_VOLT_B12_CTL__POR (0x00000080) +#define TABLA_A_CDC_MBHC_CLK_CTL (0x000003DC) +#define TABLA_A_CDC_MBHC_CLK_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_INT_CTL (0x000003DD) +#define TABLA_A_CDC_MBHC_INT_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_DEBUG_CTL (0x000003DE) +#define TABLA_A_CDC_MBHC_DEBUG_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_SPARE (0x000003DF) +#define TABLA_A_CDC_MBHC_SPARE__POR (0x00000000) + + +/* SLIMBUS Slave Registers */ +#define TABLA_SLIM_PGD_PORT_INT_EN0 (0x30) +#define TABLA_SLIM_PGD_PORT_INT_STATUS0 (0x34) +#define TABLA_SLIM_PGD_PORT_INT_CLR0 (0x38) +#define TABLA_SLIM_PGD_PORT_INT_SOURCE0 (0x60) + +/* Macros for Packing Register Writes into a U32 */ +#define TABLA_PACKED_REG_SIZE sizeof(u32) + +#define TABLA_CODEC_PACK_ENTRY(reg, mask, val) ((val & 0xff)|\ + ((mask & 0xff) << 8)|((reg & 0xffff) << 16)) + +#define TABLA_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \ + do { \ + ((reg) = ((packed >> 16) & (0xffff))); \ + ((mask) = ((packed >> 8) & (0xff))); \ + ((val) = ((packed) & (0xff))); \ + } while (0); + +#endif diff --git a/include/linux/mfd/wcd9xxx/wcd9330_registers.h b/include/linux/mfd/wcd9xxx/wcd9330_registers.h new file mode 100755 index 000000000000..c37d25f3f528 --- /dev/null +++ b/include/linux/mfd/wcd9xxx/wcd9330_registers.h @@ -0,0 +1,1626 @@ +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef WCD9330_REGISTERS_H +#define WCD9330_REGISTERS_H + +#include <linux/types.h> + +#define TOMTOM_A_CHIP_CTL (0x000) +#define TOMTOM_A_CHIP_CTL__POR (0x38) +#define TOMTOM_A_CHIP_STATUS (0x001) +#define TOMTOM_A_CHIP_STATUS__POR (0x00) +#define TOMTOM_A_CHIP_ID_BYTE_0 (0x004) +#define TOMTOM_A_CHIP_ID_BYTE_0__POR (0x00) +#define TOMTOM_A_CHIP_ID_BYTE_1 (0x005) +#define TOMTOM_A_CHIP_ID_BYTE_1__POR (0x00) +#define TOMTOM_A_CHIP_ID_BYTE_2 (0x006) +#define TOMTOM_A_CHIP_ID_BYTE_2__POR (0x05) +#define TOMTOM_A_CHIP_ID_BYTE_3 (0x007) +#define TOMTOM_A_CHIP_ID_BYTE_3__POR (0x01) +#define TOMTOM_A_CHIP_I2C_SLAVE_ID (0x008) +#define TOMTOM_A_CHIP_I2C_SLAVE_ID__POR (0x01) +#define TOMTOM_A_SLAVE_ID_1 (0x00C) +#define TOMTOM_A_SLAVE_ID_1__POR (0x77) +#define TOMTOM_A_SLAVE_ID_2 (0x00D) +#define TOMTOM_A_SLAVE_ID_2__POR (0x66) +#define TOMTOM_A_SLAVE_ID_3 (0x00E) +#define TOMTOM_A_SLAVE_ID_3__POR (0x55) +#define TOMTOM_A_PIN_CTL_OE0 (0x010) +#define TOMTOM_A_PIN_CTL_OE0__POR (0x00) +#define TOMTOM_A_PIN_CTL_OE1 (0x011) +#define TOMTOM_A_PIN_CTL_OE1__POR (0x00) +#define TOMTOM_A_PIN_CTL_OE2 (0x012) +#define TOMTOM_A_PIN_CTL_OE2__POR (0x00) +#define TOMTOM_A_PIN_CTL_DATA0 (0x013) +#define TOMTOM_A_PIN_CTL_DATA0__POR (0x00) +#define TOMTOM_A_PIN_CTL_DATA1 (0x014) +#define TOMTOM_A_PIN_CTL_DATA1__POR (0x00) +#define TOMTOM_A_PIN_CTL_DATA2 (0x015) +#define TOMTOM_A_PIN_CTL_DATA2__POR (0x00) +#define TOMTOM_A_HDRIVE_GENERIC (0x018) +#define TOMTOM_A_HDRIVE_GENERIC__POR (0x00) +#define TOMTOM_A_HDRIVE_OVERRIDE (0x019) +#define TOMTOM_A_HDRIVE_OVERRIDE__POR (0x08) +#define TOMTOM_A_ANA_CSR_WAIT_STATE (0x01C) +#define TOMTOM_A_ANA_CSR_WAIT_STATE__POR (0x44) +#define TOMTOM_A_PROCESS_MONITOR_CTL0 (0x020) +#define TOMTOM_A_PROCESS_MONITOR_CTL0__POR (0x80) +#define TOMTOM_A_PROCESS_MONITOR_CTL1 (0x021) +#define TOMTOM_A_PROCESS_MONITOR_CTL1__POR (0x00) +#define TOMTOM_A_PROCESS_MONITOR_CTL2 (0x022) +#define TOMTOM_A_PROCESS_MONITOR_CTL2__POR (0x00) +#define TOMTOM_A_PROCESS_MONITOR_CTL3 (0x023) +#define TOMTOM_A_PROCESS_MONITOR_CTL3__POR (0x01) +#define TOMTOM_A_QFUSE_CTL (0x028) +#define TOMTOM_A_QFUSE_CTL__POR (0x00) +#define TOMTOM_A_QFUSE_STATUS (0x029) +#define TOMTOM_A_QFUSE_STATUS__POR (0x00) +#define TOMTOM_A_QFUSE_DATA_OUT0 (0x02A) +#define TOMTOM_A_QFUSE_DATA_OUT0__POR (0x00) +#define TOMTOM_A_QFUSE_DATA_OUT1 (0x02B) +#define TOMTOM_A_QFUSE_DATA_OUT1__POR (0x00) +#define TOMTOM_A_QFUSE_DATA_OUT2 (0x02C) +#define TOMTOM_A_QFUSE_DATA_OUT2__POR (0x00) +#define TOMTOM_A_QFUSE_DATA_OUT3 (0x02D) +#define TOMTOM_A_QFUSE_DATA_OUT3__POR (0x00) +#define TOMTOM_A_QFUSE_DATA_OUT4 (0x02E) +#define TOMTOM_A_QFUSE_DATA_OUT4__POR (0x00) +#define TOMTOM_A_QFUSE_DATA_OUT5 (0x02F) +#define TOMTOM_A_QFUSE_DATA_OUT5__POR (0x00) +#define TOMTOM_A_QFUSE_DATA_OUT6 (0x030) +#define TOMTOM_A_QFUSE_DATA_OUT6__POR (0x00) +#define TOMTOM_A_QFUSE_DATA_OUT7 (0x031) +#define TOMTOM_A_QFUSE_DATA_OUT7__POR (0x00) +#define TOMTOM_A_CDC_CTL (0x034) +#define TOMTOM_A_CDC_CTL__POR (0x00) +#define TOMTOM_A_LEAKAGE_CTL (0x03C) +#define TOMTOM_A_LEAKAGE_CTL__POR (0x04) +#define TOMTOM_A_SVASS_MEM_PTR0 (0x044) +#define TOMTOM_A_SVASS_MEM_PTR0__POR (0x00) +#define TOMTOM_A_SVASS_MEM_PTR1 (0x045) +#define TOMTOM_A_SVASS_MEM_PTR1__POR (0x00) +#define TOMTOM_A_SVASS_MEM_PTR2 (0x046) +#define TOMTOM_A_SVASS_MEM_PTR2__POR (0x00) +#define TOMTOM_A_SVASS_MEM_CTL (0x048) +#define TOMTOM_A_SVASS_MEM_CTL__POR (0x04) +#define TOMTOM_A_SVASS_MEM_BANK (0x049) +#define TOMTOM_A_SVASS_MEM_BANK__POR (0x00) +#define TOMTOM_A_DMIC_B1_CTL (0x04A) +#define TOMTOM_A_DMIC_B1_CTL__POR (0x00) +#define TOMTOM_A_DMIC_B2_CTL (0x04B) +#define TOMTOM_A_DMIC_B2_CTL__POR (0x00) +#define TOMTOM_A_SVASS_CLKRST_CTL (0x04C) +#define TOMTOM_A_SVASS_CLKRST_CTL__POR (0x00) +#define TOMTOM_A_SVASS_CPAR_CFG (0x04D) +#define TOMTOM_A_SVASS_CPAR_CFG__POR (0x00) +#define TOMTOM_A_SVASS_BUF_RDY_INT_PERIOD (0x04E) +#define TOMTOM_A_SVASS_BUF_RDY_INT_PERIOD__POR (0x14) +#define TOMTOM_A_SVASS_CPAR_WDOG_CFG (0x04F) +#define TOMTOM_A_SVASS_CPAR_WDOG_CFG__POR (0x00) +#define TOMTOM_A_SVASS_CFG (0x050) +#define TOMTOM_A_SVASS_CFG__POR (0x01) +#define TOMTOM_A_SVASS_SPE_CFG (0x051) +#define TOMTOM_A_SVASS_SPE_CFG__POR (0x04) +#define TOMTOM_A_SVASS_STATUS (0x052) +#define TOMTOM_A_SVASS_STATUS__POR (0x00) +#define TOMTOM_A_SVASS_INT_MASK (0x053) +#define TOMTOM_A_SVASS_INT_MASK__POR (0x3F) +#define TOMTOM_A_SVASS_INT_STATUS (0x054) +#define TOMTOM_A_SVASS_INT_STATUS__POR (0x00) +#define TOMTOM_A_SVASS_INT_CLR (0x055) +#define TOMTOM_A_SVASS_INT_CLR__POR (0x00) +#define TOMTOM_A_SVASS_DEBUG (0x056) +#define TOMTOM_A_SVASS_DEBUG__POR (0x00) +#define TOMTOM_A_SVASS_SPE_BKUP_INT (0x057) +#define TOMTOM_A_SVASS_SPE_BKUP_INT__POR (0x00) +#define TOMTOM_A_SVASS_MEM_ACC (0x058) +#define TOMTOM_A_SVASS_MEM_ACC__POR (0x00) +#define TOMTOM_A_MEM_LEAKAGE_CTL (0x059) +#define TOMTOM_A_MEM_LEAKAGE_CTL__POR (0x04) +#define TOMTOM_A_SVASS_SPE_INBOX_TRG (0x05A) +#define TOMTOM_A_SVASS_SPE_INBOX_TRG__POR (0x00) +#define TOMTOM_A_SVASS_SPE_INBOX_0 (0x060) +#define TOMTOM_A_SVASS_SPE_INBOX_0__POR (0x00) +#define TOMTOM_A_SVASS_SPE_INBOX_1 (0x061) +#define TOMTOM_A_SVASS_SPE_INBOX_1__POR (0x00) +#define TOMTOM_A_SVASS_SPE_INBOX_2 (0x062) +#define TOMTOM_A_SVASS_SPE_INBOX_2__POR (0x00) +#define TOMTOM_A_SVASS_SPE_INBOX_3 (0x063) +#define TOMTOM_A_SVASS_SPE_INBOX_3__POR (0x00) +#define TOMTOM_A_SVASS_SPE_INBOX_4 (0x064) +#define TOMTOM_A_SVASS_SPE_INBOX_4__POR (0x00) +#define TOMTOM_A_SVASS_SPE_INBOX_5 (0x065) +#define TOMTOM_A_SVASS_SPE_INBOX_5__POR (0x00) +#define TOMTOM_A_SVASS_SPE_INBOX_6 (0x066) +#define TOMTOM_A_SVASS_SPE_INBOX_6__POR (0x00) +#define TOMTOM_A_SVASS_SPE_INBOX_7 (0x067) +#define TOMTOM_A_SVASS_SPE_INBOX_7__POR (0x00) +#define TOMTOM_A_SVASS_SPE_INBOX_8 (0x068) +#define TOMTOM_A_SVASS_SPE_INBOX_8__POR (0x00) +#define TOMTOM_A_SVASS_SPE_INBOX_9 (0x069) +#define TOMTOM_A_SVASS_SPE_INBOX_9__POR (0x00) +#define TOMTOM_A_SVASS_SPE_INBOX_10 (0x06A) +#define TOMTOM_A_SVASS_SPE_INBOX_10__POR (0x00) +#define TOMTOM_A_SVASS_SPE_INBOX_11 (0x06B) +#define TOMTOM_A_SVASS_SPE_INBOX_11__POR (0x00) +#define TOMTOM_A_SVASS_SPE_OUTBOX_0 (0x070) +#define TOMTOM_A_SVASS_SPE_OUTBOX_0__POR (0x00) +#define TOMTOM_A_SVASS_SPE_OUTBOX_1 (0x071) +#define TOMTOM_A_SVASS_SPE_OUTBOX_1__POR (0x00) +#define TOMTOM_A_SVASS_SPE_OUTBOX_2 (0x072) +#define TOMTOM_A_SVASS_SPE_OUTBOX_2__POR (0x00) +#define TOMTOM_A_SVASS_SPE_OUTBOX_3 (0x073) +#define TOMTOM_A_SVASS_SPE_OUTBOX_3__POR (0x00) +#define TOMTOM_A_SVASS_SPE_OUTBOX_4 (0x074) +#define TOMTOM_A_SVASS_SPE_OUTBOX_4__POR (0x00) +#define TOMTOM_A_SVASS_SPE_OUTBOX_5 (0x075) +#define TOMTOM_A_SVASS_SPE_OUTBOX_5__POR (0x00) +#define TOMTOM_A_SVASS_SPE_OUTBOX_6 (0x076) +#define TOMTOM_A_SVASS_SPE_OUTBOX_6__POR (0x00) +#define TOMTOM_A_SVASS_SPE_OUTBOX_7 (0x077) +#define TOMTOM_A_SVASS_SPE_OUTBOX_7__POR (0x00) +#define TOMTOM_A_SVASS_SPE_OUTBOX_8 (0x078) +#define TOMTOM_A_SVASS_SPE_OUTBOX_8__POR (0x00) +#define TOMTOM_A_SVASS_SPE_OUTBOX_9 (0x079) +#define TOMTOM_A_SVASS_SPE_OUTBOX_9__POR (0x00) +#define TOMTOM_A_SVASS_SPE_OUTBOX_10 (0x07A) +#define TOMTOM_A_SVASS_SPE_OUTBOX_10__POR (0x00) +#define TOMTOM_A_SVASS_SPE_OUTBOX_11 (0x07B) +#define TOMTOM_A_SVASS_SPE_OUTBOX_11__POR (0x00) +#define TOMTOM_A_INTR_MODE (0x090) +#define TOMTOM_A_INTR_MODE__POR (0x00) +#define TOMTOM_A_INTR1_MASK0 (0x094) +#define TOMTOM_A_INTR1_MASK0__POR (0xFF) +#define TOMTOM_A_INTR1_MASK1 (0x095) +#define TOMTOM_A_INTR1_MASK1__POR (0xFF) +#define TOMTOM_A_INTR1_MASK2 (0x096) +#define TOMTOM_A_INTR1_MASK2__POR (0xFF) +#define TOMTOM_A_INTR1_MASK3 (0x097) +#define TOMTOM_A_INTR1_MASK3__POR (0xFF) +#define TOMTOM_A_INTR1_STATUS0 (0x098) +#define TOMTOM_A_INTR1_STATUS0__POR (0x00) +#define TOMTOM_A_INTR1_STATUS1 (0x099) +#define TOMTOM_A_INTR1_STATUS1__POR (0x00) +#define TOMTOM_A_INTR1_STATUS2 (0x09A) +#define TOMTOM_A_INTR1_STATUS2__POR (0x00) +#define TOMTOM_A_INTR1_STATUS3 (0x09B) +#define TOMTOM_A_INTR1_STATUS3__POR (0x00) +#define TOMTOM_A_INTR1_CLEAR0 (0x09C) +#define TOMTOM_A_INTR1_CLEAR0__POR (0x00) +#define TOMTOM_A_INTR1_CLEAR1 (0x09D) +#define TOMTOM_A_INTR1_CLEAR1__POR (0x00) +#define TOMTOM_A_INTR1_CLEAR2 (0x09E) +#define TOMTOM_A_INTR1_CLEAR2__POR (0x00) +#define TOMTOM_A_INTR1_CLEAR3 (0x09F) +#define TOMTOM_A_INTR1_CLEAR3__POR (0x00) +#define TOMTOM_A_INTR1_LEVEL0 (0x0A0) +#define TOMTOM_A_INTR1_LEVEL0__POR (0x01) +#define TOMTOM_A_INTR1_LEVEL1 (0x0A1) +#define TOMTOM_A_INTR1_LEVEL1__POR (0x00) +#define TOMTOM_A_INTR1_LEVEL2 (0x0A2) +#define TOMTOM_A_INTR1_LEVEL2__POR (0x40) +#define TOMTOM_A_INTR1_LEVEL3 (0x0A3) +#define TOMTOM_A_INTR1_LEVEL3__POR (0x00) +#define TOMTOM_A_INTR1_TEST0 (0x0A4) +#define TOMTOM_A_INTR1_TEST0__POR (0x00) +#define TOMTOM_A_INTR1_TEST1 (0x0A5) +#define TOMTOM_A_INTR1_TEST1__POR (0x00) +#define TOMTOM_A_INTR1_TEST2 (0x0A6) +#define TOMTOM_A_INTR1_TEST2__POR (0x00) +#define TOMTOM_A_INTR1_TEST3 (0x0A7) +#define TOMTOM_A_INTR1_TEST3__POR (0x00) +#define TOMTOM_A_INTR1_SET0 (0x0A8) +#define TOMTOM_A_INTR1_SET0__POR (0x00) +#define TOMTOM_A_INTR1_SET1 (0x0A9) +#define TOMTOM_A_INTR1_SET1__POR (0x00) +#define TOMTOM_A_INTR1_SET2 (0x0AA) +#define TOMTOM_A_INTR1_SET2__POR (0x00) +#define TOMTOM_A_INTR1_SET3 (0x0AB) +#define TOMTOM_A_INTR1_SET3__POR (0x00) +#define TOMTOM_A_INTR2_MASK0 (0x0B0) +#define TOMTOM_A_INTR2_MASK0__POR (0xFF) +#define TOMTOM_A_INTR2_STATUS0 (0x0B2) +#define TOMTOM_A_INTR2_STATUS0__POR (0x00) +#define TOMTOM_A_INTR2_CLEAR0 (0x0B4) +#define TOMTOM_A_INTR2_CLEAR0__POR (0x00) +#define TOMTOM_A_INTR2_LEVEL0 (0x0B6) +#define TOMTOM_A_INTR2_LEVEL0__POR (0x00) +#define TOMTOM_A_INTR2_TEST0 (0x0B8) +#define TOMTOM_A_INTR2_TEST0__POR (0x00) +#define TOMTOM_A_INTR2_SET0 (0x0BA) +#define TOMTOM_A_INTR2_SET0__POR (0x00) +#define TOMTOM_A_CDC_TX_I2S_SCK_MODE (0x0C0) +#define TOMTOM_A_CDC_TX_I2S_SCK_MODE__POR (0x00) +#define TOMTOM_A_CDC_TX_I2S_WS_MODE (0x0C1) +#define TOMTOM_A_CDC_TX_I2S_WS_MODE__POR (0x00) +#define TOMTOM_A_CDC_DMIC_DATA0_MODE (0x0C4) +#define TOMTOM_A_CDC_DMIC_DATA0_MODE__POR (0x00) +#define TOMTOM_A_CDC_DMIC_CLK0_MODE (0x0C5) +#define TOMTOM_A_CDC_DMIC_CLK0_MODE__POR (0x00) +#define TOMTOM_A_CDC_DMIC_DATA1_MODE (0x0C6) +#define TOMTOM_A_CDC_DMIC_DATA1_MODE__POR (0x00) +#define TOMTOM_A_CDC_DMIC_CLK1_MODE (0x0C7) +#define TOMTOM_A_CDC_DMIC_CLK1_MODE__POR (0x00) +#define TOMTOM_A_CDC_RX_I2S_SCK_MODE (0x0C8) +#define TOMTOM_A_CDC_RX_I2S_SCK_MODE__POR (0x00) +#define TOMTOM_A_CDC_RX_I2S_WS_MODE (0x0C9) +#define TOMTOM_A_CDC_RX_I2S_WS_MODE__POR (0x00) +#define TOMTOM_A_CDC_DMIC_DATA2_MODE (0x0CA) +#define TOMTOM_A_CDC_DMIC_DATA2_MODE__POR (0x00) +#define TOMTOM_A_CDC_DMIC_CLK2_MODE (0x0CB) +#define TOMTOM_A_CDC_DMIC_CLK2_MODE__POR (0x00) +#define TOMTOM_A_CDC_INTR1_MODE (0x0CC) +#define TOMTOM_A_CDC_INTR1_MODE__POR (0x00) +#define TOMTOM_A_CDC_SB_NRZ_SEL_MODE (0x0CD) +#define TOMTOM_A_CDC_SB_NRZ_SEL_MODE__POR (0x00) +#define TOMTOM_A_CDC_INTR2_MODE (0x0CE) +#define TOMTOM_A_CDC_INTR2_MODE__POR (0x00) +#define TOMTOM_A_CDC_RF_PA_ON_MODE (0x0CF) +#define TOMTOM_A_CDC_RF_PA_ON_MODE__POR (0x00) +#define TOMTOM_A_CDC_BOOST_MODE (0x0D0) +#define TOMTOM_A_CDC_BOOST_MODE__POR (0x00) +#define TOMTOM_A_CDC_JTCK_MODE (0x0D1) +#define TOMTOM_A_CDC_JTCK_MODE__POR (0x00) +#define TOMTOM_A_CDC_JTDI_MODE (0x0D2) +#define TOMTOM_A_CDC_JTDI_MODE__POR (0x00) +#define TOMTOM_A_CDC_JTMS_MODE (0x0D3) +#define TOMTOM_A_CDC_JTMS_MODE__POR (0x00) +#define TOMTOM_A_CDC_JTDO_MODE (0x0D4) +#define TOMTOM_A_CDC_JTDO_MODE__POR (0x00) +#define TOMTOM_A_CDC_JTRST_MODE (0x0D5) +#define TOMTOM_A_CDC_JTRST_MODE__POR (0x00) +#define TOMTOM_A_CDC_BIST_MODE_MODE (0x0D6) +#define TOMTOM_A_CDC_BIST_MODE_MODE__POR (0x00) +#define TOMTOM_A_CDC_MAD_MAIN_CTL_1 (0x0E0) +#define TOMTOM_A_CDC_MAD_MAIN_CTL_1__POR (0x00) +#define TOMTOM_A_CDC_MAD_MAIN_CTL_2 (0x0E1) +#define TOMTOM_A_CDC_MAD_MAIN_CTL_2__POR (0x00) +#define TOMTOM_A_CDC_MAD_AUDIO_CTL_1 (0x0E2) +#define TOMTOM_A_CDC_MAD_AUDIO_CTL_1__POR (0x00) +#define TOMTOM_A_CDC_MAD_AUDIO_CTL_2 (0x0E3) +#define TOMTOM_A_CDC_MAD_AUDIO_CTL_2__POR (0x00) +#define TOMTOM_A_CDC_MAD_AUDIO_CTL_3 (0x0E4) +#define TOMTOM_A_CDC_MAD_AUDIO_CTL_3__POR (0x00) +#define TOMTOM_A_CDC_MAD_AUDIO_CTL_4 (0x0E5) +#define TOMTOM_A_CDC_MAD_AUDIO_CTL_4__POR (0x00) +#define TOMTOM_A_CDC_MAD_AUDIO_CTL_5 (0x0E6) +#define TOMTOM_A_CDC_MAD_AUDIO_CTL_5__POR (0x00) +#define TOMTOM_A_CDC_MAD_AUDIO_CTL_6 (0x0E7) +#define TOMTOM_A_CDC_MAD_AUDIO_CTL_6__POR (0x00) +#define TOMTOM_A_CDC_MAD_AUDIO_CTL_7 (0x0E8) +#define TOMTOM_A_CDC_MAD_AUDIO_CTL_7__POR (0x00) +#define TOMTOM_A_CDC_MAD_AUDIO_CTL_8 (0x0E9) +#define TOMTOM_A_CDC_MAD_AUDIO_CTL_8__POR (0x00) +#define TOMTOM_A_CDC_MAD_AUDIO_IIR_CTL_PTR (0x0EA) +#define TOMTOM_A_CDC_MAD_AUDIO_IIR_CTL_PTR__POR (0x00) +#define TOMTOM_A_CDC_MAD_AUDIO_IIR_CTL_VAL (0x0EB) +#define TOMTOM_A_CDC_MAD_AUDIO_IIR_CTL_VAL__POR (0x40) +#define TOMTOM_A_CDC_MAD_ULTR_CTL_1 (0x0EC) +#define TOMTOM_A_CDC_MAD_ULTR_CTL_1__POR (0x00) +#define TOMTOM_A_CDC_MAD_ULTR_CTL_2 (0x0ED) +#define TOMTOM_A_CDC_MAD_ULTR_CTL_2__POR (0x00) +#define TOMTOM_A_CDC_MAD_ULTR_CTL_3 (0x0EE) +#define TOMTOM_A_CDC_MAD_ULTR_CTL_3__POR (0x00) +#define TOMTOM_A_CDC_MAD_ULTR_CTL_4 (0x0EF) +#define TOMTOM_A_CDC_MAD_ULTR_CTL_4__POR (0x00) +#define TOMTOM_A_CDC_MAD_ULTR_CTL_5 (0x0F0) +#define TOMTOM_A_CDC_MAD_ULTR_CTL_5__POR (0x00) +#define TOMTOM_A_CDC_MAD_ULTR_CTL_6 (0x0F1) +#define TOMTOM_A_CDC_MAD_ULTR_CTL_6__POR (0x00) +#define TOMTOM_A_CDC_MAD_ULTR_CTL_7 (0x0F2) +#define TOMTOM_A_CDC_MAD_ULTR_CTL_7__POR (0x00) +#define TOMTOM_A_CDC_MAD_BEACON_CTL_1 (0x0F3) +#define TOMTOM_A_CDC_MAD_BEACON_CTL_1__POR (0x00) +#define TOMTOM_A_CDC_MAD_BEACON_CTL_2 (0x0F4) +#define TOMTOM_A_CDC_MAD_BEACON_CTL_2__POR (0x00) +#define TOMTOM_A_CDC_MAD_BEACON_CTL_3 (0x0F5) +#define TOMTOM_A_CDC_MAD_BEACON_CTL_3__POR (0x00) +#define TOMTOM_A_CDC_MAD_BEACON_CTL_4 (0x0F6) +#define TOMTOM_A_CDC_MAD_BEACON_CTL_4__POR (0x00) +#define TOMTOM_A_CDC_MAD_BEACON_CTL_5 (0x0F7) +#define TOMTOM_A_CDC_MAD_BEACON_CTL_5__POR (0x00) +#define TOMTOM_A_CDC_MAD_BEACON_CTL_6 (0x0F8) +#define TOMTOM_A_CDC_MAD_BEACON_CTL_6__POR (0x00) +#define TOMTOM_A_CDC_MAD_BEACON_CTL_7 (0x0F9) +#define TOMTOM_A_CDC_MAD_BEACON_CTL_7__POR (0x00) +#define TOMTOM_A_CDC_MAD_BEACON_CTL_8 (0x0FA) +#define TOMTOM_A_CDC_MAD_BEACON_CTL_8__POR (0x00) +#define TOMTOM_A_CDC_MAD_BEACON_IIR_CTL_PTR (0x0FB) +#define TOMTOM_A_CDC_MAD_BEACON_IIR_CTL_PTR__POR (0x00) +#define TOMTOM_A_CDC_MAD_BEACON_IIR_CTL_VAL (0x0FC) +#define TOMTOM_A_CDC_MAD_BEACON_IIR_CTL_VAL__POR (0x00) +#define TOMTOM_A_CDC_MAD_INP_SEL (0x0FD) +#define TOMTOM_A_CDC_MAD_INP_SEL__POR (0x00) +#define TOMTOM_A_BIAS_REF_CTL (0x100) +#define TOMTOM_A_BIAS_REF_CTL__POR (0x1C) +#define TOMTOM_A_BIAS_CENTRAL_BG_CTL (0x101) +#define TOMTOM_A_BIAS_CENTRAL_BG_CTL__POR (0x50) +#define TOMTOM_A_BIAS_PRECHRG_CTL (0x102) +#define TOMTOM_A_BIAS_PRECHRG_CTL__POR (0x07) +#define TOMTOM_A_BIAS_CURR_CTL_1 (0x103) +#define TOMTOM_A_BIAS_CURR_CTL_1__POR (0x52) +#define TOMTOM_A_BIAS_CURR_CTL_2 (0x104) +#define TOMTOM_A_BIAS_CURR_CTL_2__POR (0x00) +#define TOMTOM_A_BIAS_OSC_BG_CTL (0x105) +#define TOMTOM_A_BIAS_OSC_BG_CTL__POR (0x36) +#define TOMTOM_A_CLK_BUFF_EN1 (0x108) +#define TOMTOM_A_CLK_BUFF_EN1__POR (0x04) +#define TOMTOM_A_CLK_BUFF_EN2 (0x109) +#define TOMTOM_A_CLK_BUFF_EN2__POR (0x02) +#define TOMTOM_A_LDO_L_MODE_1 (0x10A) +#define TOMTOM_A_LDO_L_MODE_1__POR (0x08) +#define TOMTOM_A_LDO_L_MODE_2 (0x10B) +#define TOMTOM_A_LDO_L_MODE_2__POR (0x50) +#define TOMTOM_A_LDO_L_CTRL_1 (0x10C) +#define TOMTOM_A_LDO_L_CTRL_1__POR (0x70) +#define TOMTOM_A_LDO_L_CTRL_2 (0x10D) +#define TOMTOM_A_LDO_L_CTRL_2__POR (0x55) +#define TOMTOM_A_LDO_L_CTRL_3 (0x10E) +#define TOMTOM_A_LDO_L_CTRL_3__POR (0x56) +#define TOMTOM_A_LDO_L_CTRL_4 (0x10F) +#define TOMTOM_A_LDO_L_CTRL_4__POR (0x55) +#define TOMTOM_A_LDO_H_MODE_1 (0x110) +#define TOMTOM_A_LDO_H_MODE_1__POR (0x65) +#define TOMTOM_A_LDO_H_MODE_2 (0x111) +#define TOMTOM_A_LDO_H_MODE_2__POR (0xA8) +#define TOMTOM_A_LDO_H_LOOP_CTL (0x112) +#define TOMTOM_A_LDO_H_LOOP_CTL__POR (0x6B) +#define TOMTOM_A_LDO_H_COMP_1 (0x113) +#define TOMTOM_A_LDO_H_COMP_1__POR (0x84) +#define TOMTOM_A_LDO_H_COMP_2 (0x114) +#define TOMTOM_A_LDO_H_COMP_2__POR (0xE0) +#define TOMTOM_A_LDO_H_BIAS_1 (0x115) +#define TOMTOM_A_LDO_H_BIAS_1__POR (0x6D) +#define TOMTOM_A_LDO_H_BIAS_2 (0x116) +#define TOMTOM_A_LDO_H_BIAS_2__POR (0xA5) +#define TOMTOM_A_LDO_H_BIAS_3 (0x117) +#define TOMTOM_A_LDO_H_BIAS_3__POR (0x60) +#define TOMTOM_A_VBAT_CLK (0x118) +#define TOMTOM_A_VBAT_CLK__POR (0x03) +#define TOMTOM_A_VBAT_LOOP (0x119) +#define TOMTOM_A_VBAT_LOOP__POR (0x02) +#define TOMTOM_A_VBAT_REF (0x11A) +#define TOMTOM_A_VBAT_REF__POR (0x20) +#define TOMTOM_A_VBAT_ADC_TEST (0x11B) +#define TOMTOM_A_VBAT_ADC_TEST__POR (0x00) +#define TOMTOM_A_VBAT_FE (0x11C) +#define TOMTOM_A_VBAT_FE__POR (0x48) +#define TOMTOM_A_VBAT_BIAS_1 (0x11D) +#define TOMTOM_A_VBAT_BIAS_1__POR (0x03) +#define TOMTOM_A_VBAT_BIAS_2 (0x11E) +#define TOMTOM_A_VBAT_BIAS_2__POR (0x00) +#define TOMTOM_A_VBAT_ADC_DATA_MSB (0x11F) +#define TOMTOM_A_VBAT_ADC_DATA_MSB__POR (0x00) +#define TOMTOM_A_VBAT_ADC_DATA_LSB (0x120) +#define TOMTOM_A_VBAT_ADC_DATA_LSB__POR (0x00) +#define TOMTOM_A_FLL_NREF (0x121) +#define TOMTOM_A_FLL_NREF__POR (0x12) +#define TOMTOM_A_FLL_KDCO_TUNE (0x122) +#define TOMTOM_A_FLL_KDCO_TUNE__POR (0x05) +#define TOMTOM_A_FLL_LOCK_THRESH (0x123) +#define TOMTOM_A_FLL_LOCK_THRESH__POR (0xC2) +#define TOMTOM_A_FLL_LOCK_DET_COUNT (0x124) +#define TOMTOM_A_FLL_LOCK_DET_COUNT__POR (0x40) +#define TOMTOM_A_FLL_DAC_THRESHOLD (0x125) +#define TOMTOM_A_FLL_DAC_THRESHOLD__POR (0xC8) +#define TOMTOM_A_FLL_TEST_DCO_FREERUN (0x126) +#define TOMTOM_A_FLL_TEST_DCO_FREERUN__POR (0x00) +#define TOMTOM_A_FLL_TEST_ENABLE (0x127) +#define TOMTOM_A_FLL_TEST_ENABLE__POR (0x00) +#define TOMTOM_A_MICB_CFILT_1_CTL (0x128) +#define TOMTOM_A_MICB_CFILT_1_CTL__POR (0x40) +#define TOMTOM_A_MICB_CFILT_1_VAL (0x129) +#define TOMTOM_A_MICB_CFILT_1_VAL__POR (0x80) +#define TOMTOM_A_MICB_CFILT_1_PRECHRG (0x12A) +#define TOMTOM_A_MICB_CFILT_1_PRECHRG__POR (0x38) +#define TOMTOM_A_MICB_1_CTL (0x12B) +#define TOMTOM_A_MICB_1_CTL__POR (0x16) +#define TOMTOM_A_MICB_1_INT_RBIAS (0x12C) +#define TOMTOM_A_MICB_1_INT_RBIAS__POR (0x24) +#define TOMTOM_A_MICB_1_MBHC (0x12D) +#define TOMTOM_A_MICB_1_MBHC__POR (0x01) +#define TOMTOM_A_MICB_CFILT_2_CTL (0x12E) +#define TOMTOM_A_MICB_CFILT_2_CTL__POR (0x41) +#define TOMTOM_A_MICB_CFILT_2_VAL (0x12F) +#define TOMTOM_A_MICB_CFILT_2_VAL__POR (0x80) +#define TOMTOM_A_MICB_CFILT_2_PRECHRG (0x130) +#define TOMTOM_A_MICB_CFILT_2_PRECHRG__POR (0x38) +#define TOMTOM_A_MICB_2_CTL (0x131) +#define TOMTOM_A_MICB_2_CTL__POR (0x16) +#define TOMTOM_A_MICB_2_INT_RBIAS (0x132) +#define TOMTOM_A_MICB_2_INT_RBIAS__POR (0x24) +#define TOMTOM_A_MICB_2_MBHC (0x133) +#define TOMTOM_A_MICB_2_MBHC__POR (0x02) +#define TOMTOM_A_MICB_CFILT_3_CTL (0x134) +#define TOMTOM_A_MICB_CFILT_3_CTL__POR (0x40) +#define TOMTOM_A_MICB_CFILT_3_VAL (0x135) +#define TOMTOM_A_MICB_CFILT_3_VAL__POR (0x80) +#define TOMTOM_A_MICB_CFILT_3_PRECHRG (0x136) +#define TOMTOM_A_MICB_CFILT_3_PRECHRG__POR (0x38) +#define TOMTOM_A_MICB_3_CTL (0x137) +#define TOMTOM_A_MICB_3_CTL__POR (0x16) +#define TOMTOM_A_MICB_3_INT_RBIAS (0x138) +#define TOMTOM_A_MICB_3_INT_RBIAS__POR (0x24) +#define TOMTOM_A_MICB_3_MBHC (0x139) +#define TOMTOM_A_MICB_3_MBHC__POR (0x00) +#define TOMTOM_A_MICB_4_CTL (0x13A) +#define TOMTOM_A_MICB_4_CTL__POR (0x16) +#define TOMTOM_A_MICB_4_INT_RBIAS (0x13B) +#define TOMTOM_A_MICB_4_INT_RBIAS__POR (0x24) +#define TOMTOM_A_MICB_4_MBHC (0x13C) +#define TOMTOM_A_MICB_4_MBHC__POR (0x01) +#define TOMTOM_A_SPKR_DRV2_EN (0x13D) +#define TOMTOM_A_SPKR_DRV2_EN__POR (0x6F) +#define TOMTOM_A_SPKR_DRV2_GAIN (0x13E) +#define TOMTOM_A_SPKR_DRV2_GAIN__POR (0x00) +#define TOMTOM_A_SPKR_DRV2_DAC_CTL (0x13F) +#define TOMTOM_A_SPKR_DRV2_DAC_CTL__POR (0x04) +#define TOMTOM_A_SPKR_DRV2_OCP_CTL (0x140) +#define TOMTOM_A_SPKR_DRV2_OCP_CTL__POR (0x97) +#define TOMTOM_A_SPKR_DRV2_CLIP_DET (0x141) +#define TOMTOM_A_SPKR_DRV2_CLIP_DET__POR (0x01) +#define TOMTOM_A_SPKR_DRV2_DBG_DAC (0x142) +#define TOMTOM_A_SPKR_DRV2_DBG_DAC__POR (0x05) +#define TOMTOM_A_SPKR_DRV2_DBG_PA (0x143) +#define TOMTOM_A_SPKR_DRV2_DBG_PA__POR (0x18) +#define TOMTOM_A_SPKR_DRV2_DBG_PWRSTG (0x144) +#define TOMTOM_A_SPKR_DRV2_DBG_PWRSTG__POR (0x00) +#define TOMTOM_A_SPKR_DRV2_BIAS_LDO (0x145) +#define TOMTOM_A_SPKR_DRV2_BIAS_LDO__POR (0x45) +#define TOMTOM_A_SPKR_DRV2_BIAS_INT (0x146) +#define TOMTOM_A_SPKR_DRV2_BIAS_INT__POR (0xA5) +#define TOMTOM_A_SPKR_DRV2_BIAS_PA (0x147) +#define TOMTOM_A_SPKR_DRV2_BIAS_PA__POR (0x55) +#define TOMTOM_A_SPKR_DRV2_STATUS_OCP (0x148) +#define TOMTOM_A_SPKR_DRV2_STATUS_OCP__POR (0x00) +#define TOMTOM_A_SPKR_DRV2_STATUS_PA (0x149) +#define TOMTOM_A_SPKR_DRV2_STATUS_PA__POR (0x00) +#define TOMTOM_A_MBHC_INSERT_DETECT (0x14A) +#define TOMTOM_A_MBHC_INSERT_DETECT__POR (0x00) +#define TOMTOM_A_MBHC_INSERT_DET_STATUS (0x14B) +#define TOMTOM_A_MBHC_INSERT_DET_STATUS__POR (0x00) +#define TOMTOM_A_TX_COM_BIAS (0x14C) +#define TOMTOM_A_TX_COM_BIAS__POR (0xF0) +#define TOMTOM_A_MBHC_INSERT_DETECT2 (0x14D) +#define TOMTOM_A_MBHC_INSERT_DETECT2__POR (0xD0) +#define TOMTOM_A_MBHC_SCALING_MUX_1 (0x14E) +#define TOMTOM_A_MBHC_SCALING_MUX_1__POR (0x00) +#define TOMTOM_A_MBHC_SCALING_MUX_2 (0x14F) +#define TOMTOM_A_MBHC_SCALING_MUX_2__POR (0x80) +#define TOMTOM_A_MAD_ANA_CTRL (0x150) +#define TOMTOM_A_MAD_ANA_CTRL__POR (0xF1) +#define TOMTOM_A_TX_SUP_SWITCH_CTRL_1 (0x151) +#define TOMTOM_A_TX_SUP_SWITCH_CTRL_1__POR (0x00) +#define TOMTOM_A_TX_SUP_SWITCH_CTRL_2 (0x152) +#define TOMTOM_A_TX_SUP_SWITCH_CTRL_2__POR (0x80) +#define TOMTOM_A_TX_1_GAIN (0x153) +#define TOMTOM_A_TX_1_GAIN__POR (0x02) +#define TOMTOM_A_TX_1_2_TEST_EN (0x154) +#define TOMTOM_A_TX_1_2_TEST_EN__POR (0xCC) +#define TOMTOM_A_TX_2_GAIN (0x155) +#define TOMTOM_A_TX_2_GAIN__POR (0x02) +#define TOMTOM_A_TX_1_2_ADC_IB (0x156) +#define TOMTOM_A_TX_1_2_ADC_IB__POR (0x44) +#define TOMTOM_A_TX_1_2_ATEST_REFCTRL (0x157) +#define TOMTOM_A_TX_1_2_ATEST_REFCTRL__POR (0x00) +#define TOMTOM_A_TX_1_2_TEST_CTL (0x158) +#define TOMTOM_A_TX_1_2_TEST_CTL__POR (0x38) +#define TOMTOM_A_TX_1_2_TEST_BLOCK_EN (0x159) +#define TOMTOM_A_TX_1_2_TEST_BLOCK_EN__POR (0xFC) +#define TOMTOM_A_TX_1_2_TXFE_CLKDIV (0x15A) +#define TOMTOM_A_TX_1_2_TXFE_CLKDIV__POR (0x55) +#define TOMTOM_A_TX_1_2_SAR_ERR_CH1 (0x15B) +#define TOMTOM_A_TX_1_2_SAR_ERR_CH1__POR (0x00) +#define TOMTOM_A_TX_1_2_SAR_ERR_CH2 (0x15C) +#define TOMTOM_A_TX_1_2_SAR_ERR_CH2__POR (0x00) +#define TOMTOM_A_TX_3_GAIN (0x15D) +#define TOMTOM_A_TX_3_GAIN__POR (0x02) +#define TOMTOM_A_TX_3_4_TEST_EN (0x15E) +#define TOMTOM_A_TX_3_4_TEST_EN__POR (0xCC) +#define TOMTOM_A_TX_4_GAIN (0x15F) +#define TOMTOM_A_TX_4_GAIN__POR (0x02) +#define TOMTOM_A_TX_3_4_ADC_IB (0x160) +#define TOMTOM_A_TX_3_4_ADC_IB__POR (0x44) +#define TOMTOM_A_TX_3_4_ATEST_REFCTRL (0x161) +#define TOMTOM_A_TX_3_4_ATEST_REFCTRL__POR (0x00) +#define TOMTOM_A_TX_3_4_TEST_CTL (0x162) +#define TOMTOM_A_TX_3_4_TEST_CTL__POR (0x38) +#define TOMTOM_A_TX_3_4_TEST_BLOCK_EN (0x163) +#define TOMTOM_A_TX_3_4_TEST_BLOCK_EN__POR (0xFC) +#define TOMTOM_A_TX_3_4_TXFE_CKDIV (0x164) +#define TOMTOM_A_TX_3_4_TXFE_CKDIV__POR (0x55) +#define TOMTOM_A_TX_3_4_SAR_ERR_CH3 (0x165) +#define TOMTOM_A_TX_3_4_SAR_ERR_CH3__POR (0x00) +#define TOMTOM_A_TX_3_4_SAR_ERR_CH4 (0x166) +#define TOMTOM_A_TX_3_4_SAR_ERR_CH4__POR (0x00) +#define TOMTOM_A_TX_5_GAIN (0x167) +#define TOMTOM_A_TX_5_GAIN__POR (0x02) +#define TOMTOM_A_TX_5_6_TEST_EN (0x168) +#define TOMTOM_A_TX_5_6_TEST_EN__POR (0xCC) +#define TOMTOM_A_TX_6_GAIN (0x169) +#define TOMTOM_A_TX_6_GAIN__POR (0x02) +#define TOMTOM_A_TX_5_6_ADC_IB (0x16A) +#define TOMTOM_A_TX_5_6_ADC_IB__POR (0x44) +#define TOMTOM_A_TX_5_6_ATEST_REFCTRL (0x16B) +#define TOMTOM_A_TX_5_6_ATEST_REFCTRL__POR (0x00) +#define TOMTOM_A_TX_5_6_TEST_CTL (0x16C) +#define TOMTOM_A_TX_5_6_TEST_CTL__POR (0x38) +#define TOMTOM_A_TX_5_6_TEST_BLOCK_EN (0x16D) +#define TOMTOM_A_TX_5_6_TEST_BLOCK_EN__POR (0xFC) +#define TOMTOM_A_TX_5_6_TXFE_CKDIV (0x16E) +#define TOMTOM_A_TX_5_6_TXFE_CKDIV__POR (0x55) +#define TOMTOM_A_TX_5_6_SAR_ERR_CH5 (0x16F) +#define TOMTOM_A_TX_5_6_SAR_ERR_CH5__POR (0x00) +#define TOMTOM_A_TX_5_6_SAR_ERR_CH6 (0x170) +#define TOMTOM_A_TX_5_6_SAR_ERR_CH6__POR (0x00) +#define TOMTOM_A_TX_7_MBHC_EN (0x171) +#define TOMTOM_A_TX_7_MBHC_EN__POR (0x0C) +#define TOMTOM_A_TX_7_MBHC_ATEST_REFCTRL (0x172) +#define TOMTOM_A_TX_7_MBHC_ATEST_REFCTRL__POR (0x00) +#define TOMTOM_A_TX_7_MBHC_ADC (0x173) +#define TOMTOM_A_TX_7_MBHC_ADC__POR (0x44) +#define TOMTOM_A_TX_7_MBHC_TEST_CTL (0x174) +#define TOMTOM_A_TX_7_MBHC_TEST_CTL__POR (0x38) +#define TOMTOM_A_TX_7_MBHC_SAR_ERR (0x175) +#define TOMTOM_A_TX_7_MBHC_SAR_ERR__POR (0x00) +#define TOMTOM_A_TX_7_TXFE_CLKDIV (0x176) +#define TOMTOM_A_TX_7_TXFE_CLKDIV__POR (0x8B) +#define TOMTOM_A_RCO_CTRL (0x177) +#define TOMTOM_A_RCO_CTRL__POR (0x00) +#define TOMTOM_A_RCO_CALIBRATION_CTRL1 (0x178) +#define TOMTOM_A_RCO_CALIBRATION_CTRL1__POR (0x00) +#define TOMTOM_A_RCO_CALIBRATION_CTRL2 (0x179) +#define TOMTOM_A_RCO_CALIBRATION_CTRL2__POR (0x00) +#define TOMTOM_A_RCO_CALIBRATION_CTRL3 (0x17A) +#define TOMTOM_A_RCO_CALIBRATION_CTRL3__POR (0x00) +#define TOMTOM_A_RCO_TEST_CTRL (0x17B) +#define TOMTOM_A_RCO_TEST_CTRL__POR (0x00) +#define TOMTOM_A_RCO_CALIBRATION_RESULT1 (0x17C) +#define TOMTOM_A_RCO_CALIBRATION_RESULT1__POR (0x00) +#define TOMTOM_A_RCO_CALIBRATION_RESULT2 (0x17D) +#define TOMTOM_A_RCO_CALIBRATION_RESULT2__POR (0x00) +#define TOMTOM_A_BUCK_MODE_1 (0x181) +#define TOMTOM_A_BUCK_MODE_1__POR (0x21) +#define TOMTOM_A_BUCK_MODE_2 (0x182) +#define TOMTOM_A_BUCK_MODE_2__POR (0xFF) +#define TOMTOM_A_BUCK_MODE_3 (0x183) +#define TOMTOM_A_BUCK_MODE_3__POR (0xCE) +#define TOMTOM_A_BUCK_MODE_4 (0x184) +#define TOMTOM_A_BUCK_MODE_4__POR (0x3A) +#define TOMTOM_A_BUCK_MODE_5 (0x185) +#define TOMTOM_A_BUCK_MODE_5__POR (0x00) +#define TOMTOM_A_BUCK_CTRL_VCL_1 (0x186) +#define TOMTOM_A_BUCK_CTRL_VCL_1__POR (0x08) +#define TOMTOM_A_BUCK_CTRL_VCL_2 (0x187) +#define TOMTOM_A_BUCK_CTRL_VCL_2__POR (0xA3) +#define TOMTOM_A_BUCK_CTRL_VCL_3 (0x188) +#define TOMTOM_A_BUCK_CTRL_VCL_3__POR (0x82) +#define TOMTOM_A_BUCK_CTRL_CCL_1 (0x189) +#define TOMTOM_A_BUCK_CTRL_CCL_1__POR (0x5B) +#define TOMTOM_A_BUCK_CTRL_CCL_2 (0x18A) +#define TOMTOM_A_BUCK_CTRL_CCL_2__POR (0xDC) +#define TOMTOM_A_BUCK_CTRL_CCL_3 (0x18B) +#define TOMTOM_A_BUCK_CTRL_CCL_3__POR (0x6A) +#define TOMTOM_A_BUCK_CTRL_CCL_4 (0x18C) +#define TOMTOM_A_BUCK_CTRL_CCL_4__POR (0x51) +#define TOMTOM_A_BUCK_CTRL_PWM_DRVR_1 (0x18D) +#define TOMTOM_A_BUCK_CTRL_PWM_DRVR_1__POR (0x50) +#define TOMTOM_A_BUCK_CTRL_PWM_DRVR_2 (0x18E) +#define TOMTOM_A_BUCK_CTRL_PWM_DRVR_2__POR (0x64) +#define TOMTOM_A_BUCK_CTRL_PWM_DRVR_3 (0x18F) +#define TOMTOM_A_BUCK_CTRL_PWM_DRVR_3__POR (0x77) +#define TOMTOM_A_BUCK_TMUX_A_D (0x190) +#define TOMTOM_A_BUCK_TMUX_A_D__POR (0x00) +#define TOMTOM_A_NCP_BUCKREF (0x191) +#define TOMTOM_A_NCP_BUCKREF__POR (0x00) +#define TOMTOM_A_NCP_EN (0x192) +#define TOMTOM_A_NCP_EN__POR (0xFE) +#define TOMTOM_A_NCP_CLK (0x193) +#define TOMTOM_A_NCP_CLK__POR (0x94) +#define TOMTOM_A_NCP_STATIC (0x194) +#define TOMTOM_A_NCP_STATIC__POR (0x28) +#define TOMTOM_A_NCP_VTH_LOW (0x195) +#define TOMTOM_A_NCP_VTH_LOW__POR (0x88) +#define TOMTOM_A_NCP_VTH_HIGH (0x196) +#define TOMTOM_A_NCP_VTH_HIGH__POR (0xA0) +#define TOMTOM_A_NCP_ATEST (0x197) +#define TOMTOM_A_NCP_ATEST__POR (0x00) +#define TOMTOM_A_NCP_DTEST (0x198) +#define TOMTOM_A_NCP_DTEST__POR (0x10) +#define TOMTOM_A_NCP_DLY1 (0x199) +#define TOMTOM_A_NCP_DLY1__POR (0x06) +#define TOMTOM_A_NCP_DLY2 (0x19A) +#define TOMTOM_A_NCP_DLY2__POR (0x06) +#define TOMTOM_A_RX_AUX_SW_CTL (0x19B) +#define TOMTOM_A_RX_AUX_SW_CTL__POR (0x00) +#define TOMTOM_A_RX_PA_AUX_IN_CONN (0x19C) +#define TOMTOM_A_RX_PA_AUX_IN_CONN__POR (0x00) +#define TOMTOM_A_RX_COM_TIMER_DIV (0x19E) +#define TOMTOM_A_RX_COM_TIMER_DIV__POR (0xE8) +#define TOMTOM_A_RX_COM_OCP_CTL (0x19F) +#define TOMTOM_A_RX_COM_OCP_CTL__POR (0x1F) +#define TOMTOM_A_RX_COM_OCP_COUNT (0x1A0) +#define TOMTOM_A_RX_COM_OCP_COUNT__POR (0x77) +#define TOMTOM_A_RX_COM_DAC_CTL (0x1A1) +#define TOMTOM_A_RX_COM_DAC_CTL__POR (0x00) +#define TOMTOM_A_RX_COM_BIAS (0x1A2) +#define TOMTOM_A_RX_COM_BIAS__POR (0x20) +#define TOMTOM_A_RX_HPH_AUTO_CHOP (0x1A4) +#define TOMTOM_A_RX_HPH_AUTO_CHOP__POR (0x38) +#define TOMTOM_A_RX_HPH_CHOP_CTL (0x1A5) +#define TOMTOM_A_RX_HPH_CHOP_CTL__POR (0xA4) +#define TOMTOM_A_RX_HPH_BIAS_PA (0x1A6) +#define TOMTOM_A_RX_HPH_BIAS_PA__POR (0x7A) +#define TOMTOM_A_RX_HPH_BIAS_LDO (0x1A7) +#define TOMTOM_A_RX_HPH_BIAS_LDO__POR (0x87) +#define TOMTOM_A_RX_HPH_BIAS_CNP (0x1A8) +#define TOMTOM_A_RX_HPH_BIAS_CNP__POR (0x8A) +#define TOMTOM_A_RX_HPH_BIAS_WG_OCP (0x1A9) +#define TOMTOM_A_RX_HPH_BIAS_WG_OCP__POR (0x2A) +#define TOMTOM_A_RX_HPH_OCP_CTL (0x1AA) +#define TOMTOM_A_RX_HPH_OCP_CTL__POR (0x69) +#define TOMTOM_A_RX_HPH_CNP_EN (0x1AB) +#define TOMTOM_A_RX_HPH_CNP_EN__POR (0x80) +#define TOMTOM_A_RX_HPH_CNP_WG_CTL (0x1AC) +#define TOMTOM_A_RX_HPH_CNP_WG_CTL__POR (0xDA) +#define TOMTOM_A_RX_HPH_CNP_WG_TIME (0x1AD) +#define TOMTOM_A_RX_HPH_CNP_WG_TIME__POR (0x15) +#define TOMTOM_A_RX_HPH_L_GAIN (0x1AE) +#define TOMTOM_A_RX_HPH_L_GAIN__POR (0xC0) +#define TOMTOM_A_RX_HPH_L_TEST (0x1AF) +#define TOMTOM_A_RX_HPH_L_TEST__POR (0x02) +#define TOMTOM_A_RX_HPH_L_PA_CTL (0x1B0) +#define TOMTOM_A_RX_HPH_L_PA_CTL__POR (0x42) +#define TOMTOM_A_RX_HPH_L_DAC_CTL (0x1B1) +#define TOMTOM_A_RX_HPH_L_DAC_CTL__POR (0x00) +#define TOMTOM_A_RX_HPH_L_ATEST (0x1B2) +#define TOMTOM_A_RX_HPH_L_ATEST__POR (0x00) +#define TOMTOM_A_RX_HPH_L_STATUS (0x1B3) +#define TOMTOM_A_RX_HPH_L_STATUS__POR (0x00) +#define TOMTOM_A_RX_HPH_R_GAIN (0x1B4) +#define TOMTOM_A_RX_HPH_R_GAIN__POR (0x00) +#define TOMTOM_A_RX_HPH_R_TEST (0x1B5) +#define TOMTOM_A_RX_HPH_R_TEST__POR (0x02) +#define TOMTOM_A_RX_HPH_R_PA_CTL (0x1B6) +#define TOMTOM_A_RX_HPH_R_PA_CTL__POR (0x42) +#define TOMTOM_A_RX_HPH_R_DAC_CTL (0x1B7) +#define TOMTOM_A_RX_HPH_R_DAC_CTL__POR (0x00) +#define TOMTOM_A_RX_HPH_R_ATEST (0x1B8) +#define TOMTOM_A_RX_HPH_R_ATEST__POR (0x00) +#define TOMTOM_A_RX_HPH_R_STATUS (0x1B9) +#define TOMTOM_A_RX_HPH_R_STATUS__POR (0x00) +#define TOMTOM_A_RX_EAR_BIAS_PA (0x1BA) +#define TOMTOM_A_RX_EAR_BIAS_PA__POR (0x76) +#define TOMTOM_A_RX_EAR_BIAS_CMBUFF (0x1BB) +#define TOMTOM_A_RX_EAR_BIAS_CMBUFF__POR (0xA0) +#define TOMTOM_A_RX_EAR_EN (0x1BC) +#define TOMTOM_A_RX_EAR_EN__POR (0x00) +#define TOMTOM_A_RX_EAR_GAIN (0x1BD) +#define TOMTOM_A_RX_EAR_GAIN__POR (0x02) +#define TOMTOM_A_RX_EAR_CMBUFF (0x1BE) +#define TOMTOM_A_RX_EAR_CMBUFF__POR (0x05) +#define TOMTOM_A_RX_EAR_ICTL (0x1BF) +#define TOMTOM_A_RX_EAR_ICTL__POR (0x40) +#define TOMTOM_A_RX_EAR_CCOMP (0x1C0) +#define TOMTOM_A_RX_EAR_CCOMP__POR (0x08) +#define TOMTOM_A_RX_EAR_VCM (0x1C1) +#define TOMTOM_A_RX_EAR_VCM__POR (0x03) +#define TOMTOM_A_RX_EAR_CNP (0x1C2) +#define TOMTOM_A_RX_EAR_CNP__POR (0xC0) +#define TOMTOM_A_RX_EAR_DAC_CTL_ATEST (0x1C3) +#define TOMTOM_A_RX_EAR_DAC_CTL_ATEST__POR (0x00) +#define TOMTOM_A_RX_EAR_STATUS (0x1C5) +#define TOMTOM_A_RX_EAR_STATUS__POR (0x04) +#define TOMTOM_A_RX_LINE_BIAS_PA (0x1C6) +#define TOMTOM_A_RX_LINE_BIAS_PA__POR (0x78) +#define TOMTOM_A_RX_BUCK_BIAS1 (0x1C7) +#define TOMTOM_A_RX_BUCK_BIAS1__POR (0x42) +#define TOMTOM_A_RX_BUCK_BIAS2 (0x1C8) +#define TOMTOM_A_RX_BUCK_BIAS2__POR (0x84) +#define TOMTOM_A_RX_LINE_COM (0x1C9) +#define TOMTOM_A_RX_LINE_COM__POR (0x80) +#define TOMTOM_A_RX_LINE_CNP_EN (0x1CA) +#define TOMTOM_A_RX_LINE_CNP_EN__POR (0x00) +#define TOMTOM_A_RX_LINE_CNP_WG_CTL (0x1CB) +#define TOMTOM_A_RX_LINE_CNP_WG_CTL__POR (0x00) +#define TOMTOM_A_RX_LINE_CNP_WG_TIME (0x1CC) +#define TOMTOM_A_RX_LINE_CNP_WG_TIME__POR (0x04) +#define TOMTOM_A_RX_LINE_1_GAIN (0x1CD) +#define TOMTOM_A_RX_LINE_1_GAIN__POR (0x00) +#define TOMTOM_A_RX_LINE_1_TEST (0x1CE) +#define TOMTOM_A_RX_LINE_1_TEST__POR (0x02) +#define TOMTOM_A_RX_LINE_1_DAC_CTL (0x1CF) +#define TOMTOM_A_RX_LINE_1_DAC_CTL__POR (0x00) +#define TOMTOM_A_RX_LINE_1_STATUS (0x1D0) +#define TOMTOM_A_RX_LINE_1_STATUS__POR (0x00) +#define TOMTOM_A_RX_LINE_2_GAIN (0x1D1) +#define TOMTOM_A_RX_LINE_2_GAIN__POR (0x00) +#define TOMTOM_A_RX_LINE_2_TEST (0x1D2) +#define TOMTOM_A_RX_LINE_2_TEST__POR (0x02) +#define TOMTOM_A_RX_LINE_2_DAC_CTL (0x1D3) +#define TOMTOM_A_RX_LINE_2_DAC_CTL__POR (0x00) +#define TOMTOM_A_RX_LINE_2_STATUS (0x1D4) +#define TOMTOM_A_RX_LINE_2_STATUS__POR (0x00) +#define TOMTOM_A_RX_LINE_3_GAIN (0x1D5) +#define TOMTOM_A_RX_LINE_3_GAIN__POR (0x00) +#define TOMTOM_A_RX_LINE_3_TEST (0x1D6) +#define TOMTOM_A_RX_LINE_3_TEST__POR (0x02) +#define TOMTOM_A_RX_LINE_3_DAC_CTL (0x1D7) +#define TOMTOM_A_RX_LINE_3_DAC_CTL__POR (0x00) +#define TOMTOM_A_RX_LINE_3_STATUS (0x1D8) +#define TOMTOM_A_RX_LINE_3_STATUS__POR (0x00) +#define TOMTOM_A_RX_LINE_4_GAIN (0x1D9) +#define TOMTOM_A_RX_LINE_4_GAIN__POR (0x00) +#define TOMTOM_A_RX_LINE_4_TEST (0x1DA) +#define TOMTOM_A_RX_LINE_4_TEST__POR (0x02) +#define TOMTOM_A_RX_LINE_4_DAC_CTL (0x1DB) +#define TOMTOM_A_RX_LINE_4_DAC_CTL__POR (0x00) +#define TOMTOM_A_RX_LINE_4_STATUS (0x1DC) +#define TOMTOM_A_RX_LINE_4_STATUS__POR (0x00) +#define TOMTOM_A_RX_LINE_CNP_DBG (0x1DD) +#define TOMTOM_A_RX_LINE_CNP_DBG__POR (0x00) +#define TOMTOM_A_SPKR_DRV1_EN (0x1DF) +#define TOMTOM_A_SPKR_DRV1_EN__POR (0x6F) +#define TOMTOM_A_SPKR_DRV1_GAIN (0x1E0) +#define TOMTOM_A_SPKR_DRV1_GAIN__POR (0x00) +#define TOMTOM_A_SPKR_DRV1_DAC_CTL (0x1E1) +#define TOMTOM_A_SPKR_DRV1_DAC_CTL__POR (0x04) +#define TOMTOM_A_SPKR_DRV1_OCP_CTL (0x1E2) +#define TOMTOM_A_SPKR_DRV1_OCP_CTL__POR (0x97) +#define TOMTOM_A_SPKR_DRV1_CLIP_DET (0x1E3) +#define TOMTOM_A_SPKR_DRV1_CLIP_DET__POR (0x01) +#define TOMTOM_A_SPKR_DRV1_IEC (0x1E4) +#define TOMTOM_A_SPKR_DRV1_IEC__POR (0x00) +#define TOMTOM_A_SPKR_DRV1_DBG_DAC (0x1E5) +#define TOMTOM_A_SPKR_DRV1_DBG_DAC__POR (0x05) +#define TOMTOM_A_SPKR_DRV1_DBG_PA (0x1E6) +#define TOMTOM_A_SPKR_DRV1_DBG_PA__POR (0x18) +#define TOMTOM_A_SPKR_DRV1_DBG_PWRSTG (0x1E7) +#define TOMTOM_A_SPKR_DRV1_DBG_PWRSTG__POR (0x00) +#define TOMTOM_A_SPKR_DRV1_BIAS_LDO (0x1E8) +#define TOMTOM_A_SPKR_DRV1_BIAS_LDO__POR (0x45) +#define TOMTOM_A_SPKR_DRV1_BIAS_INT (0x1E9) +#define TOMTOM_A_SPKR_DRV1_BIAS_INT__POR (0xA5) +#define TOMTOM_A_SPKR_DRV1_BIAS_PA (0x1EA) +#define TOMTOM_A_SPKR_DRV1_BIAS_PA__POR (0x55) +#define TOMTOM_A_SPKR_DRV1_STATUS_OCP (0x1EB) +#define TOMTOM_A_SPKR_DRV1_STATUS_OCP__POR (0x00) +#define TOMTOM_A_SPKR_DRV1_STATUS_PA (0x1EC) +#define TOMTOM_A_SPKR_DRV1_STATUS_PA__POR (0x00) +#define TOMTOM_A_SPKR1_PROT_EN (0x1ED) +#define TOMTOM_A_SPKR1_PROT_EN__POR (0x00) +#define TOMTOM_A_SPKR1_PROT_ADC_TEST_EN (0x1EE) +#define TOMTOM_A_SPKR1_PROT_ADC_TEST_EN__POR (0x44) +#define TOMTOM_A_SPKR1_PROT_ATEST (0x1EF) +#define TOMTOM_A_SPKR1_PROT_ATEST__POR (0x00) +#define TOMTOM_A_SPKR1_PROT_LDO_CTRL (0x1F0) +#define TOMTOM_A_SPKR1_PROT_LDO_CTRL__POR (0x00) +#define TOMTOM_A_SPKR1_PROT_ISENSE_CTRL (0x1F1) +#define TOMTOM_A_SPKR1_PROT_ISENSE_CTRL__POR (0x00) +#define TOMTOM_A_SPKR1_PROT_VSENSE_CTRL (0x1F2) +#define TOMTOM_A_SPKR1_PROT_VSENSE_CTRL__POR (0x00) +#define TOMTOM_A_SPKR2_PROT_EN (0x1F3) +#define TOMTOM_A_SPKR2_PROT_EN__POR (0x00) +#define TOMTOM_A_SPKR2_PROT_ADC_TEST_EN (0x1F4) +#define TOMTOM_A_SPKR2_PROT_ADC_TEST_EN__POR (0x44) +#define TOMTOM_A_SPKR2_PROT_ATEST (0x1F5) +#define TOMTOM_A_SPKR2_PROT_ATEST__POR (0x00) +#define TOMTOM_A_SPKR2_PROT_LDO_CTRL (0x1F6) +#define TOMTOM_A_SPKR2_PROT_LDO_CTRL__POR (0x00) +#define TOMTOM_A_SPKR2_PROT_ISENSE_CTRL (0x1F7) +#define TOMTOM_A_SPKR2_PROT_ISENSE_CTRL__POR (0x00) +#define TOMTOM_A_SPKR2_PROT_VSENSE_CTRL (0x1F8) +#define TOMTOM_A_SPKR2_PROT_VSENSE_CTRL__POR (0x00) +#define TOMTOM_A_MBHC_HPH (0x1FE) +#define TOMTOM_A_MBHC_HPH__POR (0x44) +#define TOMTOM_A_CDC_ANC1_B1_CTL (0x200) +#define TOMTOM_A_CDC_ANC1_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC2_B1_CTL (0x280) +#define TOMTOM_A_CDC_ANC2_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC1_SHIFT (0x201) +#define TOMTOM_A_CDC_ANC1_SHIFT__POR (0x00) +#define TOMTOM_A_CDC_ANC2_SHIFT (0x281) +#define TOMTOM_A_CDC_ANC2_SHIFT__POR (0x00) +#define TOMTOM_A_CDC_ANC1_IIR_B1_CTL (0x202) +#define TOMTOM_A_CDC_ANC1_IIR_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC2_IIR_B1_CTL (0x282) +#define TOMTOM_A_CDC_ANC2_IIR_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC1_IIR_B2_CTL (0x203) +#define TOMTOM_A_CDC_ANC1_IIR_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC2_IIR_B2_CTL (0x283) +#define TOMTOM_A_CDC_ANC2_IIR_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC1_IIR_B3_CTL (0x204) +#define TOMTOM_A_CDC_ANC1_IIR_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC2_IIR_B3_CTL (0x284) +#define TOMTOM_A_CDC_ANC2_IIR_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC1_LPF_B1_CTL (0x206) +#define TOMTOM_A_CDC_ANC1_LPF_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC2_LPF_B1_CTL (0x286) +#define TOMTOM_A_CDC_ANC2_LPF_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC1_LPF_B2_CTL (0x207) +#define TOMTOM_A_CDC_ANC1_LPF_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC2_LPF_B2_CTL (0x287) +#define TOMTOM_A_CDC_ANC2_LPF_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC1_SPARE (0x209) +#define TOMTOM_A_CDC_ANC1_SPARE__POR (0x00) +#define TOMTOM_A_CDC_ANC2_SPARE (0x289) +#define TOMTOM_A_CDC_ANC2_SPARE__POR (0x00) +#define TOMTOM_A_CDC_ANC1_SMLPF_CTL (0x20A) +#define TOMTOM_A_CDC_ANC1_SMLPF_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC2_SMLPF_CTL (0x28A) +#define TOMTOM_A_CDC_ANC2_SMLPF_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC1_DCFLT_CTL (0x20B) +#define TOMTOM_A_CDC_ANC1_DCFLT_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC2_DCFLT_CTL (0x28B) +#define TOMTOM_A_CDC_ANC2_DCFLT_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC1_GAIN_CTL (0x20C) +#define TOMTOM_A_CDC_ANC1_GAIN_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC2_GAIN_CTL (0x28C) +#define TOMTOM_A_CDC_ANC2_GAIN_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC1_B2_CTL (0x20D) +#define TOMTOM_A_CDC_ANC1_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_ANC2_B2_CTL (0x28D) +#define TOMTOM_A_CDC_ANC2_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_TX1_VOL_CTL_TIMER (0x220) +#define TOMTOM_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00) +#define TOMTOM_A_CDC_TX2_VOL_CTL_TIMER (0x228) +#define TOMTOM_A_CDC_TX2_VOL_CTL_TIMER__POR (0x00) +#define TOMTOM_A_CDC_TX3_VOL_CTL_TIMER (0x230) +#define TOMTOM_A_CDC_TX3_VOL_CTL_TIMER__POR (0x00) +#define TOMTOM_A_CDC_TX4_VOL_CTL_TIMER (0x238) +#define TOMTOM_A_CDC_TX4_VOL_CTL_TIMER__POR (0x00) +#define TOMTOM_A_CDC_TX5_VOL_CTL_TIMER (0x240) +#define TOMTOM_A_CDC_TX5_VOL_CTL_TIMER__POR (0x00) +#define TOMTOM_A_CDC_TX6_VOL_CTL_TIMER (0x248) +#define TOMTOM_A_CDC_TX6_VOL_CTL_TIMER__POR (0x00) +#define TOMTOM_A_CDC_TX7_VOL_CTL_TIMER (0x250) +#define TOMTOM_A_CDC_TX7_VOL_CTL_TIMER__POR (0x00) +#define TOMTOM_A_CDC_TX8_VOL_CTL_TIMER (0x258) +#define TOMTOM_A_CDC_TX8_VOL_CTL_TIMER__POR (0x00) +#define TOMTOM_A_CDC_TX9_VOL_CTL_TIMER (0x260) +#define TOMTOM_A_CDC_TX9_VOL_CTL_TIMER__POR (0x00) +#define TOMTOM_A_CDC_TX10_VOL_CTL_TIMER (0x268) +#define TOMTOM_A_CDC_TX10_VOL_CTL_TIMER__POR (0x00) +#define TOMTOM_A_CDC_TX1_VOL_CTL_GAIN (0x221) +#define TOMTOM_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00) +#define TOMTOM_A_CDC_TX2_VOL_CTL_GAIN (0x229) +#define TOMTOM_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00) +#define TOMTOM_A_CDC_TX3_VOL_CTL_GAIN (0x231) +#define TOMTOM_A_CDC_TX3_VOL_CTL_GAIN__POR (0x00) +#define TOMTOM_A_CDC_TX4_VOL_CTL_GAIN (0x239) +#define TOMTOM_A_CDC_TX4_VOL_CTL_GAIN__POR (0x00) +#define TOMTOM_A_CDC_TX5_VOL_CTL_GAIN (0x241) +#define TOMTOM_A_CDC_TX5_VOL_CTL_GAIN__POR (0x00) +#define TOMTOM_A_CDC_TX6_VOL_CTL_GAIN (0x249) +#define TOMTOM_A_CDC_TX6_VOL_CTL_GAIN__POR (0x00) +#define TOMTOM_A_CDC_TX7_VOL_CTL_GAIN (0x251) +#define TOMTOM_A_CDC_TX7_VOL_CTL_GAIN__POR (0x00) +#define TOMTOM_A_CDC_TX8_VOL_CTL_GAIN (0x259) +#define TOMTOM_A_CDC_TX8_VOL_CTL_GAIN__POR (0x00) +#define TOMTOM_A_CDC_TX9_VOL_CTL_GAIN (0x261) +#define TOMTOM_A_CDC_TX9_VOL_CTL_GAIN__POR (0x00) +#define TOMTOM_A_CDC_TX10_VOL_CTL_GAIN (0x269) +#define TOMTOM_A_CDC_TX10_VOL_CTL_GAIN__POR (0x00) +#define TOMTOM_A_CDC_TX1_VOL_CTL_CFG (0x222) +#define TOMTOM_A_CDC_TX1_VOL_CTL_CFG__POR (0x00) +#define TOMTOM_A_CDC_TX2_VOL_CTL_CFG (0x22A) +#define TOMTOM_A_CDC_TX2_VOL_CTL_CFG__POR (0x00) +#define TOMTOM_A_CDC_TX3_VOL_CTL_CFG (0x232) +#define TOMTOM_A_CDC_TX3_VOL_CTL_CFG__POR (0x00) +#define TOMTOM_A_CDC_TX4_VOL_CTL_CFG (0x23A) +#define TOMTOM_A_CDC_TX4_VOL_CTL_CFG__POR (0x00) +#define TOMTOM_A_CDC_TX5_VOL_CTL_CFG (0x242) +#define TOMTOM_A_CDC_TX5_VOL_CTL_CFG__POR (0x00) +#define TOMTOM_A_CDC_TX6_VOL_CTL_CFG (0x24A) +#define TOMTOM_A_CDC_TX6_VOL_CTL_CFG__POR (0x00) +#define TOMTOM_A_CDC_TX7_VOL_CTL_CFG (0x252) +#define TOMTOM_A_CDC_TX7_VOL_CTL_CFG__POR (0x00) +#define TOMTOM_A_CDC_TX8_VOL_CTL_CFG (0x25A) +#define TOMTOM_A_CDC_TX8_VOL_CTL_CFG__POR (0x00) +#define TOMTOM_A_CDC_TX9_VOL_CTL_CFG (0x262) +#define TOMTOM_A_CDC_TX9_VOL_CTL_CFG__POR (0x00) +#define TOMTOM_A_CDC_TX10_VOL_CTL_CFG (0x26A) +#define TOMTOM_A_CDC_TX10_VOL_CTL_CFG__POR (0x00) +#define TOMTOM_A_CDC_TX1_MUX_CTL (0x223) +#define TOMTOM_A_CDC_TX1_MUX_CTL__POR (0x48) +#define TOMTOM_A_CDC_TX2_MUX_CTL (0x22B) +#define TOMTOM_A_CDC_TX2_MUX_CTL__POR (0x48) +#define TOMTOM_A_CDC_TX3_MUX_CTL (0x233) +#define TOMTOM_A_CDC_TX3_MUX_CTL__POR (0x48) +#define TOMTOM_A_CDC_TX4_MUX_CTL (0x23B) +#define TOMTOM_A_CDC_TX4_MUX_CTL__POR (0x48) +#define TOMTOM_A_CDC_TX5_MUX_CTL (0x243) +#define TOMTOM_A_CDC_TX5_MUX_CTL__POR (0x48) +#define TOMTOM_A_CDC_TX6_MUX_CTL (0x24B) +#define TOMTOM_A_CDC_TX6_MUX_CTL__POR (0x48) +#define TOMTOM_A_CDC_TX7_MUX_CTL (0x253) +#define TOMTOM_A_CDC_TX7_MUX_CTL__POR (0x48) +#define TOMTOM_A_CDC_TX8_MUX_CTL (0x25B) +#define TOMTOM_A_CDC_TX8_MUX_CTL__POR (0x48) +#define TOMTOM_A_CDC_TX9_MUX_CTL (0x263) +#define TOMTOM_A_CDC_TX9_MUX_CTL__POR (0x48) +#define TOMTOM_A_CDC_TX10_MUX_CTL (0x26B) +#define TOMTOM_A_CDC_TX10_MUX_CTL__POR (0x48) +#define TOMTOM_A_CDC_TX1_CLK_FS_CTL (0x224) +#define TOMTOM_A_CDC_TX1_CLK_FS_CTL__POR (0x03) +#define TOMTOM_A_CDC_TX2_CLK_FS_CTL (0x22C) +#define TOMTOM_A_CDC_TX2_CLK_FS_CTL__POR (0x03) +#define TOMTOM_A_CDC_TX3_CLK_FS_CTL (0x234) +#define TOMTOM_A_CDC_TX3_CLK_FS_CTL__POR (0x03) +#define TOMTOM_A_CDC_TX4_CLK_FS_CTL (0x23C) +#define TOMTOM_A_CDC_TX4_CLK_FS_CTL__POR (0x03) +#define TOMTOM_A_CDC_TX5_CLK_FS_CTL (0x244) +#define TOMTOM_A_CDC_TX5_CLK_FS_CTL__POR (0x03) +#define TOMTOM_A_CDC_TX6_CLK_FS_CTL (0x24C) +#define TOMTOM_A_CDC_TX6_CLK_FS_CTL__POR (0x03) +#define TOMTOM_A_CDC_TX7_CLK_FS_CTL (0x254) +#define TOMTOM_A_CDC_TX7_CLK_FS_CTL__POR (0x03) +#define TOMTOM_A_CDC_TX8_CLK_FS_CTL (0x25C) +#define TOMTOM_A_CDC_TX8_CLK_FS_CTL__POR (0x03) +#define TOMTOM_A_CDC_TX9_CLK_FS_CTL (0x264) +#define TOMTOM_A_CDC_TX9_CLK_FS_CTL__POR (0x03) +#define TOMTOM_A_CDC_TX10_CLK_FS_CTL (0x26C) +#define TOMTOM_A_CDC_TX10_CLK_FS_CTL__POR (0x03) +#define TOMTOM_A_CDC_TX1_DMIC_CTL (0x225) +#define TOMTOM_A_CDC_TX1_DMIC_CTL__POR (0x00) +#define TOMTOM_A_CDC_TX2_DMIC_CTL (0x22D) +#define TOMTOM_A_CDC_TX2_DMIC_CTL__POR (0x00) +#define TOMTOM_A_CDC_TX3_DMIC_CTL (0x235) +#define TOMTOM_A_CDC_TX3_DMIC_CTL__POR (0x00) +#define TOMTOM_A_CDC_TX4_DMIC_CTL (0x23D) +#define TOMTOM_A_CDC_TX4_DMIC_CTL__POR (0x00) +#define TOMTOM_A_CDC_TX5_DMIC_CTL (0x245) +#define TOMTOM_A_CDC_TX5_DMIC_CTL__POR (0x00) +#define TOMTOM_A_CDC_TX6_DMIC_CTL (0x24D) +#define TOMTOM_A_CDC_TX6_DMIC_CTL__POR (0x00) +#define TOMTOM_A_CDC_TX7_DMIC_CTL (0x255) +#define TOMTOM_A_CDC_TX7_DMIC_CTL__POR (0x00) +#define TOMTOM_A_CDC_TX8_DMIC_CTL (0x25D) +#define TOMTOM_A_CDC_TX8_DMIC_CTL__POR (0x00) +#define TOMTOM_A_CDC_TX9_DMIC_CTL (0x265) +#define TOMTOM_A_CDC_TX9_DMIC_CTL__POR (0x00) +#define TOMTOM_A_CDC_TX10_DMIC_CTL (0x26D) +#define TOMTOM_A_CDC_TX10_DMIC_CTL__POR (0x00) +#define TOMTOM_A_CDC_SPKR_CLIPDET_VAL0 (0x270) +#define TOMTOM_A_CDC_SPKR_CLIPDET_VAL0__POR (0x00) +#define TOMTOM_A_CDC_SPKR_CLIPDET_VAL1 (0x271) +#define TOMTOM_A_CDC_SPKR_CLIPDET_VAL1__POR (0x00) +#define TOMTOM_A_CDC_SPKR_CLIPDET_VAL2 (0x272) +#define TOMTOM_A_CDC_SPKR_CLIPDET_VAL2__POR (0x00) +#define TOMTOM_A_CDC_SPKR_CLIPDET_VAL3 (0x273) +#define TOMTOM_A_CDC_SPKR_CLIPDET_VAL3__POR (0x00) +#define TOMTOM_A_CDC_SPKR_CLIPDET_VAL4 (0x274) +#define TOMTOM_A_CDC_SPKR_CLIPDET_VAL4__POR (0x00) +#define TOMTOM_A_CDC_SPKR_CLIPDET_VAL5 (0x275) +#define TOMTOM_A_CDC_SPKR_CLIPDET_VAL5__POR (0x00) +#define TOMTOM_A_CDC_SPKR_CLIPDET_VAL6 (0x276) +#define TOMTOM_A_CDC_SPKR_CLIPDET_VAL6__POR (0x00) +#define TOMTOM_A_CDC_SPKR_CLIPDET_VAL7 (0x277) +#define TOMTOM_A_CDC_SPKR_CLIPDET_VAL7__POR (0x00) +#define TOMTOM_A_CDC_DEBUG_B1_CTL (0x278) +#define TOMTOM_A_CDC_DEBUG_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_DEBUG_B2_CTL (0x279) +#define TOMTOM_A_CDC_DEBUG_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_DEBUG_B3_CTL (0x27A) +#define TOMTOM_A_CDC_DEBUG_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_DEBUG_B4_CTL (0x27B) +#define TOMTOM_A_CDC_DEBUG_B4_CTL__POR (0x00) +#define TOMTOM_A_CDC_DEBUG_B5_CTL (0x27C) +#define TOMTOM_A_CDC_DEBUG_B5_CTL__POR (0x00) +#define TOMTOM_A_CDC_DEBUG_B6_CTL (0x27D) +#define TOMTOM_A_CDC_DEBUG_B6_CTL__POR (0x00) +#define TOMTOM_A_CDC_DEBUG_B7_CTL (0x27E) +#define TOMTOM_A_CDC_DEBUG_B7_CTL__POR (0x00) +#define TOMTOM_A_CDC_SRC1_PDA_CFG (0x2A0) +#define TOMTOM_A_CDC_SRC1_PDA_CFG__POR (0x00) +#define TOMTOM_A_CDC_SRC2_PDA_CFG (0x2A8) +#define TOMTOM_A_CDC_SRC2_PDA_CFG__POR (0x00) +#define TOMTOM_A_CDC_SRC1_FS_CTL (0x2A1) +#define TOMTOM_A_CDC_SRC1_FS_CTL__POR (0x1B) +#define TOMTOM_A_CDC_SRC2_FS_CTL (0x2A9) +#define TOMTOM_A_CDC_SRC2_FS_CTL__POR (0x1B) +#define TOMTOM_A_CDC_RX1_B1_CTL (0x2B0) +#define TOMTOM_A_CDC_RX1_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX2_B1_CTL (0x2B8) +#define TOMTOM_A_CDC_RX2_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX3_B1_CTL (0x2C0) +#define TOMTOM_A_CDC_RX3_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX4_B1_CTL (0x2C8) +#define TOMTOM_A_CDC_RX4_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX5_B1_CTL (0x2D0) +#define TOMTOM_A_CDC_RX5_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX6_B1_CTL (0x2D8) +#define TOMTOM_A_CDC_RX6_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX7_B1_CTL (0x2E0) +#define TOMTOM_A_CDC_RX7_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX1_B2_CTL (0x2B1) +#define TOMTOM_A_CDC_RX1_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX2_B2_CTL (0x2B9) +#define TOMTOM_A_CDC_RX2_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX3_B2_CTL (0x2C1) +#define TOMTOM_A_CDC_RX3_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX4_B2_CTL (0x2C9) +#define TOMTOM_A_CDC_RX4_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX5_B2_CTL (0x2D1) +#define TOMTOM_A_CDC_RX5_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX6_B2_CTL (0x2D9) +#define TOMTOM_A_CDC_RX6_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX7_B2_CTL (0x2E1) +#define TOMTOM_A_CDC_RX7_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX1_B3_CTL (0x2B2) +#define TOMTOM_A_CDC_RX1_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX2_B3_CTL (0x2BA) +#define TOMTOM_A_CDC_RX2_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX3_B3_CTL (0x2C2) +#define TOMTOM_A_CDC_RX3_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX4_B3_CTL (0x2CA) +#define TOMTOM_A_CDC_RX4_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX5_B3_CTL (0x2D2) +#define TOMTOM_A_CDC_RX5_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX6_B3_CTL (0x2DA) +#define TOMTOM_A_CDC_RX6_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX7_B3_CTL (0x2E2) +#define TOMTOM_A_CDC_RX7_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX1_B4_CTL (0x2B3) +#define TOMTOM_A_CDC_RX1_B4_CTL__POR (0x0B) +#define TOMTOM_A_CDC_RX2_B4_CTL (0x2BB) +#define TOMTOM_A_CDC_RX2_B4_CTL__POR (0x0B) +#define TOMTOM_A_CDC_RX3_B4_CTL (0x2C3) +#define TOMTOM_A_CDC_RX3_B4_CTL__POR (0x0B) +#define TOMTOM_A_CDC_RX4_B4_CTL (0x2CB) +#define TOMTOM_A_CDC_RX4_B4_CTL__POR (0x0B) +#define TOMTOM_A_CDC_RX5_B4_CTL (0x2D3) +#define TOMTOM_A_CDC_RX5_B4_CTL__POR (0x0B) +#define TOMTOM_A_CDC_RX6_B4_CTL (0x2DB) +#define TOMTOM_A_CDC_RX6_B4_CTL__POR (0x0B) +#define TOMTOM_A_CDC_RX7_B4_CTL (0x2E3) +#define TOMTOM_A_CDC_RX7_B4_CTL__POR (0x0B) +#define TOMTOM_A_CDC_RX1_B5_CTL (0x2B4) +#define TOMTOM_A_CDC_RX1_B5_CTL__POR (0x78) +#define TOMTOM_A_CDC_RX2_B5_CTL (0x2BC) +#define TOMTOM_A_CDC_RX2_B5_CTL__POR (0x78) +#define TOMTOM_A_CDC_RX3_B5_CTL (0x2C4) +#define TOMTOM_A_CDC_RX3_B5_CTL__POR (0x78) +#define TOMTOM_A_CDC_RX4_B5_CTL (0x2CC) +#define TOMTOM_A_CDC_RX4_B5_CTL__POR (0x78) +#define TOMTOM_A_CDC_RX5_B5_CTL (0x2D4) +#define TOMTOM_A_CDC_RX5_B5_CTL__POR (0x78) +#define TOMTOM_A_CDC_RX6_B5_CTL (0x2DC) +#define TOMTOM_A_CDC_RX6_B5_CTL__POR (0x78) +#define TOMTOM_A_CDC_RX7_B5_CTL (0x2E4) +#define TOMTOM_A_CDC_RX7_B5_CTL__POR (0x78) +#define TOMTOM_A_CDC_RX1_B6_CTL (0x2B5) +#define TOMTOM_A_CDC_RX1_B6_CTL__POR (0x80) +#define TOMTOM_A_CDC_RX2_B6_CTL (0x2BD) +#define TOMTOM_A_CDC_RX2_B6_CTL__POR (0x80) +#define TOMTOM_A_CDC_RX3_B6_CTL (0x2C5) +#define TOMTOM_A_CDC_RX3_B6_CTL__POR (0x80) +#define TOMTOM_A_CDC_RX4_B6_CTL (0x2CD) +#define TOMTOM_A_CDC_RX4_B6_CTL__POR (0x80) +#define TOMTOM_A_CDC_RX5_B6_CTL (0x2D5) +#define TOMTOM_A_CDC_RX5_B6_CTL__POR (0x80) +#define TOMTOM_A_CDC_RX6_B6_CTL (0x2DD) +#define TOMTOM_A_CDC_RX6_B6_CTL__POR (0x80) +#define TOMTOM_A_CDC_RX7_B6_CTL (0x2E5) +#define TOMTOM_A_CDC_RX7_B6_CTL__POR (0x80) +#define TOMTOM_A_CDC_RX1_VOL_CTL_B1_CTL (0x2B6) +#define TOMTOM_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX2_VOL_CTL_B1_CTL (0x2BE) +#define TOMTOM_A_CDC_RX2_VOL_CTL_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX3_VOL_CTL_B1_CTL (0x2C6) +#define TOMTOM_A_CDC_RX3_VOL_CTL_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX4_VOL_CTL_B1_CTL (0x2CE) +#define TOMTOM_A_CDC_RX4_VOL_CTL_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX5_VOL_CTL_B1_CTL (0x2D6) +#define TOMTOM_A_CDC_RX5_VOL_CTL_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX6_VOL_CTL_B1_CTL (0x2DE) +#define TOMTOM_A_CDC_RX6_VOL_CTL_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX7_VOL_CTL_B1_CTL (0x2E6) +#define TOMTOM_A_CDC_RX7_VOL_CTL_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX1_VOL_CTL_B2_CTL (0x2B7) +#define TOMTOM_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX2_VOL_CTL_B2_CTL (0x2BF) +#define TOMTOM_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX3_VOL_CTL_B2_CTL (0x2C7) +#define TOMTOM_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX4_VOL_CTL_B2_CTL (0x2CF) +#define TOMTOM_A_CDC_RX4_VOL_CTL_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX5_VOL_CTL_B2_CTL (0x2D7) +#define TOMTOM_A_CDC_RX5_VOL_CTL_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX6_VOL_CTL_B2_CTL (0x2DF) +#define TOMTOM_A_CDC_RX6_VOL_CTL_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX7_VOL_CTL_B2_CTL (0x2E7) +#define TOMTOM_A_CDC_RX7_VOL_CTL_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_VBAT_CFG (0x2E8) +#define TOMTOM_A_CDC_VBAT_CFG__POR (0x1A) +#define TOMTOM_A_CDC_VBAT_ADC_CAL1 (0x2E9) +#define TOMTOM_A_CDC_VBAT_ADC_CAL1__POR (0x00) +#define TOMTOM_A_CDC_VBAT_ADC_CAL2 (0x2EA) +#define TOMTOM_A_CDC_VBAT_ADC_CAL2__POR (0x00) +#define TOMTOM_A_CDC_VBAT_ADC_CAL3 (0x2EB) +#define TOMTOM_A_CDC_VBAT_ADC_CAL3__POR (0x04) +#define TOMTOM_A_CDC_VBAT_PK_EST1 (0x2EC) +#define TOMTOM_A_CDC_VBAT_PK_EST1__POR (0xE0) +#define TOMTOM_A_CDC_VBAT_PK_EST2 (0x2ED) +#define TOMTOM_A_CDC_VBAT_PK_EST2__POR (0x01) +#define TOMTOM_A_CDC_VBAT_PK_EST3 (0x2EE) +#define TOMTOM_A_CDC_VBAT_PK_EST3__POR (0x40) +#define TOMTOM_A_CDC_VBAT_RF_PROC1 (0x2EF) +#define TOMTOM_A_CDC_VBAT_RF_PROC1__POR (0x2A) +#define TOMTOM_A_CDC_VBAT_RF_PROC2 (0x2F0) +#define TOMTOM_A_CDC_VBAT_RF_PROC2__POR (0x86) +#define TOMTOM_A_CDC_VBAT_TAC1 (0x2F1) +#define TOMTOM_A_CDC_VBAT_TAC1__POR (0x70) +#define TOMTOM_A_CDC_VBAT_TAC2 (0x2F2) +#define TOMTOM_A_CDC_VBAT_TAC2__POR (0x18) +#define TOMTOM_A_CDC_VBAT_TAC3 (0x2F3) +#define TOMTOM_A_CDC_VBAT_TAC3__POR (0x18) +#define TOMTOM_A_CDC_VBAT_TAC4 (0x2F4) +#define TOMTOM_A_CDC_VBAT_TAC4__POR (0x03) +#define TOMTOM_A_CDC_VBAT_GAIN_UPD1 (0x2F5) +#define TOMTOM_A_CDC_VBAT_GAIN_UPD1__POR (0x01) +#define TOMTOM_A_CDC_VBAT_GAIN_UPD2 (0x2F6) +#define TOMTOM_A_CDC_VBAT_GAIN_UPD2__POR (0x00) +#define TOMTOM_A_CDC_VBAT_GAIN_UPD3 (0x2F7) +#define TOMTOM_A_CDC_VBAT_GAIN_UPD3__POR (0x64) +#define TOMTOM_A_CDC_VBAT_GAIN_UPD4 (0x2F8) +#define TOMTOM_A_CDC_VBAT_GAIN_UPD4__POR (0x01) +#define TOMTOM_A_CDC_VBAT_DEBUG1 (0x2F9) +#define TOMTOM_A_CDC_VBAT_DEBUG1__POR (0x00) +#define TOMTOM_A_CDC_VBAT_GAIN_UPD_MON (0x2FA) +#define TOMTOM_A_CDC_VBAT_GAIN_UPD_MON__POR (0x00) +#define TOMTOM_A_CDC_VBAT_GAIN_MON_VAL (0x2FB) +#define TOMTOM_A_CDC_VBAT_GAIN_MON_VAL__POR (0x00) +#define TOMTOM_A_CDC_CLK_ANC_RESET_CTL (0x300) +#define TOMTOM_A_CDC_CLK_ANC_RESET_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLK_RX_RESET_CTL (0x301) +#define TOMTOM_A_CDC_CLK_RX_RESET_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLK_TX_RESET_B1_CTL (0x302) +#define TOMTOM_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLK_TX_RESET_B2_CTL (0x303) +#define TOMTOM_A_CDC_CLK_TX_RESET_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLK_RX_I2S_CTL (0x306) +#define TOMTOM_A_CDC_CLK_RX_I2S_CTL__POR (0x03) +#define TOMTOM_A_CDC_CLK_TX_I2S_CTL (0x307) +#define TOMTOM_A_CDC_CLK_TX_I2S_CTL__POR (0x03) +#define TOMTOM_A_CDC_CLK_OTHR_RESET_B1_CTL (0x308) +#define TOMTOM_A_CDC_CLK_OTHR_RESET_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLK_OTHR_RESET_B2_CTL (0x309) +#define TOMTOM_A_CDC_CLK_OTHR_RESET_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x30A) +#define TOMTOM_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLK_TX_CLK_EN_B2_CTL (0x30B) +#define TOMTOM_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLK_OTHR_CTL (0x30C) +#define TOMTOM_A_CDC_CLK_OTHR_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLK_ANC_CLK_EN_CTL (0x30E) +#define TOMTOM_A_CDC_CLK_ANC_CLK_EN_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLK_RX_B1_CTL (0x30F) +#define TOMTOM_A_CDC_CLK_RX_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLK_RX_B2_CTL (0x310) +#define TOMTOM_A_CDC_CLK_RX_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLK_MCLK_CTL (0x311) +#define TOMTOM_A_CDC_CLK_MCLK_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLK_PDM_CTL (0x312) +#define TOMTOM_A_CDC_CLK_PDM_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLK_SD_CTL (0x313) +#define TOMTOM_A_CDC_CLK_SD_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLSH_B1_CTL (0x320) +#define TOMTOM_A_CDC_CLSH_B1_CTL__POR (0xE4) +#define TOMTOM_A_CDC_CLSH_B2_CTL (0x321) +#define TOMTOM_A_CDC_CLSH_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLSH_B3_CTL (0x322) +#define TOMTOM_A_CDC_CLSH_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLSH_BUCK_NCP_VARS (0x323) +#define TOMTOM_A_CDC_CLSH_BUCK_NCP_VARS__POR (0x00) +#define TOMTOM_A_CDC_CLSH_IDLE_HPH_THSD (0x324) +#define TOMTOM_A_CDC_CLSH_IDLE_HPH_THSD__POR (0x12) +#define TOMTOM_A_CDC_CLSH_IDLE_EAR_THSD (0x325) +#define TOMTOM_A_CDC_CLSH_IDLE_EAR_THSD__POR (0x0C) +#define TOMTOM_A_CDC_CLSH_FCLKONLY_HPH_THSD (0x326) +#define TOMTOM_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR (0x18) +#define TOMTOM_A_CDC_CLSH_FCLKONLY_EAR_THSD (0x327) +#define TOMTOM_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR (0x23) +#define TOMTOM_A_CDC_CLSH_K_ADDR (0x328) +#define TOMTOM_A_CDC_CLSH_K_ADDR__POR (0x00) +#define TOMTOM_A_CDC_CLSH_K_DATA (0x329) +#define TOMTOM_A_CDC_CLSH_K_DATA__POR (0xA4) +#define TOMTOM_A_CDC_CLSH_I_PA_FACT_HPH_L (0x32A) +#define TOMTOM_A_CDC_CLSH_I_PA_FACT_HPH_L__POR (0xD7) +#define TOMTOM_A_CDC_CLSH_I_PA_FACT_HPH_U (0x32B) +#define TOMTOM_A_CDC_CLSH_I_PA_FACT_HPH_U__POR (0x05) +#define TOMTOM_A_CDC_CLSH_I_PA_FACT_EAR_L (0x32C) +#define TOMTOM_A_CDC_CLSH_I_PA_FACT_EAR_L__POR (0x60) +#define TOMTOM_A_CDC_CLSH_I_PA_FACT_EAR_U (0x32D) +#define TOMTOM_A_CDC_CLSH_I_PA_FACT_EAR_U__POR (0x09) +#define TOMTOM_A_CDC_CLSH_V_PA_HD_EAR (0x32E) +#define TOMTOM_A_CDC_CLSH_V_PA_HD_EAR__POR (0x00) +#define TOMTOM_A_CDC_CLSH_V_PA_HD_HPH (0x32F) +#define TOMTOM_A_CDC_CLSH_V_PA_HD_HPH__POR (0x00) +#define TOMTOM_A_CDC_CLSH_V_PA_MIN_EAR (0x330) +#define TOMTOM_A_CDC_CLSH_V_PA_MIN_EAR__POR (0x00) +#define TOMTOM_A_CDC_CLSH_V_PA_MIN_HPH (0x331) +#define TOMTOM_A_CDC_CLSH_V_PA_MIN_HPH__POR (0x00) +#define TOMTOM_A_CDC_IIR1_GAIN_B1_CTL (0x340) +#define TOMTOM_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR2_GAIN_B1_CTL (0x350) +#define TOMTOM_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR1_GAIN_B2_CTL (0x341) +#define TOMTOM_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR2_GAIN_B2_CTL (0x351) +#define TOMTOM_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR1_GAIN_B3_CTL (0x342) +#define TOMTOM_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR2_GAIN_B3_CTL (0x352) +#define TOMTOM_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR1_GAIN_B4_CTL (0x343) +#define TOMTOM_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR2_GAIN_B4_CTL (0x353) +#define TOMTOM_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR1_GAIN_B5_CTL (0x344) +#define TOMTOM_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR2_GAIN_B5_CTL (0x354) +#define TOMTOM_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR1_GAIN_B6_CTL (0x345) +#define TOMTOM_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR2_GAIN_B6_CTL (0x355) +#define TOMTOM_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR1_GAIN_B7_CTL (0x346) +#define TOMTOM_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR2_GAIN_B7_CTL (0x356) +#define TOMTOM_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR1_GAIN_B8_CTL (0x347) +#define TOMTOM_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR2_GAIN_B8_CTL (0x357) +#define TOMTOM_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR1_CTL (0x348) +#define TOMTOM_A_CDC_IIR1_CTL__POR (0x40) +#define TOMTOM_A_CDC_IIR2_CTL (0x358) +#define TOMTOM_A_CDC_IIR2_CTL__POR (0x40) +#define TOMTOM_A_CDC_IIR1_GAIN_TIMER_CTL (0x349) +#define TOMTOM_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR2_GAIN_TIMER_CTL (0x359) +#define TOMTOM_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR1_COEF_B1_CTL (0x34A) +#define TOMTOM_A_CDC_IIR1_COEF_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR2_COEF_B1_CTL (0x35A) +#define TOMTOM_A_CDC_IIR2_COEF_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR1_COEF_B2_CTL (0x34B) +#define TOMTOM_A_CDC_IIR1_COEF_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_IIR2_COEF_B2_CTL (0x35B) +#define TOMTOM_A_CDC_IIR2_COEF_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_TOP_GAIN_UPDATE (0x360) +#define TOMTOM_A_CDC_TOP_GAIN_UPDATE__POR (0x00) +#define TOMTOM_A_CDC_PA_RAMP_B1_CTL (0x361) +#define TOMTOM_A_CDC_PA_RAMP_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_PA_RAMP_B2_CTL (0x362) +#define TOMTOM_A_CDC_PA_RAMP_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_PA_RAMP_B3_CTL (0x363) +#define TOMTOM_A_CDC_PA_RAMP_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_PA_RAMP_B4_CTL (0x364) +#define TOMTOM_A_CDC_PA_RAMP_B4_CTL__POR (0x00) +#define TOMTOM_A_CDC_SPKR_CLIPDET_B1_CTL (0x365) +#define TOMTOM_A_CDC_SPKR_CLIPDET_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_B1_CTL (0x366) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_COMP0_B1_CTL (0x368) +#define TOMTOM_A_CDC_COMP0_B1_CTL__POR (0x30) +#define TOMTOM_A_CDC_COMP1_B1_CTL (0x370) +#define TOMTOM_A_CDC_COMP1_B1_CTL__POR (0x30) +#define TOMTOM_A_CDC_COMP2_B1_CTL (0x378) +#define TOMTOM_A_CDC_COMP2_B1_CTL__POR (0x30) +#define TOMTOM_A_CDC_COMP0_B2_CTL (0x369) +#define TOMTOM_A_CDC_COMP0_B2_CTL__POR (0xB5) +#define TOMTOM_A_CDC_COMP1_B2_CTL (0x371) +#define TOMTOM_A_CDC_COMP1_B2_CTL__POR (0xB5) +#define TOMTOM_A_CDC_COMP2_B2_CTL (0x379) +#define TOMTOM_A_CDC_COMP2_B2_CTL__POR (0xB5) +#define TOMTOM_A_CDC_COMP0_B3_CTL (0x36A) +#define TOMTOM_A_CDC_COMP0_B3_CTL__POR (0x28) +#define TOMTOM_A_CDC_COMP1_B3_CTL (0x372) +#define TOMTOM_A_CDC_COMP1_B3_CTL__POR (0x28) +#define TOMTOM_A_CDC_COMP2_B3_CTL (0x37A) +#define TOMTOM_A_CDC_COMP2_B3_CTL__POR (0x28) +#define TOMTOM_A_CDC_COMP0_B4_CTL (0x36B) +#define TOMTOM_A_CDC_COMP0_B4_CTL__POR (0x37) +#define TOMTOM_A_CDC_COMP1_B4_CTL (0x373) +#define TOMTOM_A_CDC_COMP1_B4_CTL__POR (0x37) +#define TOMTOM_A_CDC_COMP2_B4_CTL (0x37B) +#define TOMTOM_A_CDC_COMP2_B4_CTL__POR (0x37) +#define TOMTOM_A_CDC_COMP0_B5_CTL (0x36C) +#define TOMTOM_A_CDC_COMP0_B5_CTL__POR (0x7F) +#define TOMTOM_A_CDC_COMP1_B5_CTL (0x374) +#define TOMTOM_A_CDC_COMP1_B5_CTL__POR (0x7F) +#define TOMTOM_A_CDC_COMP2_B5_CTL (0x37C) +#define TOMTOM_A_CDC_COMP2_B5_CTL__POR (0x7F) +#define TOMTOM_A_CDC_COMP0_B6_CTL (0x36D) +#define TOMTOM_A_CDC_COMP0_B6_CTL__POR (0x00) +#define TOMTOM_A_CDC_COMP1_B6_CTL (0x375) +#define TOMTOM_A_CDC_COMP1_B6_CTL__POR (0x00) +#define TOMTOM_A_CDC_COMP2_B6_CTL (0x37D) +#define TOMTOM_A_CDC_COMP2_B6_CTL__POR (0x00) +#define TOMTOM_A_CDC_COMP0_SHUT_DOWN_STATUS (0x36E) +#define TOMTOM_A_CDC_COMP0_SHUT_DOWN_STATUS__POR (0x03) +#define TOMTOM_A_CDC_COMP1_SHUT_DOWN_STATUS (0x376) +#define TOMTOM_A_CDC_COMP1_SHUT_DOWN_STATUS__POR (0x03) +#define TOMTOM_A_CDC_COMP2_SHUT_DOWN_STATUS (0x37E) +#define TOMTOM_A_CDC_COMP2_SHUT_DOWN_STATUS__POR (0x03) +#define TOMTOM_A_CDC_COMP0_FS_CFG (0x36F) +#define TOMTOM_A_CDC_COMP0_FS_CFG__POR (0x03) +#define TOMTOM_A_CDC_COMP1_FS_CFG (0x377) +#define TOMTOM_A_CDC_COMP1_FS_CFG__POR (0x03) +#define TOMTOM_A_CDC_COMP2_FS_CFG (0x37F) +#define TOMTOM_A_CDC_COMP2_FS_CFG__POR (0x03) +#define TOMTOM_A_CDC_CONN_RX1_B1_CTL (0x380) +#define TOMTOM_A_CDC_CONN_RX1_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX1_B2_CTL (0x381) +#define TOMTOM_A_CDC_CONN_RX1_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX1_B3_CTL (0x382) +#define TOMTOM_A_CDC_CONN_RX1_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX2_B1_CTL (0x383) +#define TOMTOM_A_CDC_CONN_RX2_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX2_B2_CTL (0x384) +#define TOMTOM_A_CDC_CONN_RX2_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX2_B3_CTL (0x385) +#define TOMTOM_A_CDC_CONN_RX2_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX3_B1_CTL (0x386) +#define TOMTOM_A_CDC_CONN_RX3_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX3_B2_CTL (0x387) +#define TOMTOM_A_CDC_CONN_RX3_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX4_B1_CTL (0x388) +#define TOMTOM_A_CDC_CONN_RX4_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX4_B2_CTL (0x389) +#define TOMTOM_A_CDC_CONN_RX4_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX5_B1_CTL (0x38A) +#define TOMTOM_A_CDC_CONN_RX5_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX5_B2_CTL (0x38B) +#define TOMTOM_A_CDC_CONN_RX5_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX6_B1_CTL (0x38C) +#define TOMTOM_A_CDC_CONN_RX6_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX6_B2_CTL (0x38D) +#define TOMTOM_A_CDC_CONN_RX6_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX7_B1_CTL (0x38E) +#define TOMTOM_A_CDC_CONN_RX7_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX7_B2_CTL (0x38F) +#define TOMTOM_A_CDC_CONN_RX7_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX7_B3_CTL (0x390) +#define TOMTOM_A_CDC_CONN_RX7_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_ANC_B1_CTL (0x391) +#define TOMTOM_A_CDC_CONN_ANC_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_ANC_B2_CTL (0x392) +#define TOMTOM_A_CDC_CONN_ANC_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_TX_B1_CTL (0x393) +#define TOMTOM_A_CDC_CONN_TX_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_TX_B2_CTL (0x394) +#define TOMTOM_A_CDC_CONN_TX_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_TX_B3_CTL (0x395) +#define TOMTOM_A_CDC_CONN_TX_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_TX_B4_CTL (0x396) +#define TOMTOM_A_CDC_CONN_TX_B4_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_EQ1_B1_CTL (0x397) +#define TOMTOM_A_CDC_CONN_EQ1_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_EQ1_B2_CTL (0x398) +#define TOMTOM_A_CDC_CONN_EQ1_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_EQ1_B3_CTL (0x399) +#define TOMTOM_A_CDC_CONN_EQ1_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_EQ1_B4_CTL (0x39A) +#define TOMTOM_A_CDC_CONN_EQ1_B4_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_EQ2_B1_CTL (0x39B) +#define TOMTOM_A_CDC_CONN_EQ2_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_EQ2_B2_CTL (0x39C) +#define TOMTOM_A_CDC_CONN_EQ2_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_EQ2_B3_CTL (0x39D) +#define TOMTOM_A_CDC_CONN_EQ2_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_EQ2_B4_CTL (0x39E) +#define TOMTOM_A_CDC_CONN_EQ2_B4_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_SRC1_B1_CTL (0x39F) +#define TOMTOM_A_CDC_CONN_SRC1_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_SRC1_B2_CTL (0x3A0) +#define TOMTOM_A_CDC_CONN_SRC1_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_SRC2_B1_CTL (0x3A1) +#define TOMTOM_A_CDC_CONN_SRC2_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_SRC2_B2_CTL (0x3A2) +#define TOMTOM_A_CDC_CONN_SRC2_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_TX_SB_B1_CTL (0x3A3) +#define TOMTOM_A_CDC_CONN_TX_SB_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_TX_SB_B2_CTL (0x3A4) +#define TOMTOM_A_CDC_CONN_TX_SB_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_TX_SB_B3_CTL (0x3A5) +#define TOMTOM_A_CDC_CONN_TX_SB_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_TX_SB_B4_CTL (0x3A6) +#define TOMTOM_A_CDC_CONN_TX_SB_B4_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_TX_SB_B5_CTL (0x3A7) +#define TOMTOM_A_CDC_CONN_TX_SB_B5_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_TX_SB_B6_CTL (0x3A8) +#define TOMTOM_A_CDC_CONN_TX_SB_B6_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_TX_SB_B7_CTL (0x3A9) +#define TOMTOM_A_CDC_CONN_TX_SB_B7_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_TX_SB_B8_CTL (0x3AA) +#define TOMTOM_A_CDC_CONN_TX_SB_B8_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_TX_SB_B9_CTL (0x3AB) +#define TOMTOM_A_CDC_CONN_TX_SB_B9_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_TX_SB_B10_CTL (0x3AC) +#define TOMTOM_A_CDC_CONN_TX_SB_B10_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_TX_SB_B11_CTL (0x3AD) +#define TOMTOM_A_CDC_CONN_TX_SB_B11_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX_SB_B1_CTL (0x3AE) +#define TOMTOM_A_CDC_CONN_RX_SB_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_RX_SB_B2_CTL (0x3AF) +#define TOMTOM_A_CDC_CONN_RX_SB_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_CLSH_CTL (0x3B0) +#define TOMTOM_A_CDC_CONN_CLSH_CTL__POR (0x00) +#define TOMTOM_A_CDC_CONN_MISC (0x3B1) +#define TOMTOM_A_CDC_CONN_MISC__POR (0x01) +#define TOMTOM_A_CDC_CONN_RX8_B1_CTL (0x3B3) +#define TOMTOM_A_CDC_CONN_RX8_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR_B1_CTL (0x3B4) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR_B1_CTL__POR (0x81) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR_CLIP_LEVEL_ADJUST (0x3B5) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR_CLIP_LEVEL_ADJUST__POR (0x00) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR_MIN_CLIP_THRESHOLD (0x3B6) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR_MIN_CLIP_THRESHOLD__POR (0xFF) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR_THRESHOLD_STATUS (0x3B7) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR_THRESHOLD_STATUS__POR (0x00) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR_SAMPLE_MARK (0x3B8) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR_SAMPLE_MARK__POR (0x04) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR_BOOST_GATING (0x3B9) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR_BOOST_GATING__POR (0x04) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR2_B1_CTL (0x3BA) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR2_B1_CTL__POR (0x81) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR2_CLIP_LEVEL_ADJUST (0x3BB) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR2_CLIP_LEVEL_ADJUST__POR (0x00) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR2_MIN_CLIP_THRESHOLD (0x3BC) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR2_MIN_CLIP_THRESHOLD__POR (0xFF) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR2_THRESHOLD_STATUS (0x3BD) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR2_THRESHOLD_STATUS__POR (0x00) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR2_SAMPLE_MARK (0x3BE) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR2_SAMPLE_MARK__POR (0x04) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR2_BOOST_GATING (0x3BF) +#define TOMTOM_A_CDC_CLIP_ADJ_SPKR2_BOOST_GATING__POR (0x04) +#define TOMTOM_A_CDC_MBHC_EN_CTL (0x3C0) +#define TOMTOM_A_CDC_MBHC_EN_CTL__POR (0x00) +#define TOMTOM_A_CDC_MBHC_FIR_B1_CFG (0x3C1) +#define TOMTOM_A_CDC_MBHC_FIR_B1_CFG__POR (0x00) +#define TOMTOM_A_CDC_MBHC_FIR_B2_CFG (0x3C2) +#define TOMTOM_A_CDC_MBHC_FIR_B2_CFG__POR (0x06) +#define TOMTOM_A_CDC_MBHC_TIMER_B1_CTL (0x3C3) +#define TOMTOM_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03) +#define TOMTOM_A_CDC_MBHC_TIMER_B2_CTL (0x3C4) +#define TOMTOM_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09) +#define TOMTOM_A_CDC_MBHC_TIMER_B3_CTL (0x3C5) +#define TOMTOM_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E) +#define TOMTOM_A_CDC_MBHC_TIMER_B4_CTL (0x3C6) +#define TOMTOM_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45) +#define TOMTOM_A_CDC_MBHC_TIMER_B5_CTL (0x3C7) +#define TOMTOM_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04) +#define TOMTOM_A_CDC_MBHC_TIMER_B6_CTL (0x3C8) +#define TOMTOM_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78) +#define TOMTOM_A_CDC_MBHC_B1_STATUS (0x3C9) +#define TOMTOM_A_CDC_MBHC_B1_STATUS__POR (0x00) +#define TOMTOM_A_CDC_MBHC_B2_STATUS (0x3CA) +#define TOMTOM_A_CDC_MBHC_B2_STATUS__POR (0x00) +#define TOMTOM_A_CDC_MBHC_B3_STATUS (0x3CB) +#define TOMTOM_A_CDC_MBHC_B3_STATUS__POR (0x00) +#define TOMTOM_A_CDC_MBHC_B4_STATUS (0x3CC) +#define TOMTOM_A_CDC_MBHC_B4_STATUS__POR (0x00) +#define TOMTOM_A_CDC_MBHC_B5_STATUS (0x3CD) +#define TOMTOM_A_CDC_MBHC_B5_STATUS__POR (0x00) +#define TOMTOM_A_CDC_MBHC_B1_CTL (0x3CE) +#define TOMTOM_A_CDC_MBHC_B1_CTL__POR (0xC0) +#define TOMTOM_A_CDC_MBHC_B2_CTL (0x3CF) +#define TOMTOM_A_CDC_MBHC_B2_CTL__POR (0x5D) +#define TOMTOM_A_CDC_MBHC_VOLT_B1_CTL (0x3D0) +#define TOMTOM_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_MBHC_VOLT_B2_CTL (0x3D1) +#define TOMTOM_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_MBHC_VOLT_B3_CTL (0x3D2) +#define TOMTOM_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_MBHC_VOLT_B4_CTL (0x3D3) +#define TOMTOM_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00) +#define TOMTOM_A_CDC_MBHC_VOLT_B5_CTL (0x3D4) +#define TOMTOM_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00) +#define TOMTOM_A_CDC_MBHC_VOLT_B6_CTL (0x3D5) +#define TOMTOM_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00) +#define TOMTOM_A_CDC_MBHC_VOLT_B7_CTL (0x3D6) +#define TOMTOM_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF) +#define TOMTOM_A_CDC_MBHC_VOLT_B8_CTL (0x3D7) +#define TOMTOM_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07) +#define TOMTOM_A_CDC_MBHC_VOLT_B9_CTL (0x3D8) +#define TOMTOM_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF) +#define TOMTOM_A_CDC_MBHC_VOLT_B10_CTL (0x3D9) +#define TOMTOM_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F) +#define TOMTOM_A_CDC_MBHC_VOLT_B11_CTL (0x3DA) +#define TOMTOM_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00) +#define TOMTOM_A_CDC_MBHC_VOLT_B12_CTL (0x3DB) +#define TOMTOM_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80) +#define TOMTOM_A_CDC_MBHC_CLK_CTL (0x3DC) +#define TOMTOM_A_CDC_MBHC_CLK_CTL__POR (0x00) +#define TOMTOM_A_CDC_MBHC_INT_CTL (0x3DD) +#define TOMTOM_A_CDC_MBHC_INT_CTL__POR (0x00) +#define TOMTOM_A_CDC_MBHC_DEBUG_CTL (0x3DE) +#define TOMTOM_A_CDC_MBHC_DEBUG_CTL__POR (0x00) +#define TOMTOM_A_CDC_MBHC_SPARE (0x3DF) +#define TOMTOM_A_CDC_MBHC_SPARE__POR (0x00) +#define TOMTOM_A_CDC_RX8_B1_CTL (0x3E0) +#define TOMTOM_A_CDC_RX8_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX8_B2_CTL (0x3E1) +#define TOMTOM_A_CDC_RX8_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX8_B3_CTL (0x3E2) +#define TOMTOM_A_CDC_RX8_B3_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX8_B4_CTL (0x3E3) +#define TOMTOM_A_CDC_RX8_B4_CTL__POR (0x0B) +#define TOMTOM_A_CDC_RX8_B5_CTL (0x3E4) +#define TOMTOM_A_CDC_RX8_B5_CTL__POR (0x78) +#define TOMTOM_A_CDC_RX8_B6_CTL (0x3E5) +#define TOMTOM_A_CDC_RX8_B6_CTL__POR (0x80) +#define TOMTOM_A_CDC_RX8_VOL_CTL_B1_CTL (0x3E6) +#define TOMTOM_A_CDC_RX8_VOL_CTL_B1_CTL__POR (0x00) +#define TOMTOM_A_CDC_RX8_VOL_CTL_B2_CTL (0x3E7) +#define TOMTOM_A_CDC_RX8_VOL_CTL_B2_CTL__POR (0x00) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_VAL0 (0x3E8) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_VAL0__POR (0x00) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_VAL1 (0x3E9) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_VAL1__POR (0x00) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_VAL2 (0x3EA) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_VAL2__POR (0x00) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_VAL3 (0x3EB) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_VAL3__POR (0x00) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_VAL4 (0x3EC) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_VAL4__POR (0x00) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_VAL5 (0x3ED) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_VAL5__POR (0x00) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_VAL6 (0x3EE) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_VAL6__POR (0x00) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_VAL7 (0x3EF) +#define TOMTOM_A_CDC_SPKR2_CLIPDET_VAL7__POR (0x00) +#define TOMTOM_A_CDC_BOOST_MODE_CTL (0x3F0) +#define TOMTOM_A_CDC_BOOST_MODE_CTL__POR (0x00) +#define TOMTOM_A_CDC_BOOST_THRESHOLD (0x3F1) +#define TOMTOM_A_CDC_BOOST_THRESHOLD__POR (0x02) +#define TOMTOM_A_CDC_BOOST_TAP_SEL (0x3F2) +#define TOMTOM_A_CDC_BOOST_TAP_SEL__POR (0x00) +#define TOMTOM_A_CDC_BOOST_HOLD_TIME (0x3F3) +#define TOMTOM_A_CDC_BOOST_HOLD_TIME__POR (0x02) +#define TOMTOM_A_CDC_BOOST_TRGR_EN (0x3F4) +#define TOMTOM_A_CDC_BOOST_TRGR_EN__POR (0x00) + +/* SLIMBUS Slave Registers */ +#define TOMTOM_SLIM_PGD_PORT_INT_EN0 (0x30) +#define TOMTOM_SLIM_PGD_PORT_INT_STATUS_RX_0 (0x34) +#define TOMTOM_SLIM_PGD_PORT_INT_STATUS_RX_1 (0x35) +#define TOMTOM_SLIM_PGD_PORT_INT_STATUS_TX_0 (0x36) +#define TOMTOM_SLIM_PGD_PORT_INT_STATUS_TX_1 (0x37) +#define TOMTOM_SLIM_PGD_PORT_INT_CLR_RX_0 (0x38) +#define TOMTOM_SLIM_PGD_PORT_INT_CLR_RX_1 (0x39) +#define TOMTOM_SLIM_PGD_PORT_INT_CLR_TX_0 (0x3A) +#define TOMTOM_SLIM_PGD_PORT_INT_CLR_TX_1 (0x3B) +#define TOMTOM_SLIM_PGD_PORT_INT_RX_SOURCE0 (0x60) +#define TOMTOM_SLIM_PGD_PORT_INT_TX_SOURCE0 (0x70) + +/* Macros for Packing Register Writes into a U32 */ +#define TOMTOM_PACKED_REG_SIZE sizeof(u32) + +#define TOMTOM_CODEC_PACK_ENTRY(reg, mask, val) ((val & 0xff)|\ + ((mask & 0xff) << 8)|((reg & 0xffff) << 16)) +#define TOMTOM_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \ + do { \ + ((reg) = ((packed >> 16) & (0xffff))); \ + ((mask) = ((packed >> 8) & (0xff))); \ + ((val) = ((packed) & (0xff))); \ + } while (0) + +#define TOMTOM_SB_PGD_PORT_TX_BASE 0x50 +#define TOMTOM_SB_PGD_PORT_RX_BASE 0x40 +#define WCD9330_MAX_REGISTER 0x3FF +extern const u8 tomtom_reg_readable[WCD9330_MAX_REGISTER + 1]; +#endif diff --git a/include/linux/mfd/wcd9xxx/wcd9xxx-irq.h b/include/linux/mfd/wcd9xxx/wcd9xxx-irq.h new file mode 100644 index 000000000000..f1b7a4320ad1 --- /dev/null +++ b/include/linux/mfd/wcd9xxx/wcd9xxx-irq.h @@ -0,0 +1,32 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/types.h> +#include <linux/mfd/wcd9xxx/core.h> + +#ifndef __MFD_WCD9XXX_IRQ_H +#define __MFD_WCD9XXX_IRQ_H +bool wcd9xxx_lock_sleep(struct wcd9xxx_core_resource *); +void wcd9xxx_unlock_sleep(struct wcd9xxx_core_resource *); +void wcd9xxx_nested_irq_lock(struct wcd9xxx_core_resource *); +void wcd9xxx_nested_irq_unlock(struct wcd9xxx_core_resource *); +int wcd9xxx_request_irq(struct wcd9xxx_core_resource *, int, + irq_handler_t, const char *, void *); + +void wcd9xxx_free_irq(struct wcd9xxx_core_resource *, int, void*); +void wcd9xxx_enable_irq(struct wcd9xxx_core_resource *, int); +void wcd9xxx_disable_irq(struct wcd9xxx_core_resource *, int); +void wcd9xxx_disable_irq_sync(struct wcd9xxx_core_resource *, int); + +int wcd9xxx_irq_init(struct wcd9xxx_core_resource *); +void wcd9xxx_irq_exit(struct wcd9xxx_core_resource *); +#endif diff --git a/include/linux/mfd/wcd9xxx/wcd9xxx-slimslave.h b/include/linux/mfd/wcd9xxx/wcd9xxx-slimslave.h new file mode 100755 index 000000000000..96fdb00a2e03 --- /dev/null +++ b/include/linux/mfd/wcd9xxx/wcd9xxx-slimslave.h @@ -0,0 +1,119 @@ +/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __WCD9310_SLIMSLAVE_H_ +#define __WCD9310_SLIMSLAVE_H_ + +#include <linux/slimbus/slimbus.h> +#include <linux/mfd/wcd9xxx/core.h> + + +/* + * client is expected to give port ids in the range of + * 1-10 for pre Taiko Tx ports and 1-16 for Taiko + * 1-7 for pre Taiko Rx ports and 1-16 for Tako, + * we need to add offset for getting the absolute slave + * port id before configuring the HW + */ +#define TABLA_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS 10 +#define TAIKO_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS 16 + +#define SLIM_MAX_TX_PORTS TAIKO_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS + +#define TABLA_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS \ + TABLA_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS +#define TAIKO_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS \ + TAIKO_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS + +#define TABLA_SB_PGD_MAX_NUMBER_OF_RX_SLAVE_DEV_PORTS 7 +#define TAIKO_SB_PGD_MAX_NUMBER_OF_RX_SLAVE_DEV_PORTS 13 + +#define SLIM_MAX_RX_PORTS TAIKO_SB_PGD_MAX_NUMBER_OF_RX_SLAVE_DEV_PORTS + +#define SLIM_MAX_REG_ADDR (0x180 + 4 * (SLIM_MAX_RX_PORTS)) + +#define TABLA_SB_PGD_RX_PORT_MULTI_CHANNEL_0_START_PORT_ID \ + TABLA_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS +#define TAIKO_SB_PGD_RX_PORT_MULTI_CHANNEL_0_START_PORT_ID \ + TAIKO_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS + +#define TABLA_SB_PGD_RX_PORT_MULTI_CHANNEL_0_END_PORT_ID 16 +#define TAIKO_SB_PGD_RX_PORT_MULTI_CHANNEL_0_END_PORT_ID 31 + +#define TABLA_SB_PGD_TX_PORT_MULTI_CHANNEL_1_END_PORT_ID 9 +#define TAIKO_SB_PGD_TX_PORT_MULTI_CHANNEL_1_END_PORT_ID 15 + +/* below details are taken from SLIMBUS slave SWI */ +#define SB_PGD_PORT_BASE 0x000 + +#define SB_PGD_PORT_CFG_BYTE_ADDR(offset, port_num) \ + (SB_PGD_PORT_BASE + offset + (1 * port_num)) + +#define SB_PGD_TX_PORT_MULTI_CHANNEL_0(port_num) \ + (SB_PGD_PORT_BASE + 0x100 + 4*port_num) +#define SB_PGD_TX_PORT_MULTI_CHANNEL_0_START_PORT_ID 0 +#define SB_PGD_TX_PORT_MULTI_CHANNEL_0_END_PORT_ID 7 + +#define SB_PGD_TX_PORT_MULTI_CHANNEL_1(port_num) \ + (SB_PGD_PORT_BASE + 0x101 + 4*port_num) +#define SB_PGD_TX_PORT_MULTI_CHANNEL_1_START_PORT_ID 8 + +#define SB_PGD_RX_PORT_MULTI_CHANNEL_0(offset, port_num) \ + (SB_PGD_PORT_BASE + offset + (4 * port_num)) + +/* slave port water mark level + * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes) + */ +#define SLAVE_PORT_WATER_MARK_6BYTES 0 +#define SLAVE_PORT_WATER_MARK_9BYTES 1 +#define SLAVE_PORT_WATER_MARK_12BYTES 2 +#define SLAVE_PORT_WATER_MARK_15BYTES 3 +#define SLAVE_PORT_WATER_MARK_SHIFT 1 +#define SLAVE_PORT_ENABLE 1 +#define SLAVE_PORT_DISABLE 0 +#define WATER_MARK_VAL \ + ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \ + (SLAVE_PORT_ENABLE)) +#define BASE_CH_NUM 128 + + +int wcd9xxx_init_slimslave(struct wcd9xxx *wcd9xxx, + u8 wcd9xxx_pgd_la, + unsigned int tx_num, unsigned int *tx_slot, + unsigned int rx_num, unsigned int *rx_slot); + +int wcd9xxx_deinit_slimslave(struct wcd9xxx *wcd9xxx); + +int wcd9xxx_cfg_slim_sch_rx(struct wcd9xxx *wcd9xxx, + struct list_head *wcd9xxx_ch_list, + unsigned int rate, unsigned int bit_width, + u16 *grph); +int wcd9xxx_cfg_slim_sch_tx(struct wcd9xxx *wcd9xxx, + struct list_head *wcd9xxx_ch_list, + unsigned int rate, unsigned int bit_width, + u16 *grph); +int wcd9xxx_close_slim_sch_rx(struct wcd9xxx *wcd9xxx, + struct list_head *wcd9xxx_ch_list, u16 grph); +int wcd9xxx_close_slim_sch_tx(struct wcd9xxx *wcd9xxx, + struct list_head *wcd9xxx_ch_list, u16 grph); +int wcd9xxx_get_channel(struct wcd9xxx *wcd9xxx, + unsigned int *rx_ch, + unsigned int *tx_ch); +int wcd9xxx_get_slave_port(unsigned int ch_num); +int wcd9xxx_disconnect_port(struct wcd9xxx *wcd9xxx, + struct list_head *wcd9xxx_ch_list, u16 grph); +int wcd9xxx_rx_vport_validation(u32 port_id, + struct list_head *codec_dai_list); +int wcd9xxx_tx_vport_validation(u32 vtable, u32 port_id, + struct wcd9xxx_codec_dai_data *codec_dai, + u32 num_codec_dais); +#endif /* __WCD9310_SLIMSLAVE_H_ */ diff --git a/include/linux/mfd/wcd9xxx/wcd9xxx-utils.h b/include/linux/mfd/wcd9xxx/wcd9xxx-utils.h new file mode 100644 index 000000000000..7c35d7fecc50 --- /dev/null +++ b/include/linux/mfd/wcd9xxx/wcd9xxx-utils.h @@ -0,0 +1,141 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __WCD9XXX_UTILS_H__ +#define __WCD9XXX_UTILS_H__ + +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/regmap.h> +#include <linux/mfd/wcd9xxx/pdata.h> +#include <linux/mfd/wcd9xxx/core.h> + +struct wcd9xxx_pdata *wcd9xxx_populate_dt_data(struct device *dev); +int wcd9xxx_bringup(struct device *dev); +int wcd9xxx_bringdown(struct device *dev); +struct regmap *wcd9xxx_regmap_init(struct device *, + const struct regmap_config *); +int wcd9xxx_reset(struct device *dev); +int wcd9xxx_reset_low(struct device *dev); +int wcd9xxx_get_codec_info(struct device *dev); + +typedef int (*codec_bringup_fn)(struct wcd9xxx *); +typedef int (*codec_bringdown_fn)(struct wcd9xxx *); +typedef int (*codec_type_fn)(struct wcd9xxx *, + struct wcd9xxx_codec_type *); + +#ifdef CONFIG_WCD934X_CODEC +extern int wcd934x_bringup(struct wcd9xxx *wcd9xxx); +extern int wcd934x_bringdown(struct wcd9xxx *wcd9xxx); +extern int wcd934x_get_codec_info(struct wcd9xxx *, + struct wcd9xxx_codec_type *); +#endif + +#ifdef CONFIG_WCD9335_CODEC +extern int wcd9335_bringup(struct wcd9xxx *wcd9xxx); +extern int wcd9335_bringdown(struct wcd9xxx *wcd9xxx); +extern int wcd9335_get_codec_info(struct wcd9xxx *, + struct wcd9xxx_codec_type *); +#endif + +#ifdef CONFIG_WCD9330_CODEC +extern int wcd9330_bringup(struct wcd9xxx *wcd9xxx); +extern int wcd9330_bringdown(struct wcd9xxx *wcd9xxx); +extern int wcd9330_get_codec_info(struct wcd9xxx *, + struct wcd9xxx_codec_type *); +#endif + +static inline codec_bringdown_fn wcd9xxx_bringdown_fn(int type) +{ + codec_bringdown_fn cdc_bdown_fn; + + switch (type) { +#ifdef CONFIG_WCD934X_CODEC + case WCD934X: + cdc_bdown_fn = wcd934x_bringdown; + break; +#endif +#ifdef CONFIG_WCD9335_CODEC + case WCD9335: + cdc_bdown_fn = wcd9335_bringdown; + break; +#endif +#ifdef CONFIG_WCD9330_CODEC + case WCD9330: + cdc_bdown_fn = wcd9330_bringdown; + break; +#endif + default: + cdc_bdown_fn = NULL; + break; + } + + return cdc_bdown_fn; +} + +static inline codec_bringup_fn wcd9xxx_bringup_fn(int type) +{ + codec_bringup_fn cdc_bup_fn; + + switch (type) { +#ifdef CONFIG_WCD934X_CODEC + case WCD934X: + cdc_bup_fn = wcd934x_bringup; + break; +#endif +#ifdef CONFIG_WCD9335_CODEC + case WCD9335: + cdc_bup_fn = wcd9335_bringup; + break; +#endif +#ifdef CONFIG_WCD9330_CODEC + case WCD9330: + cdc_bup_fn = wcd9330_bringup; + break; +#endif + default: + cdc_bup_fn = NULL; + break; + } + + return cdc_bup_fn; +} + +static inline codec_type_fn wcd9xxx_get_codec_info_fn(int type) +{ + codec_type_fn cdc_type_fn; + + switch (type) { +#ifdef CONFIG_WCD934X_CODEC + case WCD934X: + cdc_type_fn = wcd934x_get_codec_info; + break; +#endif +#ifdef CONFIG_WCD9335_CODEC + case WCD9335: + cdc_type_fn = wcd9335_get_codec_info; + break; +#endif +#ifdef CONFIG_WCD9330_CODEC + case WCD9330: + cdc_type_fn = wcd9330_get_codec_info; + break; +#endif + default: + cdc_type_fn = NULL; + break; + } + + return cdc_type_fn; +} +#endif + |