diff options
Diffstat (limited to 'include/dt-bindings/clock/msm-clocks-hwio-8998.h')
| -rw-r--r-- | include/dt-bindings/clock/msm-clocks-hwio-8998.h | 395 |
1 files changed, 395 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/msm-clocks-hwio-8998.h b/include/dt-bindings/clock/msm-clocks-hwio-8998.h new file mode 100644 index 000000000000..fc42ac3d49a0 --- /dev/null +++ b/include/dt-bindings/clock/msm-clocks-hwio-8998.h @@ -0,0 +1,395 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CLKFLAG_NO_RATE_CACHE 0x00004000 + +#define FMAX_LOWER 0 +#define FMAX_LOW 1 +#define FMAX_NOM 2 +#define FMAX_TURBO 3 + +#define HALT_CHECK_DELAY 5 + +#define RPM_MISC_CLK_TYPE 0x306b6c63 +#define RPM_BUS_CLK_TYPE 0x316b6c63 +#define RPM_MEM_CLK_TYPE 0x326b6c63 +#define RPM_IPA_CLK_TYPE 0x617069 +#define RPM_CE_CLK_TYPE 0x6563 +#define RPM_AGGR_CLK_TYPE 0x72676761 +#define RPM_SMD_KEY_ENABLE 0x62616E45 +#define RPM_MMAXI_CLK_TYPE 0x69786d6d + +#define CXO_CLK_SRC_ID 0x0 +#define QDSS_CLK_ID 0x1 +#define SNOC_CLK_ID 0x1 +#define CNOC_CLK_ID 0x2 +#define CNOC_PERIPH_CLK_ID 0x0 +#define BIMC_CLK_ID 0x0 +#define IPA_CLK_ID 0x0 +#define CE1_CLK_ID 0x0 +#define RF_CLK1_ID 0x4 +#define RF_CLK2_ID 0x5 +#define RF_CLK3_ID 0x6 +#define LN_BB_CLK1_ID 0x1 +#define LN_BB_CLK2_ID 0x2 +#define LN_BB_CLK3_ID 0x3 +#define DIV_CLK1_ID 0xb +#define DIV_CLK2_ID 0xc +#define DIV_CLK3_ID 0xd +#define RF_CLK1_PIN_ID 0x4 +#define RF_CLK2_PIN_ID 0x5 +#define RF_CLK3_PIN_ID 0x6 +#define LN_BB_CLK1_PIN_ID 0x1 +#define LN_BB_CLK2_PIN_ID 0x2 +#define LN_BB_CLK3_PIN_ID 0x3 +#define AGGR1_NOC_ID 0x1 +#define AGGR2_NOC_ID 0x2 +#define MMSSNOC_AXI_CLK_ID 0x0 + +#define APCS_COMMON_LMH_CMD_RCGR 0x0012C + +#define GCC_APCS_GPLL_ENA_VOTE 0x52000 +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE 0x52004 +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1 0x5200C +#define PLLTEST_PAD_CFG 0x6200C +#define GCC_XO_DIV4_CBCR 0x43008 +#define CLOCK_FRQ_MEASURE_CTL 0x62004 +#define CLOCK_FRQ_MEASURE_STATUS 0x62008 +#define GCC_GPLL0_MODE 0x00000 +#define GCC_GPLL4_MODE 0x77000 +#define GCC_USB30_MASTER_CMD_RCGR 0x0F014 +#define GCC_PCIE_AUX_CMD_RCGR 0x6C000 +#define GCC_UFS_AXI_CMD_RCGR 0x75018 +#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR 0x19020 +#define GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR 0x1900C +#define GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR 0x1B020 +#define GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR 0x1B00C +#define GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR 0x1D020 +#define GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR 0x1D00C +#define GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR 0x1F020 +#define GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR 0x1F00C +#define GCC_BLSP1_QUP5_I2C_APPS_CMD_RCGR 0x21020 +#define GCC_BLSP1_QUP5_SPI_APPS_CMD_RCGR 0x2100C +#define GCC_BLSP1_QUP6_I2C_APPS_CMD_RCGR 0x23020 +#define GCC_BLSP1_QUP6_SPI_APPS_CMD_RCGR 0x2300C +#define GCC_BLSP1_UART1_APPS_CMD_RCGR 0x1A00C +#define GCC_BLSP1_UART2_APPS_CMD_RCGR 0x1C00C +#define GCC_BLSP1_UART3_APPS_CMD_RCGR 0x1E00C +#define GCC_BLSP2_QUP1_I2C_APPS_CMD_RCGR 0x26020 +#define GCC_BLSP2_QUP2_I2C_APPS_CMD_RCGR 0x28020 +#define GCC_BLSP2_QUP3_I2C_APPS_CMD_RCGR 0x2A020 +#define GCC_BLSP2_QUP4_I2C_APPS_CMD_RCGR 0x2C020 +#define GCC_BLSP2_QUP5_I2C_APPS_CMD_RCGR 0x2E020 +#define GCC_BLSP2_QUP6_I2C_APPS_CMD_RCGR 0x30020 +#define GCC_BLSP2_QUP1_SPI_APPS_CMD_RCGR 0x2600C +#define GCC_BLSP2_QUP2_SPI_APPS_CMD_RCGR 0x2800C +#define GCC_BLSP2_QUP3_SPI_APPS_CMD_RCGR 0x2A00C +#define GCC_BLSP2_QUP4_SPI_APPS_CMD_RCGR 0x2C00C +#define GCC_BLSP2_QUP5_SPI_APPS_CMD_RCGR 0x2E00C +#define GCC_BLSP2_QUP6_SPI_APPS_CMD_RCGR 0x3000C +#define GCC_BLSP2_UART1_APPS_CMD_RCGR 0x2700C +#define GCC_BLSP2_UART2_APPS_CMD_RCGR 0x2900C +#define GCC_BLSP2_UART3_APPS_CMD_RCGR 0x2B00C +#define GCC_GP1_CMD_RCGR 0x64004 +#define GCC_GP2_CMD_RCGR 0x65004 +#define GCC_GP3_CMD_RCGR 0x66004 +#define GCC_HMSS_RBCPR_CMD_RCGR 0x48044 +#define GCC_PDM2_CMD_RCGR 0x33010 +#define GCC_SDCC2_APPS_CMD_RCGR 0x14010 +#define GCC_SDCC4_APPS_CMD_RCGR 0x16010 +#define GCC_TSIF_REF_CMD_RCGR 0x36010 +#define GCC_UFS_ICE_CORE_CMD_RCGR 0x76010 +#define GCC_UFS_PHY_AUX_CMD_RCGR 0x76044 +#define GCC_UFS_UNIPRO_CORE_CMD_RCGR 0x76028 +#define GCC_USB30_MOCK_UTMI_CMD_RCGR 0x0F028 +#define GCC_USB3_PHY_AUX_CMD_RCGR 0x5000C +#define GCC_QSPI_REF_CMD_RCGR 0x9000C +#define GCC_PCIE_0_PHY_BCR 0x6C01C +#define GCC_HDMI_CLKREF_EN 0x88000 +#define GCC_UFS_CLKREF_EN 0x88004 +#define GCC_USB3_CLKREF_EN 0x88008 +#define GCC_PCIE_CLKREF_EN 0x8800C +#define GCC_RX1_USB2_CLKREF_EN 0x88014 +#define GCC_USB3_PHY_BCR 0x50020 +#define GCC_AGGRE1_NOC_XO_CBCR 0x8202C +#define GCC_AGGRE1_UFS_AXI_CBCR 0x82028 +#define GCC_AGGRE1_USB3_AXI_CBCR 0x82024 +#define GCC_BIMC_MSS_Q6_AXI_CBCR 0x4401C +#define GCC_BLSP1_AHB_CBCR 0x17004 +#define GCC_BLSP1_BCR 0x17000 +#define GCC_BLSP1_QUP1_SPI_APPS_CBCR 0x19004 +#define GCC_BLSP1_QUP1_I2C_APPS_CBCR 0x19008 +#define GCC_BLSP1_QUP2_SPI_APPS_CBCR 0x1B004 +#define GCC_BLSP1_QUP2_I2C_APPS_CBCR 0x1B008 +#define GCC_BLSP1_QUP3_SPI_APPS_CBCR 0x1D004 +#define GCC_BLSP1_QUP3_I2C_APPS_CBCR 0x1D008 +#define GCC_BLSP1_QUP4_SPI_APPS_CBCR 0x1F004 +#define GCC_BLSP1_QUP4_I2C_APPS_CBCR 0x1F008 +#define GCC_BLSP1_QUP5_SPI_APPS_CBCR 0x21004 +#define GCC_BLSP1_QUP5_I2C_APPS_CBCR 0x21008 +#define GCC_BLSP1_QUP6_SPI_APPS_CBCR 0x23004 +#define GCC_BLSP1_QUP6_I2C_APPS_CBCR 0x23008 +#define GCC_BLSP1_UART1_APPS_CBCR 0x1A004 +#define GCC_BLSP1_UART2_APPS_CBCR 0x1C004 +#define GCC_BLSP1_UART3_APPS_CBCR 0x1E004 +#define GCC_BLSP2_AHB_CBCR 0x25004 +#define GCC_BLSP2_BCR 0x25000 +#define GCC_BLSP2_QUP1_SPI_APPS_CBCR 0x26004 +#define GCC_BLSP2_QUP1_I2C_APPS_CBCR 0x26008 +#define GCC_BLSP2_QUP2_I2C_APPS_CBCR 0x28008 +#define GCC_BLSP2_QUP2_SPI_APPS_CBCR 0x28004 +#define GCC_BLSP2_QUP3_SPI_APPS_CBCR 0x2A004 +#define GCC_BLSP2_QUP3_I2C_APPS_CBCR 0x2A008 +#define GCC_BLSP2_QUP4_SPI_APPS_CBCR 0x2C004 +#define GCC_BLSP2_QUP4_I2C_APPS_CBCR 0x2C008 +#define GCC_BLSP2_QUP5_SPI_APPS_CBCR 0x2E004 +#define GCC_BLSP2_QUP5_I2C_APPS_CBCR 0x2E008 +#define GCC_BLSP2_QUP6_SPI_APPS_CBCR 0x30004 +#define GCC_BLSP2_QUP6_I2C_APPS_CBCR 0x30008 +#define GCC_BLSP2_UART1_APPS_CBCR 0x27004 +#define GCC_BLSP2_UART2_APPS_CBCR 0x29004 +#define GCC_BLSP2_UART3_APPS_CBCR 0x2B004 +#define GCC_BOOT_ROM_AHB_CBCR 0x38004 +#define GCC_BOOT_ROM_BCR 0x38000 +#define GCC_CFG_NOC_USB3_AXI_CBCR 0x05018 +#define GCC_BIMC_GFX_CBCR 0x46040 +#define GCC_GP1_CBCR 0x64000 +#define GCC_GP2_CBCR 0x65000 +#define GCC_GP3_CBCR 0x66000 +#define GCC_GPU_BIMC_GFX_CBCR 0x71010 +#define GCC_GPU_CFG_AHB_CBCR 0x71004 +#define GCC_GPU_IREF_EN 0x88010 +#define GCC_HMSS_DVM_BUS_CBCR 0x4808C +#define GCC_HMSS_RBCPR_CBCR 0x48008 +#define GCC_MMSS_SYS_NOC_AXI_CBCR 0x09000 +#define GCC_MMSS_NOC_CFG_AHB_CBCR 0x09004 +#define GCC_PCIE_0_SLV_AXI_CBCR 0x6B008 +#define GCC_PCIE_0_MSTR_AXI_CBCR 0x6B00C +#define GCC_PCIE_0_CFG_AHB_CBCR 0x6B010 +#define GCC_PCIE_0_AUX_CBCR 0x6B014 +#define GCC_PCIE_0_PIPE_CBCR 0x6B018 +#define GCC_PCIE_PHY_AUX_CBCR 0x6F004 +#define GCC_PCIE_PHY_BCR 0x6F000 +#define GCC_PCIE_PHY_COM_BCR 0x6F014 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 0x6F00C +#define GCC_QUSB2PHY_PRIM_BCR 0x12000 +#define GCC_QUSB2PHY_SEC_BCR 0x12004 +#define GCC_PDM2_CBCR 0x3300C +#define GCC_PDM_AHB_CBCR 0x33004 +#define GCC_PRNG_AHB_CBCR 0x34004 +#define GCC_PRNG_BCR 0x34000 +#define GCC_SDCC2_APPS_CBCR 0x14004 +#define GCC_SDCC2_AHB_CBCR 0x14008 +#define GCC_SDCC4_APPS_CBCR 0x16004 +#define GCC_SDCC4_AHB_CBCR 0x16008 +#define GCC_TSIF_AHB_CBCR 0x36004 +#define GCC_TSIF_REF_CBCR 0x36008 +#define GCC_UFS_AXI_CBCR 0x75008 +#define GCC_UFS_BCR 0x75000 +#define GCC_UFS_AHB_CBCR 0x7500C +#define GCC_UFS_TX_SYMBOL_0_CBCR 0x75010 +#define GCC_UFS_RX_SYMBOL_0_CBCR 0x75014 +#define GCC_UFS_RX_SYMBOL_1_CBCR 0x7605C +#define GCC_UFS_UNIPRO_CORE_CBCR 0x76008 +#define GCC_UFS_ICE_CORE_CBCR 0x7600C +#define GCC_UFS_PHY_AUX_CBCR 0x76040 +#define GCC_USB30_MASTER_CBCR 0x0F008 +#define GCC_USB30_SLEEP_CBCR 0x0F00C +#define GCC_USB30_MOCK_UTMI_CBCR 0x0F010 +#define GCC_USB_30_BCR 0x0F000 +#define GCC_USB3_PHY_AUX_CBCR 0x50000 +#define GCC_USB3_PHY_PIPE_CBCR 0x50004 +#define GCC_USB3PHY_PHY_BCR 0x50024 +#define GCC_APCS_CLOCK_SLEEP_ENA_VOTE 0x52008 +#define GCC_MSS_CFG_AHB_CBCR 0x8A000 +#define GCC_MSS_Q6_BIMC_AXI_CBCR 0x8A040 +#define GCC_MSS_MNOC_BIMC_AXI_CBCR 0x8A004 +#define GCC_MSS_SNOC_AXI_CBCR 0x8A03C +#define GCC_HMSS_GPLL0_CMD_RCGR 0x4805C +#define GCC_MSS_CFG_AHB_CBCR 0x8A000 +#define GCC_MSS_Q6_BIMC_AXI_CBCR 0x8A040 +#define GCC_MSS_MNOC_BIMC_AXI_CBCR 0x8A004 +#define GCC_MSS_SNOC_AXI_CBCR 0x8A03C +#define GCC_DCC_AHB_CBCR 0x84004 +#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CBCR 0x7D010 +#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CBCR 0x7D014 +#define GCC_QSPI_AHB_CBCR 0x90004 +#define GCC_QSPI_REF_CBCR 0x90008 +#define GCC_MMSS_MISC 0x0902C +#define GCC_GPU_MISC 0x71028 + +#define GPUCC_GPU_PLL0_PLL_MODE 0x00000 +#define GPUCC_GPU_PLL0_USER_CTL_MODE 0x0000C +#define GPUCC_GFX3D_CMD_RCGR 0x01070 +#define GPUCC_RBBMTIMER_CMD_RCGR 0x010B0 +#define GPUCC_GFX3D_ISENSE_CMD_RCGR 0x01100 +#define GPUCC_RBCPR_CMD_RCGR 0x01030 +#define GPUCC_GFX3D_CBCR 0x01098 +#define GPUCC_RBBMTIMER_CBCR 0x010D0 +#define GPUCC_GFX3D_ISENSE_CBCR 0x01124 +#define GPUCC_CXO_CBCR 0x01020 +#define GPUCC_RBCPR_CBCR 0x01054 +#define GPU_GX_BCR 0x01090 +#define GPUCC_GX_DOMAIN_MISC 0x00130 +#define GPUCC_GPU_DD_WRAP_CTRL 0x00430 +#define GPUCC_DEBUG_CLK_CTL 0x00120 + +#define MMSS_PLL_VOTE_APCS 0x001E0 +#define MMSS_MMPLL0_PLL_MODE 0x0C000 +#define MMSS_MMPLL1_PLL_MODE 0x0C050 +#define MMSS_MMPLL3_PLL_MODE 0x00000 +#define MMSS_MMPLL4_PLL_MODE 0x00050 +#define MMSS_MMPLL5_PLL_MODE 0x000A0 +#define MMSS_MMPLL6_PLL_MODE 0x000F0 +#define MMSS_MMPLL7_PLL_MODE 0x00140 +#define MMSS_MMPLL10_PLL_MODE 0x00190 +#define MMSS_AHB_CMD_RCGR 0x05000 +#define MMSS_CSI0_CMD_RCGR 0x03090 +#define MMSS_VFE0_CMD_RCGR 0x03600 +#define MMSS_VFE1_CMD_RCGR 0x03620 +#define MMSS_MDP_CMD_RCGR 0x02040 +#define MMSS_MAXI_CMD_RCGR 0x0F020 +#define MMSS_CPP_CMD_RCGR 0x03640 +#define MMSS_JPEG0_CMD_RCGR 0x03500 +#define MMSS_ROT_CMD_RCGR 0x021A0 +#define MMSS_VIDEO_CORE_CMD_RCGR 0x01000 +#define MMSS_CSI1_CMD_RCGR 0x03100 +#define MMSS_CSI2_CMD_RCGR 0x03160 +#define MMSS_CSI3_CMD_RCGR 0x031C0 +#define MMSS_FD_CORE_CMD_RCGR 0x03B00 +#define MMSS_BYTE0_CMD_RCGR 0x02120 +#define MMSS_BYTE1_CMD_RCGR 0x02140 +#define MMSS_PCLK0_CMD_RCGR 0x02000 +#define MMSS_PCLK1_CMD_RCGR 0x02020 +#define MMSS_VIDEO_SUBCORE0_CMD_RCGR 0x01060 +#define MMSS_VIDEO_SUBCORE1_CMD_RCGR 0x01080 +#define MMSS_CSIPHY_CMD_RCGR 0x03800 +#define MMSS_CCI_CMD_RCGR 0x03300 +#define MMSS_CAMSS_GP0_CMD_RCGR 0x03420 +#define MMSS_CAMSS_GP1_CMD_RCGR 0x03450 +#define MMSS_MCLK0_CMD_RCGR 0x03360 +#define MMSS_MCLK1_CMD_RCGR 0x03390 +#define MMSS_MCLK2_CMD_RCGR 0x033C0 +#define MMSS_MCLK3_CMD_RCGR 0x033F0 +#define MMSS_CAMSS_CSI2PHYTIMER_CBCR 0x03084 +#define MMSS_CSI0PHYTIMER_CMD_RCGR 0x03000 +#define MMSS_CSI1PHYTIMER_CMD_RCGR 0x03030 +#define MMSS_CSI2PHYTIMER_CMD_RCGR 0x03060 +#define MMSS_DP_GTC_CMD_RCGR 0x02280 +#define MMSS_ESC0_CMD_RCGR 0x02160 +#define MMSS_ESC1_CMD_RCGR 0x02180 +#define MMSS_EXTPCLK_CMD_RCGR 0x02060 +#define MMSS_HDMI_CMD_RCGR 0x02100 +#define MMSS_VSYNC_CMD_RCGR 0x02080 +#define MMSS_BIMC_SMMU_AHB_CBCR 0x0E004 +#define MMSS_BIMC_SMMU_AXI_CBCR 0x0E008 +#define MMSS_SNOC_DVM_AXI_CBCR 0x0E040 +#define MMSS_CAMSS_AHB_CBCR 0x0348C +#define MMSS_CAMSS_CCI_AHB_CBCR 0x03348 +#define MMSS_CAMSS_CCI_CBCR 0x03344 +#define MMSS_CAMSS_CPP_AHB_CBCR 0x036B4 +#define MMSS_CAMSS_CPP_CBCR 0x036B0 +#define MMSS_CAMSS_CPP_AXI_CBCR 0x036C4 +#define MMSS_CAMSS_CPP_VBIF_AHB_CBCR 0x036C8 +#define MMSS_CAMSS_CPHY_CSID0_CBCR 0x03730 +#define MMSS_CAMSS_CSI0_AHB_CBCR 0x030BC +#define MMSS_CAMSS_CSI0_CBCR 0x030B4 +#define MMSS_CAMSS_CSI0PIX_CBCR 0x030E4 +#define MMSS_CAMSS_CSI0RDI_CBCR 0x030D4 +#define MMSS_CAMSS_CPHY_CSID1_CBCR 0x03734 +#define MMSS_CAMSS_CSI1_AHB_CBCR 0x03128 +#define MMSS_CAMSS_CSI1_CBCR 0x03124 +#define MMSS_CAMSS_CSI1PIX_CBCR 0x03154 +#define MMSS_CAMSS_CSI1RDI_CBCR 0x03144 +#define MMSS_CAMSS_CPHY_CSID2_CBCR 0x03738 +#define MMSS_CAMSS_CSI2_AHB_CBCR 0x03188 +#define MMSS_CAMSS_CSI2_CBCR 0x03184 +#define MMSS_CAMSS_CSI2PIX_CBCR 0x031B4 +#define MMSS_CAMSS_CSI2RDI_CBCR 0x031A4 +#define MMSS_CAMSS_CPHY_CSID3_CBCR 0x0373C +#define MMSS_CAMSS_CSI3_AHB_CBCR 0x031E8 +#define MMSS_CAMSS_CSI3_CBCR 0x031E4 +#define MMSS_CAMSS_CSI3PIX_CBCR 0x03214 +#define MMSS_CAMSS_CSI3RDI_CBCR 0x03204 +#define MMSS_CAMSS_CSI_VFE0_CBCR 0x03704 +#define MMSS_CAMSS_CSI_VFE1_CBCR 0x03714 +#define MMSS_CAMSS_CSIPHY0_CBCR 0x03740 +#define MMSS_CAMSS_CSIPHY1_CBCR 0x03744 +#define MMSS_CAMSS_CSIPHY2_CBCR 0x03748 +#define MMSS_FD_AHB_CBCR 0x03B74 +#define MMSS_FD_CORE_CBCR 0x03B68 +#define MMSS_FD_CORE_UAR_CBCR 0x03B6C +#define MMSS_CAMSS_GP0_CBCR 0x03444 +#define MMSS_CAMSS_GP1_CBCR 0x03474 +#define MMSS_CAMSS_ISPIF_AHB_CBCR 0x03224 +#define MMSS_CAMSS_JPEG0_CBCR 0x035A8 +#define MMSS_CAMSS_JPEG_AHB_CBCR 0x035B4 +#define MMSS_CAMSS_JPEG_AXI_CBCR 0x035B8 +#define MMSS_CAMSS_MCLK0_CBCR 0x03384 +#define MMSS_CAMSS_MCLK1_CBCR 0x033B4 +#define MMSS_CAMSS_MCLK2_CBCR 0x033E4 +#define MMSS_CAMSS_MCLK3_CBCR 0x03414 +#define MMSS_CAMSS_MICRO_AHB_CBCR 0x03494 +#define MMSS_CAMSS_CSI0PHYTIMER_CBCR 0x03024 +#define MMSS_CAMSS_CSI1PHYTIMER_CBCR 0x03054 +#define MMSS_CSI2PHYTIMER_CMD_RCGR 0x03060 +#define MMSS_CAMSS_TOP_AHB_CBCR 0x03484 +#define MMSS_CAMSS_VFE0_AHB_CBCR 0x03668 +#define MMSS_CAMSS_VFE0_CBCR 0x036A8 +#define MMSS_CAMSS_VFE0_STREAM_CBCR 0x03720 +#define MMSS_CAMSS_VFE1_AHB_CBCR 0x03678 +#define MMSS_CAMSS_VFE1_CBCR 0x036AC +#define MMSS_CAMSS_VFE1_STREAM_CBCR 0x03724 +#define MMSS_CAMSS_VFE_VBIF_AHB_CBCR 0x036B8 +#define MMSS_CAMSS_VFE_VBIF_AXI_CBCR 0x036BC +#define MMSS_MDSS_AHB_CBCR 0x02308 +#define MMSS_MDSS_AXI_CBCR 0x02310 +#define MMSS_MDSS_BYTE0_CBCR 0x0233C +#define MMSS_MDSS_BYTE0_INTF_CBCR 0x02374 +#define MMSS_MDSS_BYTE0_INTF_DIV 0x0237C +#define MMSS_MDSS_BYTE1_CBCR 0x02340 +#define MMSS_MDSS_BYTE1_INTF_CBCR 0x02378 +#define MMSS_MDSS_BYTE1_INTF_DIV 0x02380 +#define MMSS_MDSS_DP_AUX_CBCR 0x02364 +#define MMSS_MDSS_DP_CRYPTO_CBCR 0x0235C +#define MMSS_MDSS_DP_GTC_CBCR 0x02368 +#define MMSS_MDSS_DP_LINK_CBCR 0x02354 +#define MMSS_MDSS_DP_LINK_INTF_CBCR 0x02358 +#define MMSS_MDSS_DP_PIXEL_CBCR 0x02360 +#define MMSS_MDSS_ESC0_CBCR 0x02344 +#define MMSS_MDSS_ESC1_CBCR 0x02348 +#define MMSS_MDSS_EXTPCLK_CBCR 0x02324 +#define MMSS_MDSS_HDMI_CBCR 0x02338 +#define MMSS_MDSS_HDMI_DP_AHB_CBCR 0x0230C +#define MMSS_MDSS_MDP_CBCR 0x0231C +#define MMSS_MDSS_MDP_LUT_CBCR 0x02320 +#define MMSS_MDSS_PCLK0_CBCR 0x02314 +#define MMSS_MDSS_PCLK1_CBCR 0x02318 +#define MMSS_MDSS_ROT_CBCR 0x02350 +#define MMSS_MDSS_VSYNC_CBCR 0x02328 +#define MMSS_MISC_AHB_CBCR 0x00328 +#define MMSS_MISC_CXO_CBCR 0x00324 +#define MMSS_MNOC_AHB_CBCR 0x05024 +#define MMSS_MNOC_MAXI_CBCR 0x0F004 +#define MMSS_VIDEO_SUBCORE0_CBCR 0x01048 +#define MMSS_VIDEO_SUBCORE1_CBCR 0x0104C +#define MMSS_VIDEO_AHB_CBCR 0x01030 +#define MMSS_VIDEO_AXI_CBCR 0x01034 +#define MMSS_VIDEO_CORE_CBCR 0x01028 +#define MMSS_VIDEO_MAXI_CBCR 0x01038 +#define MMSS_VMEM_AHB_CBCR 0x0F068 +#define MMSS_VMEM_MAXI_CBCR 0x0F064 +#define MMSS_DP_AUX_CMD_RCGR 0x02260 +#define MMSS_DP_CRYPTO_CMD_RCGR 0x02220 +#define MMSS_DP_LINK_CMD_RCGR 0x02200 +#define MMSS_DP_PIXEL_CMD_RCGR 0x02240 +#define MMSS_DEBUG_CLK_CTL 0x00900 |