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path: root/drivers/pci/host/pci-msm.c
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Diffstat (limited to 'drivers/pci/host/pci-msm.c')
-rw-r--r--drivers/pci/host/pci-msm.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c
index 9be5d601d38a..87b0abfacb87 100644
--- a/drivers/pci/host/pci-msm.c
+++ b/drivers/pci/host/pci-msm.c
@@ -4520,7 +4520,7 @@ int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)
/* assert PCIe reset link to keep EP in reset */
- PCIE_INFO(dev, "PCIe: Assert the reset of endpoint of RC%d.\n",
+ PCIE_DBG(dev, "PCIe: Assert the reset of endpoint of RC%d.\n",
dev->rc_idx);
gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num,
dev->gpio[MSM_PCIE_GPIO_PERST].on);
@@ -4640,7 +4640,7 @@ int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)
dev->rc_idx, retries);
if (pcie_phy_is_ready(dev))
- PCIE_INFO(dev, "PCIe RC%d PHY is ready!\n", dev->rc_idx);
+ PCIE_DBG(dev, "PCIe RC%d PHY is ready!\n", dev->rc_idx);
else {
PCIE_ERR(dev, "PCIe PHY RC%d failed to come up!\n",
dev->rc_idx);
@@ -4660,7 +4660,7 @@ int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)
/* de-assert PCIe reset link to bring EP out of reset */
- PCIE_INFO(dev, "PCIe: Release the reset of endpoint of RC%d.\n",
+ PCIE_DBG(dev, "PCIe: Release the reset of endpoint of RC%d.\n",
dev->rc_idx);
gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num,
1 - dev->gpio[MSM_PCIE_GPIO_PERST].on);
@@ -4689,9 +4689,9 @@ int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)
msm_pcie_confirm_linkup(dev, false, false, NULL)) {
PCIE_DBG(dev, "Link is up after %d checkings\n",
link_check_count);
- PCIE_INFO(dev, "PCIe RC%d link initialized\n", dev->rc_idx);
+ PCIE_DBG(dev, "PCIe RC%d link initialized\n", dev->rc_idx);
} else {
- PCIE_INFO(dev, "PCIe: Assert the reset of endpoint of RC%d.\n",
+ PCIE_DBG(dev, "PCIe: Assert the reset of endpoint of RC%d.\n",
dev->rc_idx);
gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num,
dev->gpio[MSM_PCIE_GPIO_PERST].on);
@@ -4774,7 +4774,7 @@ void msm_pcie_disable(struct msm_pcie_dev_t *dev, u32 options)
dev->power_on = false;
dev->link_turned_off_counter++;
- PCIE_INFO(dev, "PCIe: Assert the reset of endpoint of RC%d.\n",
+ PCIE_DBG(dev, "PCIe: Assert the reset of endpoint of RC%d.\n",
dev->rc_idx);
gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num,
@@ -6736,8 +6736,8 @@ module_exit(pcie_exit);
/* RC do not represent the right class; set it to PCI_CLASS_BRIDGE_PCI */
static void msm_pcie_fixup_early(struct pci_dev *dev)
{
- struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev->bus);
- PCIE_DBG(pcie_dev, "hdr_type %d\n", dev->hdr_type);
+ PCIE_DBG((struct msm_pcie_dev_t*)PCIE_BUS_PRIV_DATA(dev->bus), "hdr_type %d\n",
+ dev->hdr_type);
if (dev->hdr_type == 1)
dev->class = (dev->class & 0xff) | (PCI_CLASS_BRIDGE_PCI << 8);
}