/*
 * Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H
#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H

/* Hardware/Dummy/Voter clocks */
#define GPLL0_DIV					0
#define MDSS_MDP_VOTE_CLK				1
#define MDSS_ROTATOR_VOTE_CLK				2

/* RCG and Branches */
#define MMPLL0_EARLY					10
#define MMPLL0_PLL					11
#define MMPLL1_EARLY					12
#define MMPLL1_PLL					13
#define MMPLL2_EARLY					14
#define MMPLL2_PLL					15
#define MMPLL3_EARLY					16
#define MMPLL3_PLL					17
#define MMPLL4_EARLY					18
#define MMPLL4_PLL					19
#define MMPLL5_EARLY					20
#define MMPLL5_PLL					21
#define MMPLL8_EARLY					22
#define MMPLL8_PLL					23
#define MMPLL9_EARLY					24
#define MMPLL9_PLL					25
#define AHB_CLK_SRC					26
#define MAXI_CLK_SRC					27
#define RBCPR_CLK_SRC					28
#define VIDEO_CORE_CLK_SRC				29
#define VIDEO_SUBCORE0_CLK_SRC				30
#define VIDEO_SUBCORE1_CLK_SRC				31
#define PCLK0_CLK_SRC					32
#define PCLK1_CLK_SRC					33
#define MDP_CLK_SRC					34
#define EXTPCLK_CLK_SRC					35
#define VSYNC_CLK_SRC					36
#define HDMI_CLK_SRC					37
#define BYTE0_CLK_SRC					38
#define BYTE1_CLK_SRC					39
#define ESC0_CLK_SRC					40
#define ESC1_CLK_SRC					41
#define CAMSS_GP0_CLK_SRC				42
#define CAMSS_GP1_CLK_SRC				43
#define MCLK0_CLK_SRC					44
#define MCLK1_CLK_SRC					45
#define MCLK2_CLK_SRC					46
#define MCLK3_CLK_SRC					47
#define CCI_CLK_SRC					48
#define CSI0PHYTIMER_CLK_SRC				49
#define CSI1PHYTIMER_CLK_SRC				50
#define CSI2PHYTIMER_CLK_SRC				51
#define CSIPHY0_3P_CLK_SRC				52
#define CSIPHY1_3P_CLK_SRC				53
#define CSIPHY2_3P_CLK_SRC				54
#define JPEG0_CLK_SRC					55
#define JPEG2_CLK_SRC					56
#define JPEG_DMA_CLK_SRC				57
#define VFE0_CLK_SRC					58
#define VFE1_CLK_SRC					59
#define CPP_CLK_SRC					60
#define CSI0_CLK_SRC					61
#define CSI1_CLK_SRC					62
#define CSI2_CLK_SRC					63
#define CSI3_CLK_SRC					64
#define FD_CORE_CLK_SRC					65
#define MMSS_MMAGIC_AHB_CLK				66
#define MMSS_MMAGIC_CFG_AHB_CLK				67
#define MMSS_MISC_AHB_CLK				68
#define MMSS_MISC_CXO_CLK				69
#define MMSS_MMAGIC_MAXI_CLK				70
#define MMAGIC_CAMSS_AXI_CLK				71
#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK			72
#define SMMU_VFE_AHB_CLK				73
#define SMMU_VFE_AXI_CLK				74
#define SMMU_CPP_AHB_CLK				75
#define SMMU_CPP_AXI_CLK				76
#define SMMU_JPEG_AHB_CLK				77
#define SMMU_JPEG_AXI_CLK				78
#define MMAGIC_MDSS_AXI_CLK				79
#define MMAGIC_MDSS_NOC_CFG_AHB_CLK			80
#define SMMU_ROT_AHB_CLK				81
#define SMMU_ROT_AXI_CLK				82
#define SMMU_MDP_AHB_CLK				83
#define SMMU_MDP_AXI_CLK				84
#define MMAGIC_VIDEO_AXI_CLK				85
#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK			86
#define SMMU_VIDEO_AHB_CLK				87
#define SMMU_VIDEO_AXI_CLK				88
#define MMAGIC_BIMC_NOC_CFG_AHB_CLK			89
#define VMEM_MAXI_CLK					90
#define VMEM_AHB_CLK					91
#define MMSS_RBCPR_CLK					92
#define MMSS_RBCPR_AHB_CLK				93
#define VIDEO_CORE_CLK					94
#define VIDEO_AXI_CLK					95
#define VIDEO_MAXI_CLK					96
#define VIDEO_AHB_CLK					97
#define VIDEO_SUBCORE0_CLK				98
#define VIDEO_SUBCORE1_CLK				99
#define MDSS_AHB_CLK					100
#define MDSS_HDMI_AHB_CLK				101
#define MDSS_AXI_CLK					102
#define MDSS_PCLK0_CLK					103
#define MDSS_PCLK1_CLK					104
#define MDSS_MDP_CLK					105
#define MDSS_EXTPCLK_CLK				106
#define MDSS_VSYNC_CLK					107
#define MDSS_HDMI_CLK					108
#define MDSS_BYTE0_CLK					109
#define MDSS_BYTE1_CLK					110
#define MDSS_ESC0_CLK					111
#define MDSS_ESC1_CLK					112
#define CAMSS_TOP_AHB_CLK				113
#define CAMSS_AHB_CLK					114
#define CAMSS_MICRO_AHB_CLK				115
#define CAMSS_GP0_CLK					116
#define CAMSS_GP1_CLK					117
#define CAMSS_MCLK0_CLK					118
#define CAMSS_MCLK1_CLK					119
#define CAMSS_MCLK2_CLK					120
#define CAMSS_MCLK3_CLK					121
#define CAMSS_CCI_CLK					122
#define CAMSS_CCI_AHB_CLK				123
#define CAMSS_CSI0PHYTIMER_CLK				124
#define CAMSS_CSI1PHYTIMER_CLK				125
#define CAMSS_CSI2PHYTIMER_CLK				126
#define CAMSS_CSIPHY0_3P_CLK				127
#define CAMSS_CSIPHY1_3P_CLK				128
#define CAMSS_CSIPHY2_3P_CLK				129
#define CAMSS_JPEG0_CLK					130
#define CAMSS_JPEG2_CLK					131
#define CAMSS_JPEG_DMA_CLK				132
#define CAMSS_JPEG_AHB_CLK				133
#define CAMSS_JPEG_AXI_CLK				134
#define CAMSS_VFE_AHB_CLK				135
#define CAMSS_VFE_AXI_CLK				136
#define CAMSS_VFE0_CLK					137
#define CAMSS_VFE0_STREAM_CLK				138
#define CAMSS_VFE0_AHB_CLK				139
#define CAMSS_VFE1_CLK					140
#define CAMSS_VFE1_STREAM_CLK				141
#define CAMSS_VFE1_AHB_CLK				142
#define CAMSS_CSI_VFE0_CLK				143
#define CAMSS_CSI_VFE1_CLK				144
#define CAMSS_CPP_VBIF_AHB_CLK				145
#define CAMSS_CPP_AXI_CLK				146
#define CAMSS_CPP_CLK					147
#define CAMSS_CPP_AHB_CLK				148
#define CAMSS_CSI0_CLK					149
#define CAMSS_CSI0_AHB_CLK				150
#define CAMSS_CSI0PHY_CLK				151
#define CAMSS_CSI0RDI_CLK				152
#define CAMSS_CSI0PIX_CLK				153
#define CAMSS_CSI1_CLK					154
#define CAMSS_CSI1_AHB_CLK				155
#define CAMSS_CSI1PHY_CLK				156
#define CAMSS_CSI1RDI_CLK				157
#define CAMSS_CSI1PIX_CLK				158
#define CAMSS_CSI2_CLK					159
#define CAMSS_CSI2_AHB_CLK				160
#define CAMSS_CSI2PHY_CLK				161
#define CAMSS_CSI2RDI_CLK				162
#define CAMSS_CSI2PIX_CLK				163
#define CAMSS_CSI3_CLK					164
#define CAMSS_CSI3_AHB_CLK				165
#define CAMSS_CSI3PHY_CLK				166
#define CAMSS_CSI3RDI_CLK				167
#define CAMSS_CSI3PIX_CLK				168
#define CAMSS_ISPIF_AHB_CLK				169
#define FD_CORE_CLK					170
#define FD_CORE_UAR_CLK					171
#define FD_AHB_CLK					172

/* Block resets */
#define MMAGICAHB_BCR					0
#define MMAGIC_CFG_BCR					1
#define MISC_BCR					2
#define BTO_BCR						3
#define MMAGICAXI_BCR					4
#define MMAGICMAXI_BCR					5
#define DSA_BCR						6
#define MMAGIC_CAMSS_BCR				7
#define THROTTLE_CAMSS_BCR				8
#define SMMU_VFE_BCR					9
#define SMMU_CPP_BCR					10
#define SMMU_JPEG_BCR					11
#define MMAGIC_MDSS_BCR					12
#define THROTTLE_MDSS_BCR				13
#define SMMU_ROT_BCR					14
#define SMMU_MDP_BCR					15
#define MMAGIC_VIDEO_BCR				16
#define THROTTLE_VIDEO_BCR				17
#define SMMU_VIDEO_BCR					18
#define MMAGIC_BIMC_BCR					19
#define VMEM_BCR					20
#define MMSS_RBCPR_BCR					21
#define VIDEO_BCR					22
#define MDSS_BCR					23
#define CAMSS_TOP_BCR					24
#define CAMSS_AHB_BCR					25
#define CAMSS_MICRO_BCR					26
#define CAMSS_CCI_BCR					27
#define CAMSS_PHY0_BCR					28
#define CAMSS_PHY1_BCR					29
#define CAMSS_PHY2_BCR					30
#define CAMSS_CSIPHY0_3P_BCR				31
#define CAMSS_CSIPHY1_3P_BCR				32
#define CAMSS_CSIPHY2_3P_BCR				33
#define CAMSS_JPEG_BCR					34
#define CAMSS_VFE_BCR					35
#define CAMSS_VFE0_BCR					36
#define CAMSS_VFE1_BCR					37
#define CAMSS_CSI_VFE0_BCR				38
#define CAMSS_CSI_VFE1_BCR				39
#define CAMSS_CPP_TOP_BCR				40
#define CAMSS_CPP_BCR					41
#define CAMSS_CSI0_BCR					42
#define CAMSS_CSI0RDI_BCR				43
#define CAMSS_CSI0PIX_BCR				44
#define CAMSS_CSI1_BCR					45
#define CAMSS_CSI1RDI_BCR				46
#define CAMSS_CSI1PIX_BCR				47
#define CAMSS_CSI2_BCR					48
#define CAMSS_CSI2RDI_BCR				49
#define CAMSS_CSI2PIX_BCR				50
#define CAMSS_CSI3_BCR					51
#define CAMSS_CSI3RDI_BCR				52
#define CAMSS_CSI3PIX_BCR				53
#define CAMSS_ISPIF_BCR					54
#define FD_BCR						55
#define MMSS_SPDM_RM_BCR				56

/* Indexes for GDSCs */
#define MMAGIC_VIDEO_GDSC				0
#define MMAGIC_MDSS_GDSC				1
#define MMAGIC_CAMSS_GDSC				2
#define GPU_GDSC					3
#define VENUS_GDSC					4
#define VENUS_CORE0_GDSC				5
#define VENUS_CORE1_GDSC				6
#define CAMSS_GDSC					7
#define VFE0_GDSC					8
#define VFE1_GDSC					9
#define JPEG_GDSC					10
#define CPP_GDSC					11
#define FD_GDSC						12
#define MDSS_GDSC					13
#define GPU_GX_GDSC					14
#define MMAGIC_BIMC_GDSC				15

#endif