/*
 * ARM Ltd. Juno Platform
 *
 * Copyright (c) 2013-2014 ARM Ltd.
 *
 * This file is licensed under a dual GPLv2 or BSD license.
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "ARM Juno development board (r0)";
	compatible = "arm,juno", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &soc_uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&A57_0>;
				};
				core1 {
					cpu = <&A57_1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&A53_0>;
				};
				core1 {
					cpu = <&A53_1>;
				};
				core2 {
					cpu = <&A53_2>;
				};
				core3 {
					cpu = <&A53_3>;
				};
			};
		};

		idle-states {
			entry-method = "arm,psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010000>;
				local-timer-stop;
				entry-latency-us = <300>;
				exit-latency-us = <1200>;
				min-residency-us = <2000>;
			};

			CLUSTER_SLEEP_0: cluster-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x1010000>;
				local-timer-stop;
				entry-latency-us = <400>;
				exit-latency-us = <1200>;
				min-residency-us = <2500>;
			};
		};

		A57_0: cpu@0 {
			compatible = "arm,cortex-a57","arm,armv8";
			reg = <0x0 0x0>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&A57_L2>;
			clocks = <&scpi_dvfs 0>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			sched-energy-costs = <&CPU_COST_A57 &CLUSTER_COST_A57>;
		};

		A57_1: cpu@1 {
			compatible = "arm,cortex-a57","arm,armv8";
			reg = <0x0 0x1>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&A57_L2>;
			clocks = <&scpi_dvfs 0>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			sched-energy-costs = <&CPU_COST_A57 &CLUSTER_COST_A57>;
		};

		A53_0: cpu@100 {
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x100>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
		};

		A53_1: cpu@101 {
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x101>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
		};

		A53_2: cpu@102 {
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x102>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
		};

		A53_3: cpu@103 {
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x103>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
		};

		A57_L2: l2-cache0 {
			compatible = "cache";
		};

		A53_L2: l2-cache1 {
			compatible = "cache";
		};

		/include/ "juno-sched-energy.dtsi"
	};

	pmu_a57 {
		compatible = "arm,cortex-a57-pmu";
		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&A57_0>,
				     <&A57_1>;
	};

	pmu_a53 {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&A53_0>,
				     <&A53_1>,
				     <&A53_2>,
				     <&A53_3>;
	};

	etr@20070000 {
		compatible = "arm,coresight-tmc", "arm,primecell";
		reg = <0 0x20070000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		port {
			etr_in_port: endpoint {
				slave-mode;
				remote-endpoint = <&replicator_out_port1>;
			};
		};
	};

	tpiu@20030000 {
		compatible = "arm,coresight-tpiu", "arm,primecell";
		reg = <0 0x20030000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		port {
			tpiu_in_port: endpoint {
				slave-mode;
				remote-endpoint = <&replicator_out_port0>;
			};
		};
	};

	replicator@20020000 {
		/* non-configurable replicators don't show up on the
		 * AMBA bus.  As such no need to add "arm,primecell".
		 */
		compatible = "arm,coresight-replicator";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* replicator output ports */
			port@0 {
				reg = <0>;
				replicator_out_port0: endpoint {
					remote-endpoint = <&tpiu_in_port>;
				};
			};

			port@1 {
				reg = <1>;
				replicator_out_port1: endpoint {
					remote-endpoint = <&etr_in_port>;
				};
			};

			/* replicator input port */
			port@2 {
				reg = <0>;
				replicator_in_port0: endpoint {
					slave-mode;
					remote-endpoint = <&etf_out_port>;
				};
			};
		};
	};

	etf@20010000 {
		compatible = "arm,coresight-tmc", "arm,primecell";
		reg = <0 0x20010000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* input port */
			port@0 {
				reg = <0>;
				etf_in_port: endpoint {
					slave-mode;
					remote-endpoint =
						<&main_funnel_out_port>;
				};
			};

			/* output port */
			port@1 {
				reg = <0>;
				etf_out_port: endpoint {
					remote-endpoint =
						<&replicator_in_port0>;
				};
			};
		};
	};

	main_funnel@20040000 {
		compatible = "arm,coresight-funnel", "arm,primecell";
		reg = <0 0x20040000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				main_funnel_out_port: endpoint {
					remote-endpoint =
						<&etf_in_port>;
				};
			};

			port@1 {
				reg = <0>;
				main_funnel_in_port0: endpoint {
					slave-mode;
					remote-endpoint =
						<&A72_57_funnel_out_port>;
				};
			};

			port@2 {
				reg = <1>;
				main_funnel_in_port1: endpoint {
					slave-mode;
					remote-endpoint = <&A53_funnel_out_port>;
				};
			};

		};
	};

	A72_57_funnel@220c0000 {
		compatible = "arm,coresight-funnel", "arm,primecell";
		reg = <0 0x220c0000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				A72_57_funnel_out_port: endpoint {
					remote-endpoint =
						<&main_funnel_in_port0>;
				};
			};

			port@1 {
				reg = <0>;
				A72_57_funnel_in_port0: endpoint {
					slave-mode;
					remote-endpoint =
							<&A72_57_etm0_out_port>;
				};
			};

			port@2 {
				reg = <1>;
				A72_57_funnel_in_port1: endpoint {
					slave-mode;
					remote-endpoint =
							<&A72_57_etm1_out_port>;
				};
			};
		};
	};

	A53_funnel@220c0000 {
		compatible = "arm,coresight-funnel", "arm,primecell";
		reg = <0 0x230c0000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				A53_funnel_out_port: endpoint {
					remote-endpoint =
						<&main_funnel_in_port1>;
				};
			};

			port@1 {
				reg = <0>;
				A53_funnel_in_port0: endpoint {
					slave-mode;
					remote-endpoint = <&A53_etm0_out_port>;
				};
			};

			port@2 {
				reg = <1>;
				A53_funnel_in_port1: endpoint {
					slave-mode;
					remote-endpoint = <&A53_etm1_out_port>;
				};
			};
			port@3 {
				reg = <2>;
				A53_funnel_in_port2: endpoint {
					slave-mode;
					remote-endpoint = <&A53_etm2_out_port>;
				};
			};
			port@4 {
				reg = <3>;
				A53_funnel_in_port3: endpoint {
					slave-mode;
					remote-endpoint = <&A53_etm3_out_port>;
				};
			};
		};
	};

	etm@22040000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x22040000 0 0x1000>;

		cpu = <&A57_0>;
		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		port {
			A72_57_etm0_out_port: endpoint {
				remote-endpoint = <&A72_57_funnel_in_port0>;
			};
		};
	};

	etm@22140000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x22140000 0 0x1000>;

		cpu = <&A57_1>;
		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		port {
			A72_57_etm1_out_port: endpoint {
				remote-endpoint = <&A72_57_funnel_in_port1>;
			};
		};
	};

	etm@23040000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x23040000 0 0x1000>;

		cpu = <&A53_0>;
		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		port {
			A53_etm0_out_port: endpoint {
				remote-endpoint = <&A53_funnel_in_port0>;
			};
		};
	};

	etm@23140000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x23140000 0 0x1000>;

		cpu = <&A53_1>;
		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		port {
			A53_etm1_out_port: endpoint {
				remote-endpoint = <&A53_funnel_in_port1>;
			};
		};
	};

	etm@23240000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x23240000 0 0x1000>;

		cpu = <&A53_2>;
		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		port {
			A53_etm2_out_port: endpoint {
				remote-endpoint = <&A53_funnel_in_port2>;
			};
		};
	};

	etm@23340000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x23340000 0 0x1000>;

		cpu = <&A53_3>;
		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		port {
			A53_etm3_out_port: endpoint {
				remote-endpoint = <&A53_funnel_in_port3>;
			};
		};
	};

	#include "juno-base.dtsi"
};