/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

&soc {
	pil_gpu: qcom,kgsl-hyp {
		compatible = "qcom,pil-tz-generic";
		qcom,pas-id = <13>;
		qcom,firmware-name = "a508_zap";
	};

	msm_bus: qcom,kgsl-busmon{
		label = "kgsl-busmon";
		compatible = "qcom,kgsl-busmon";
	};

	gpubw: qcom,gpubw {
		compatible = "qcom,devbw";
		governor = "bw_vbif";
		qcom,src-dst-ports = <26 512>;
		/*
		 * active-only flag is used while registering the bus
		 * governor. It helps release the bus vote when the CPU
		 * subsystem is inactive
		 */
		qcom,active-only;
		/*
		 * IB votes in MBPS, derived using below formula
		 * IB = (DDR frequency * DDR bus width in Bytes * Dual rate)
		 * Note: IB vote is per DDR channel vote
		 */
		qcom,bw-tbl =
			<     0 /*  off     */ >,
			<   381 /*  100 MHz */ >,
			<   572 /*  150 MHz */ >,
			<   762 /*  200 MHz */ >,
			<  1144 /*  300 MHz */ >,
			<  1571 /*  412 MHz */ >,
			<  2086 /*  547 MHz */ >,
			<  2597 /*  681 MHz */ >,
			<  2929 /*  768 MHz */ >,
			<  3879 /*  1017 MHz */ >,
			<  4943 /*  1296 MHz */ >,
			<  5161 /*  1353 MHz */ >;
	};

	msm_gpu: qcom,kgsl-3d0@5000000 {
		label = "kgsl-3d0";
		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
		status = "ok";
		reg = <0x5000000 0x40000
			0x780000 0x6220>;
		reg-names = "kgsl_3d0_reg_memory", "qfprom_memory";
		interrupts = <0 300 0>;
		interrupt-names = "kgsl_3d0_irq";
		qcom,id = <0>;

		qcom,chipid = <0x05000800>;

		qcom,initial-pwrlevel = <5>;

		/* <HZ/12> */
		qcom,idle-timeout = <80>;

		qcom,highest-bank-bit = <14>;

		/* size in bytes */
		qcom,snapshot-size = <1048576>;

		clocks = <&clock_gfx GPUCC_GFX3D_CLK>,
			<&clock_gcc GCC_GPU_CFG_AHB_CLK>,
			<&clock_gfx GPUCC_RBBMTIMER_CLK>,
			<&clock_gcc GCC_GPU_BIMC_GFX_CLK>,
			<&clock_gcc GCC_BIMC_GFX_CLK>,
			<&clock_gpu GPUCC_RBCPR_CLK>;

		clock-names = "core_clk", "iface_clk", "rbbmtimer_clk",
			"mem_clk", "alt_mem_iface_clk", "rbcpr_clk";

		/* Bus Scale Settings */
		qcom,gpubw-dev = <&gpubw>;
		qcom,bus-control;
		/* GPU to BIMC bus width, VBIF data transfer in 1 cycle */
		qcom,bus-width = <32>;
		qcom,msm-bus,name = "grp3d";
		qcom,msm-bus,num-cases = <12>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
				<26 512 0 0>,
				<26 512 0 400000>,     /*  1 bus=100  */
				<26 512 0 600000>,     /*  2 bus=150  */
				<26 512 0 800000>,     /*  3 bus=200  */
				<26 512 0 1200000>,    /*  4 bus=300  */
				<26 512 0 1648000>,    /*  5 bus=412  */
				<26 512 0 2188000>,    /*  6 bus=547  */
				<26 512 0 2724000>,    /*  7 bus=681  */
				<26 512 0 3072000>,    /*  8 bus=768  */
				<26 512 0 4068000>,    /*  9 bus=1017 */
				<26 512 0 5184000>,    /* 10 bus=1296 */
				<26 512 0 5412000>;    /* 11 bus=1353 */

		/* GDSC regulator names */
		regulator-names = "vddcx", "vdd";
		/* GDSC oxili regulators */
		vddcx-supply = <&gdsc_gpu_cx>;
		vdd-supply = <&gdsc_gpu_gx>;

		/* CPU latency parameter */
		qcom,pm-qos-active-latency = <424>;
		qcom,pm-qos-wakeup-latency = <424>;

		/* Quirks */
		qcom,gpu-quirk-dp2clockgating-disable;
		qcom,gpu-quirk-lmloadkill-disable;

		/* Enable context aware freq. scaling */
		qcom,enable-ca-jump;

		/* Context aware jump busy penalty in us */
		qcom,ca-busy-penalty = <12000>;

		/* Context aware jump target power level */
		qcom,ca-target-pwrlevel = <4>;

		qcom,gpu-speed-bin = <0x41a0 0x1fe00000 21>;

		/* Enable midframe sampling */
		qcom,enable-midframe-timer;

		/* GPU Mempools */
		qcom,gpu-mempools {
			#address-cells= <1>;
			#size-cells = <0>;
			compatible = "qcom,gpu-mempools";

			qcom,mempool-max-pages = <32768>;

			/* 4K Page Pool configuration */
			qcom,gpu-mempool@0 {
				reg = <0>;
				qcom,mempool-page-size = <4096>;
			};
			/* 64K Page Pool configuration */
			qcom,gpu-mempool@1 {
				reg = <1>;
				qcom,mempool-page-size  = <65536>;
				qcom,mempool-allocate;
			};
		};

		/*
		 * Speed-bin zero is default speed bin.
		 * For rest of the speed bins, speed-bin value
		 * is calulated as FMAX/4.8 MHz round up to zero
		 * decimal places.
		 */
		qcom,gpu-pwrlevel-bins {
			#address-cells = <1>;
			#size-cells = <0>;

			compatible="qcom,gpu-pwrlevel-bins";

			qcom,gpu-pwrlevels-0 {
				#address-cells = <1>;
				#size-cells = <0>;

				qcom,speed-bin = <0>;

				qcom,initial-pwrlevel = <5>;

				/* TURBO */
				qcom,gpu-pwrlevel@0 {
					reg = <0>;
					qcom,gpu-freq = <775000000>;
					qcom,bus-freq = <11>;
					qcom,bus-min = <10>;
					qcom,bus-max = <11>;
				};

				/* TURBO */
				qcom,gpu-pwrlevel@1 {
					reg = <1>;
					qcom,gpu-freq = <700000000>;
					qcom,bus-freq = <10>;
					qcom,bus-min = <9>;
					qcom,bus-max = <11>;
				};

				/* NOM_L1 */
				qcom,gpu-pwrlevel@2 {
					reg = <2>;
					qcom,gpu-freq = <647000000>;
					qcom,bus-freq = <9>;
					qcom,bus-min = <8>;
					qcom,bus-max = <9>;
				};

				/* NOM */
				qcom,gpu-pwrlevel@3 {
					reg = <3>;
					qcom,gpu-freq = <588000000>;
					qcom,bus-freq = <9>;
					qcom,bus-min = <7>;
					qcom,bus-max = <9>;
				};

				/* SVS_L1 */
				qcom,gpu-pwrlevel@4 {
					reg = <4>;
					qcom,gpu-freq = <465000000>;
					qcom,bus-freq = <8>;
					qcom,bus-min = <6>;
					qcom,bus-max = <9>;
				};

				/* SVS */
				qcom,gpu-pwrlevel@5 {
					reg = <5>;
					qcom,gpu-freq = <370000000>;
					qcom,bus-freq = <5>;
					qcom,bus-min = <4>;
					qcom,bus-max = <7>;
				};

				/* Low SVS */
				qcom,gpu-pwrlevel@6 {
					reg = <6>;
					qcom,gpu-freq = <240000000>;
					qcom,bus-freq = <3>;
					qcom,bus-min = <3>;
					qcom,bus-max = <5>;
				};

				/* Min SVS */
				qcom,gpu-pwrlevel@7 {
					reg = <7>;
					qcom,gpu-freq = <160000000>;
					qcom,bus-freq = <3>;
					qcom,bus-min = <2>;
					qcom,bus-max = <4>;
				};

				/* XO */
				qcom,gpu-pwrlevel@8 {
					reg = <8>;
					qcom,gpu-freq = <19200000>;
					qcom,bus-freq = <0>;
					qcom,bus-min = <0>;
					qcom,bus-max = <0>;
				};
			};

			qcom,gpu-pwrlevels-1 {
				#address-cells = <1>;
				#size-cells = <0>;

				qcom,speed-bin = <162>;

				qcom,initial-pwrlevel = <5>;

				/* TURBO */
				qcom,gpu-pwrlevel@0 {
					reg = <0>;
					qcom,gpu-freq = <775000000>;
					qcom,bus-freq = <11>;
					qcom,bus-min = <10>;
					qcom,bus-max = <11>;
				};

				/* TURBO */
				qcom,gpu-pwrlevel@1 {
					reg = <1>;
					qcom,gpu-freq = <700000000>;
					qcom,bus-freq = <10>;
					qcom,bus-min = <9>;
					qcom,bus-max = <11>;
				};

				/* NOM_L1 */
				qcom,gpu-pwrlevel@2 {
					reg = <2>;
					qcom,gpu-freq = <647000000>;
					qcom,bus-freq = <9>;
					qcom,bus-min = <8>;
					qcom,bus-max = <9>;
				};

				/* NOM */
				qcom,gpu-pwrlevel@3 {
					reg = <3>;
					qcom,gpu-freq = <588000000>;
					qcom,bus-freq = <9>;
					qcom,bus-min = <7>;
					qcom,bus-max = <9>;
				};

				/* SVS_L1 */
				qcom,gpu-pwrlevel@4 {
					reg = <4>;
					qcom,gpu-freq = <465000000>;
					qcom,bus-freq = <8>;
					qcom,bus-min = <6>;
					qcom,bus-max = <9>;
				};

				/* SVS */
				qcom,gpu-pwrlevel@5 {
					reg = <5>;
					qcom,gpu-freq = <370000000>;
					qcom,bus-freq = <5>;
					qcom,bus-min = <4>;
					qcom,bus-max = <7>;
				};

				/* Low SVS */
				qcom,gpu-pwrlevel@6 {
					reg = <6>;
					qcom,gpu-freq = <240000000>;
					qcom,bus-freq = <3>;
					qcom,bus-min = <3>;
					qcom,bus-max = <5>;
				};

				/* Min SVS */
				qcom,gpu-pwrlevel@7 {
					reg = <7>;
					qcom,gpu-freq = <160000000>;
					qcom,bus-freq = <3>;
					qcom,bus-min = <2>;
					qcom,bus-max = <4>;
				};

				/* XO */
				qcom,gpu-pwrlevel@8 {
					reg = <8>;
					qcom,gpu-freq = <19200000>;
					qcom,bus-freq = <0>;
					qcom,bus-min = <0>;
					qcom,bus-max = <0>;
				};
			};

			qcom,gpu-pwrlevels-2 {
				#address-cells = <1>;
				#size-cells = <0>;

				qcom,speed-bin = <146>;

				qcom,initial-pwrlevel = <4>;

				/* TURBO */
				qcom,gpu-pwrlevel@0 {
					reg = <0>;
					qcom,gpu-freq = <700000000>;
					qcom,bus-freq = <11>;
					qcom,bus-min = <10>;
					qcom,bus-max = <11>;
				};

				/* NOM_L1 */
				qcom,gpu-pwrlevel@1 {
					reg = <1>;
					qcom,gpu-freq = <647000000>;
					qcom,bus-freq = <9>;
					qcom,bus-min = <8>;
					qcom,bus-max = <9>;
				};

				/* NOM */
				qcom,gpu-pwrlevel@2 {
					reg = <2>;
					qcom,gpu-freq = <588000000>;
					qcom,bus-freq = <9>;
					qcom,bus-min = <7>;
					qcom,bus-max = <9>;
				};

				/* SVS_L1 */
				qcom,gpu-pwrlevel@3 {
					reg = <3>;
					qcom,gpu-freq = <465000000>;
					qcom,bus-freq = <8>;
					qcom,bus-min = <6>;
					qcom,bus-max = <9>;
				};

				/* SVS */
				qcom,gpu-pwrlevel@4 {
					reg = <4>;
					qcom,gpu-freq = <370000000>;
					qcom,bus-freq = <5>;
					qcom,bus-min = <4>;
					qcom,bus-max = <7>;
				};

				/* Low SVS */
				qcom,gpu-pwrlevel@5 {
					reg = <5>;
					qcom,gpu-freq = <240000000>;
					qcom,bus-freq = <3>;
					qcom,bus-min = <3>;
					qcom,bus-max = <5>;
				};

				/* Min SVS */
				qcom,gpu-pwrlevel@6 {
					reg = <6>;
					qcom,gpu-freq = <160000000>;
					qcom,bus-freq = <3>;
					qcom,bus-min = <2>;
					qcom,bus-max = <4>;
				};

				/* XO */
				qcom,gpu-pwrlevel@7 {
					reg = <7>;
					qcom,gpu-freq = <19200000>;
					qcom,bus-freq = <0>;
					qcom,bus-min = <0>;
					qcom,bus-max = <0>;
				};
			};

			qcom,gpu-pwrlevels-3 {
				#address-cells = <1>;
				#size-cells = <0>;

				qcom,speed-bin = <135>;

				qcom,initial-pwrlevel = <3>;

				/* NOM_L1 */
				qcom,gpu-pwrlevel@0 {
					reg = <0>;
					qcom,gpu-freq = <647000000>;
					qcom,bus-freq = <11>;
					qcom,bus-min = <10>;
					qcom,bus-max = <11>;
				};

				/* NOM */
				qcom,gpu-pwrlevel@1 {
					reg = <1>;
					qcom,gpu-freq = <588000000>;
					qcom,bus-freq = <9>;
					qcom,bus-min = <7>;
					qcom,bus-max = <9>;
				};

				/* SVS_L1 */
				qcom,gpu-pwrlevel@2 {
					reg = <2>;
					qcom,gpu-freq = <465000000>;
					qcom,bus-freq = <8>;
					qcom,bus-min = <6>;
					qcom,bus-max = <9>;
				};

				/* SVS */
				qcom,gpu-pwrlevel@3 {
					reg = <3>;
					qcom,gpu-freq = <370000000>;
					qcom,bus-freq = <5>;
					qcom,bus-min = <4>;
					qcom,bus-max = <7>;
				};

				/* Low SVS */
				qcom,gpu-pwrlevel@4 {
					reg = <4>;
					qcom,gpu-freq = <240000000>;
					qcom,bus-freq = <3>;
					qcom,bus-min = <3>;
					qcom,bus-max = <5>;
				};

				/* Min SVS */
				qcom,gpu-pwrlevel@5 {
					reg = <5>;
					qcom,gpu-freq = <160000000>;
					qcom,bus-freq = <3>;
					qcom,bus-min = <2>;
					qcom,bus-max = <4>;
				};

				/* XO */
				qcom,gpu-pwrlevel@6 {
					reg = <6>;
					qcom,gpu-freq = <19200000>;
					qcom,bus-freq = <0>;
					qcom,bus-min = <0>;
					qcom,bus-max = <0>;
				};
			};
		};
	};

	kgsl_msm_iommu: qcom,kgsl-iommu {
		compatible = "qcom,kgsl-smmu-v2";

		reg = <0x05040000 0x10000>;
		qcom,protect = <0x40000 0x10000>;
		qcom,micro-mmu-control = <0x6000>;

		clocks = <&clock_gcc GCC_GPU_CFG_AHB_CLK>,
			<&clock_gcc GCC_GPU_BIMC_GFX_CLK>,
			<&clock_gcc GCC_BIMC_GFX_CLK>;

		clock-names = "iface_clk", "mem_clk", "alt_mem_iface_clk";

		qcom,secure_align_mask = <0xfff>;
		qcom,retention;
		qcom,hyp_secure_alloc;

		gfx3d_user: gfx3d_user {
			compatible = "qcom,smmu-kgsl-cb";
			label = "gfx3d_user";
			iommus = <&kgsl_smmu 0>;
			qcom,gpu-offset = <0x48000>;
		};

		gfx3d_secure: gfx3d_secure {
			compatible = "qcom,smmu-kgsl-cb";
			iommus = <&kgsl_smmu 2>;
		};
	};
};