From b0dfb38811ed601bca0f52a2425fa4eae760f9aa Mon Sep 17 00:00:00 2001 From: Jordan Crouse Date: Mon, 13 Feb 2017 10:14:23 -0700 Subject: drm/msm: Add a property for the GMEM base Return the base address of GMEM in virtual address space as a parameter. Change-Id: Ic0dedbad3b849052313e4673efcf6c22bc81f21f Signed-off-by: Jordan Crouse --- include/uapi/drm/msm_drm.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index 587d35ce1638..20ef9bc424f3 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -54,6 +54,7 @@ struct drm_msm_timespec { #define MSM_PARAM_CHIP_ID 0x03 #define MSM_PARAM_MAX_FREQ 0x04 #define MSM_PARAM_TIMESTAMP 0x05 +#define MSM_PARAM_GMEM_BASE 0x06 struct drm_msm_param { __u32 pipe; /* in, MSM_PIPE_x */ -- cgit v1.2.3 From 378583458fa167277b15d145dccce253459393ec Mon Sep 17 00:00:00 2001 From: Jordan Crouse Date: Mon, 13 Feb 2017 10:14:24 -0700 Subject: drm/msm: Add support for multiple ringbuffers Add the infrastructure for supporting multiple ringbuffers. Change-Id: Ic0dedbada90ec5c4c8074ffce33c3fe275b0cda1 Signed-off-by: Jordan Crouse --- include/uapi/drm/msm_drm.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index 20ef9bc424f3..be4a18c0712c 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -40,6 +40,15 @@ #define MSM_PIPE_2D1 0x02 #define MSM_PIPE_3D0 0x10 +/* The pipe-id just uses the lower bits, so can be OR'd with flags in + * the upper 16 bits (which could be extended further, if needed, maybe + * we extend/overload the pipe-id some day to deal with multiple rings, + * but even then I don't think we need the full lower 16 bits). + */ +#define MSM_PIPE_ID_MASK 0xffff +#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) +#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) + /* timeouts are specified in clock-monotonic absolute times (to simplify * restarting interrupted ioctls). The following struct is logically the * same as 'struct timespec' but 32/64b ABI safe. @@ -178,12 +187,18 @@ struct drm_msm_gem_submit_bo { __u64 presumed; /* in/out, presumed buffer address */ }; +/* Valid submit ioctl flags: */ +#define MSM_SUBMIT_RING_MASK 0x000F0000 +#define MSM_SUBMIT_RING_SHIFT 16 + +#define MSM_SUBMIT_FLAGS (MSM_SUBMIT_RING_MASK) + /* Each cmdstream submit consists of a table of buffers involved, and * one or more cmdstream buffers. This allows for conditional execution * (context-restore), and IB buffers needed for per tile/bin draw cmds. */ struct drm_msm_gem_submit { - __u32 pipe; /* in, MSM_PIPE_x */ + __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */ __u32 fence; /* out */ __u32 nr_bos; /* in, number of submit_bo's */ __u32 nr_cmds; /* in, number of submit_cmd's */ -- cgit v1.2.3 From 425372c0ba8e332995e05be0ba6ec513192512d2 Mon Sep 17 00:00:00 2001 From: Jordan Crouse Date: Mon, 13 Feb 2017 10:14:26 -0700 Subject: drm/msm: Set IOMMU map attributes Remove the IOMMU_WRITE bit from buffer objects that are marked MSM_BO_GPU_READONLY. Add a new flag (MSM_BO_PRIVILEGED) to pass through IOMMU_PRIV for those IOMMU targets that support it. Change-Id: Ic0dedbad8d9d3f461a47ea093fad3fdd90f46535 Signed-off-by: Jordan Crouse --- include/uapi/drm/msm_drm.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index be4a18c0712c..d2f19ac6f536 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -77,6 +77,7 @@ struct drm_msm_param { #define MSM_BO_SCANOUT 0x00000001 /* scanout capable */ #define MSM_BO_GPU_READONLY 0x00000002 +#define MSM_BO_PRIVILEGED 0x00000004 #define MSM_BO_CACHE_MASK 0x000f0000 /* cache modes */ #define MSM_BO_CACHED 0x00010000 -- cgit v1.2.3 From 663d4c0a64159fb15cc0817424081695901f39cb Mon Sep 17 00:00:00 2001 From: Jordan Crouse Date: Mon, 13 Feb 2017 10:14:28 -0700 Subject: iommu/arm-smmu: Add support for TTBR1 Allow a domain to opt into allocating and maintaining a TTBR1 pagetable. The size of the TTBR1 region will be the same as the TTBR0 size with the sign extension bit set on the highest bit in the region. By example, given a TTBR0/TTBR1 virtual address range of 36 bits the memory map will look like this: TTBR0 [0x000000000:0x7FFFFFFFF] TTBR1 [0x800000000:0xFFFFFFFFF] The map/unmap operations will automatically use the appropriate pagetable for the given iova. Change-Id: Ic0dedbad2b2c58cd9c47ce31356472e0463d4228 Signed-off-by: Jordan Crouse --- include/linux/iommu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 1b3f20e8fb74..c4c25651ff21 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -136,6 +136,7 @@ enum iommu_attr { DOMAIN_ATTR_EARLY_MAP, DOMAIN_ATTR_PAGE_TABLE_IS_COHERENT, DOMAIN_ATTR_PAGE_TABLE_FORCE_COHERENT, + DOMAIN_ATTR_ENABLE_TTBR1, DOMAIN_ATTR_MAX, }; -- cgit v1.2.3