From 54f161d263e0488ffcb5aca473b6d8672a599a8a Mon Sep 17 00:00:00 2001 From: Jayachandran Sreekumaran Date: Tue, 3 Jul 2018 14:11:54 +0530 Subject: cnss2: cnss api update for genoa pcie cnss api update for genoa pcie to pass the memory information for read index update. Change-Id: Ic6a96bef1dfacdc78bc127cc2570e148e9cd4baf CRs-fixed: 2272072 Signed-off-by: Jayachandran Sreekumaran --- include/net/cnss2.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/net/cnss2.h b/include/net/cnss2.h index 53f73d436752..3a8b503c1938 100644 --- a/include/net/cnss2.h +++ b/include/net/cnss2.h @@ -115,6 +115,11 @@ struct cnss_shadow_reg_v2_cfg { u32 addr; }; +struct cnss_rri_over_ddr_cfg { + u32 base_addr_low; + u32 base_addr_high; +}; + struct cnss_wlan_enable_cfg { u32 num_ce_tgt_cfg; struct cnss_ce_tgt_pipe_cfg *ce_tgt_cfg; @@ -124,6 +129,8 @@ struct cnss_wlan_enable_cfg { struct cnss_shadow_reg_cfg *shadow_reg_cfg; u32 num_shadow_reg_v2_cfg; struct cnss_shadow_reg_v2_cfg *shadow_reg_v2_cfg; + bool rri_over_ddr_cfg_valid; + struct cnss_rri_over_ddr_cfg rri_over_ddr_cfg; }; enum cnss_driver_mode { -- cgit v1.2.3