From ae8eef27c36e4f781982da17fd2feabd8156e941 Mon Sep 17 00:00:00 2001 From: Devesh Jhunjhunwala Date: Fri, 18 Mar 2016 12:40:31 -0700 Subject: clk: msm: alpha-pll: Add support for dynamic programming of PLLs Update the alpha_pll_set_rate function to support dynamically updating the pll frequency if the dynamic_update flag is defined for the pll. Also set the HW_UPDATE_BYPASS_LOGIC bit for these plls during handoff. CRs-Fixed: 988270 Change-Id: I7f3527ef45cf68c3f5c41e04bfdd3ede55bbaa4d Signed-off-by: Devesh Jhunjhunwala --- include/soc/qcom/clock-alpha-pll.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/soc/qcom/clock-alpha-pll.h b/include/soc/qcom/clock-alpha-pll.h index b5a34b4cecb5..0b5329ba817c 100644 --- a/include/soc/qcom/clock-alpha-pll.h +++ b/include/soc/qcom/clock-alpha-pll.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -66,6 +66,12 @@ struct alpha_pll_clk { bool slew; bool no_prepared_reconfig; + /* some PLLs support dynamically updating their rate + * without disabling the PLL first. Set this flag + * to enable this support. + */ + bool dynamic_update; + /* * Some chipsets need the offline request bit to be * cleared on a second write to the register, even though -- cgit v1.2.3