From f47dba1b3132907fdafe320ecd052d6b4e239d60 Mon Sep 17 00:00:00 2001 From: Asutosh Das Date: Wed, 9 Dec 2015 10:48:18 +0530 Subject: mmc: core: support DDR52 bus-speed during eMMC clock scaling Add support for DDR52 bus-speed mode during clock scaling. The reason for this change is DDR52 can be supported at SVS mode. Change-Id: I68e5fca57ae5cbc154f5dd7001df368900cb3f57 Signed-off-by: Asutosh Das --- drivers/mmc/core/mmc.c | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index fda54ff43720..39bf4455d16a 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -1550,6 +1550,24 @@ out: return ret; } +static int mmc_select_hs_ddr52(struct mmc_host *host) +{ + int err; + + mmc_select_hs(host->card); + mmc_set_clock(host, MMC_HIGH_52_MAX_DTR); + err = mmc_select_bus_width(host->card); + if (err < 0) { + pr_err("%s: %s: select_bus_width failed(%d)\n", + mmc_hostname(host), __func__, err); + return err; + } + + err = mmc_select_hs_ddr(host->card); + + return err; +} + /* * Scale down from HS400 to HS in order to allow frequency change. * This is needed for cards that doesn't support changing frequency in HS400 @@ -1561,10 +1579,20 @@ static int mmc_scale_low(struct mmc_host *host, unsigned long freq) mmc_set_timing(host, MMC_TIMING_LEGACY); mmc_set_clock(host, MMC_HIGH_26_MAX_DTR); + if (host->clk_scaling.lower_bus_speed_mode & + MMC_SCALING_LOWER_DDR52_MODE) { + err = mmc_select_hs_ddr52(host); + if (err) + pr_err("%s: %s: failed to switch to DDR52: err: %d\n", + mmc_hostname(host), __func__, err); + else + return err; + } + err = mmc_select_hs(host->card); if (err) { - pr_err("%s: %s: selecting HS (52Mhz) failed (%d)\n", - mmc_hostname(host), __func__, err); + pr_err("%s: %s: scaling low: failed (%d)\n", + mmc_hostname(host), __func__, err); return err; } -- cgit v1.2.3