From 9ef3d654f27ba9c3d17cb7465f7f79880996d929 Mon Sep 17 00:00:00 2001 From: Jack Pham Date: Wed, 29 Mar 2017 18:59:37 -0700 Subject: qcom: smb-lib: Disable HW trigger when forcing sink-only mode Due to an existing HW workaround, the UFP_EN_CMD bit may end up getting cleared even after having been set. The result of this is the Type-C state machine returns to DRP behavior despite SW intention to force sink mode, such as PR Swap or Try.SNK. Temporarily disable this particular HW trigger whenever the typec_power_role property is getting set to sink-only mode, and restore it when leaving sink mode. Change-Id: I21e840bfeee3ad88b0562645378b1fea200e3803 Signed-off-by: Jack Pham Signed-off-by: Abhijeet Dharmapurikar --- drivers/power/supply/qcom/smb-lib.c | 16 ++++++++++++++++ drivers/power/supply/qcom/smb-reg.h | 2 ++ 2 files changed, 18 insertions(+) (limited to 'drivers') diff --git a/drivers/power/supply/qcom/smb-lib.c b/drivers/power/supply/qcom/smb-lib.c index 50af1087278a..ba846351f186 100644 --- a/drivers/power/supply/qcom/smb-lib.c +++ b/drivers/power/supply/qcom/smb-lib.c @@ -2477,6 +2477,22 @@ int smblib_set_prop_typec_power_role(struct smb_charger *chg, return -EINVAL; } + if (power_role == UFP_EN_CMD_BIT) { + /* disable PBS workaround when forcing sink mode */ + rc = smblib_write(chg, TM_IO_DTEST4_SEL, 0x0); + if (rc < 0) { + smblib_err(chg, "Couldn't write to TM_IO_DTEST4_SEL rc=%d\n", + rc); + } + } else { + /* restore it back to 0xA5 */ + rc = smblib_write(chg, TM_IO_DTEST4_SEL, 0xA5); + if (rc < 0) { + smblib_err(chg, "Couldn't write to TM_IO_DTEST4_SEL rc=%d\n", + rc); + } + } + rc = smblib_masked_write(chg, TYPE_C_INTRPT_ENB_SOFTWARE_CTRL_REG, TYPEC_POWER_ROLE_CMD_MASK, power_role); if (rc < 0) { diff --git a/drivers/power/supply/qcom/smb-reg.h b/drivers/power/supply/qcom/smb-reg.h index f7c13390d477..b79060094cf6 100644 --- a/drivers/power/supply/qcom/smb-reg.h +++ b/drivers/power/supply/qcom/smb-reg.h @@ -1019,6 +1019,8 @@ enum { #define CFG_BUCKBOOST_FREQ_SELECT_BUCK_REG (MISC_BASE + 0xA0) #define CFG_BUCKBOOST_FREQ_SELECT_BOOST_REG (MISC_BASE + 0xA1) +#define TM_IO_DTEST4_SEL (MISC_BASE + 0xE9) + /* CHGR FREQ Peripheral registers */ #define FREQ_CLK_DIV_REG (CHGR_FREQ_BASE + 0x50) -- cgit v1.2.3