From 10287fa85354ab3645707ee3eccfefbbd536407d Mon Sep 17 00:00:00 2001
From: Mitchel Humpherys <mitchelh@codeaurora.org>
Date: Tue, 9 Feb 2016 15:25:05 -0800
Subject: ARM: dts: msm: Clean up SMMU interrupts on 8996

We're currently registering for some interrupts that don't exist, and
we're not registering for some interrupts that we should be.  This
results in error messages like:

    d80000.arm,smmu-jpeg: found 4 context interrupt(s) but have \
        3 context banks. assuming 3 context interrupts.
    b40000.arm,smmu-kgsl: found 4 context interrupt(s) but have \
        2 context banks. assuming 2 context interrupts.

This could also result in us missing some interrupts.

Clean all of these up based on the interrupt information from the
hardware docs.

CRs-Fixed: 975201
Change-Id: I33e309ecb700bdead6a0a82a231f3d199c3d34f0
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
---
 arch/arm/boot/dts/qcom/msm-arm-smmu-8996.dtsi | 51 +++++++--------------------
 1 file changed, 13 insertions(+), 38 deletions(-)

(limited to 'arch')

diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-8996.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-8996.dtsi
index cf22be75c9dc..e1c2dd8bde6a 100644
--- a/arch/arm/boot/dts/qcom/msm-arm-smmu-8996.dtsi
+++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-8996.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -25,7 +25,8 @@
 		<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+		<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+		<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
 	vdd-supply = <&gdsc_aggre0_noc>;
 	clocks = <&clock_gcc clk_gcc_smmu_aggre0_axi_clk>,
 		<&clock_gcc clk_gcc_smmu_aggre0_ahb_clk>;
@@ -43,11 +44,7 @@
 		<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
+		<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>;
 	#iommu-cells = <1>;
 	clocks = <&clock_gcc clk_aggre1_noc_clk>;
 	clock-names = "smmu_aggre1_noc_clk";
@@ -67,11 +64,7 @@
 		<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+		<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
 	#iommu-cells = <1>;
 	clocks = <&clock_gcc clk_aggre2_noc_clk>;
 	clock-names = "smmu_aggre2_noc_clk";
@@ -95,11 +88,7 @@
 		<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
+		<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
 	vdd-supply = <&gdsc_hlos1_vote_lpass_adsp>;
 	clocks = <&clock_gcc clk_hlos1_vote_lpass_adsp_smmu_clk>;
 	clock-names = "lpass_q6_smmu_clocks";
@@ -115,8 +104,7 @@
 	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+		<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 	vdd-supply = <&gdsc_mmagic_camss>;
 	clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
 		<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>,
@@ -138,9 +126,7 @@
 	#global-interrupts = <1>;
 	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+		<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
 	vdd-supply = <&gdsc_mmagic_camss>;
 	clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
 		<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>,
@@ -163,8 +149,7 @@
 	interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+		<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 	vdd-supply = <&gdsc_mmagic_camss>;
 	clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
 		<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>,
@@ -190,11 +175,7 @@
 		<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+		<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 	vdd-supply = <&gdsc_mmagic_video>;
 	clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
 		<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>,
@@ -216,9 +197,7 @@
 	#global-interrupts = <1>;
 	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
+		<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
 	vdd-supply = <&gdsc_mmagic_mdss>;
 	clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
 		<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>,
@@ -239,9 +218,7 @@
 	#global-interrupts = <1>;
 	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>;
+		<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
 	vdd-supply = <&gdsc_mmagic_mdss>;
 	clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
 		<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>,
@@ -263,9 +240,7 @@
 	#global-interrupts = <1>;
 	interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
 		<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
-		<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+		<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
 	vdd-supply = <&gdsc_gpu>;
 	clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
 		<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>,
-- 
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