From 6dbc7675bc6332e9fde918faa2a1b70d625234e3 Mon Sep 17 00:00:00 2001 From: Ajay Agarwal Date: Wed, 1 Nov 2017 11:20:03 +0530 Subject: USB: dwc3: gadget: Fix TxFIFO resizing logic The TxFIFO RAM start address for some USB controller might be non-zero. The current FIFO resizing logic in place always considers that this start address is 0x0000 and writes the RAM start address for subsequent TxFIFOs with the last FIFO depth only, leading to the controller not functioning properly. To make the controller work, start address of GTXFIFOSIZ(#n) should be written with the start address of GTXFIFOSIZ(0) + last FIFO depth. Fix the resizing logic accordingly. Change-Id: Ia83edef7165b980828f2a43832493be2349ae0dc Signed-off-by: Ajay Agarwal --- drivers/usb/dwc3/gadget.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index b9c5c9ba8419..48bfe2aaef1a 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -207,7 +207,8 @@ int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc, struct dwc3_ep *dep) tmp = ((max_packet + mdwidth) * mult) + mdwidth; fifo_size = DIV_ROUND_UP(tmp, mdwidth); dep->fifo_depth = fifo_size; - fifo_size |= (dwc->last_fifo_depth << 16); + fifo_size |= (dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0)) & 0xffff0000) + + (dwc->last_fifo_depth << 16); dwc->last_fifo_depth += (fifo_size & 0xffff); dev_dbg(dwc->dev, "%s ep_num:%d last_fifo_depth:%04x fifo_depth:%d\n", -- cgit v1.2.3