From a53de8141c46c2314ab337f441296bdc7f75972e Mon Sep 17 00:00:00 2001 From: Sayali Lokhande Date: Fri, 17 Mar 2017 18:23:44 +0530 Subject: ARM: dts: msm: Add DDR52 bus speed mode for SDM660 SDCC is running at NOM during 4K video playback test case which is causing power regression. Fix this by adding DDR52 lower bus speed mode in clock scaling. With this change sdcc is able to run in low power mode(SVS) and hence improving power savings. Change-Id: I99e03bea142e5377ee7c12c29a31631c1b4dabed Signed-off-by: Sayali Lokhande --- arch/arm/boot/dts/qcom/sdm660-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom/sdm660-common.dtsi b/arch/arm/boot/dts/qcom/sdm660-common.dtsi index a9bf6fdae72a..fbe6d1d8cc74 100644 --- a/arch/arm/boot/dts/qcom/sdm660-common.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-common.dtsi @@ -518,6 +518,8 @@ qcom,ice-clk-rates = <300000000 75000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + status = "disabled"; }; -- cgit v1.2.3